bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
Blue Swirl | 5b6dd86 | 2012-12-02 16:04:43 +0000 | [diff] [blame] | 2 | * Virtual page mapping |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 18 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 19 | #include "config.h" |
Stefan Weil | 777872e | 2014-02-23 18:02:08 +0100 | [diff] [blame] | 20 | #ifndef _WIN32 |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 21 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 22 | #include <sys/mman.h> |
| 23 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 24 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 25 | #include "qemu-common.h" |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 26 | #include "cpu.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 27 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 28 | #include "hw/hw.h" |
Michael S. Tsirkin | 4485bd2 | 2015-03-11 07:56:34 +0100 | [diff] [blame] | 29 | #if !defined(CONFIG_USER_ONLY) |
Marcel Apfelbaum | 47c8ca5 | 2015-02-04 17:43:54 +0200 | [diff] [blame] | 30 | #include "hw/boards.h" |
Michael S. Tsirkin | 4485bd2 | 2015-03-11 07:56:34 +0100 | [diff] [blame] | 31 | #endif |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 32 | #include "hw/qdev.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 33 | #include "qemu/osdep.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 34 | #include "sysemu/kvm.h" |
Markus Armbruster | 2ff3de6 | 2013-07-04 15:09:22 +0200 | [diff] [blame] | 35 | #include "sysemu/sysemu.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 36 | #include "hw/xen/xen.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 37 | #include "qemu/timer.h" |
| 38 | #include "qemu/config-file.h" |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 39 | #include "qemu/error-report.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 40 | #include "exec/memory.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 41 | #include "sysemu/dma.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 42 | #include "exec/address-spaces.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 43 | #if defined(CONFIG_USER_ONLY) |
| 44 | #include <qemu.h> |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 45 | #else /* !CONFIG_USER_ONLY */ |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 46 | #include "sysemu/xen-mapcache.h" |
Stefano Stabellini | 6506e4f | 2011-05-19 18:35:44 +0100 | [diff] [blame] | 47 | #include "trace.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 48 | #endif |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 49 | #include "exec/cpu-all.h" |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 50 | #include "qemu/rcu_queue.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 51 | #include "exec/cputlb.h" |
Blue Swirl | 5b6dd86 | 2012-12-02 16:04:43 +0000 | [diff] [blame] | 52 | #include "translate-all.h" |
Blue Swirl | 0cac1b6 | 2012-04-09 16:50:52 +0000 | [diff] [blame] | 53 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 54 | #include "exec/memory-internal.h" |
Juan Quintela | 220c3eb | 2013-10-14 17:13:59 +0200 | [diff] [blame] | 55 | #include "exec/ram_addr.h" |
Avi Kivity | 67d95c1 | 2011-12-15 15:25:22 +0200 | [diff] [blame] | 56 | |
Michael S. Tsirkin | b35ba30 | 2013-11-11 17:52:07 +0200 | [diff] [blame] | 57 | #include "qemu/range.h" |
| 58 | |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 59 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 60 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 61 | #if !defined(CONFIG_USER_ONLY) |
Juan Quintela | 981fdf2 | 2013-10-10 11:54:09 +0200 | [diff] [blame] | 62 | static bool in_migration; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 63 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 64 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
| 65 | * are protected by the ramlist lock. |
| 66 | */ |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 67 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 68 | |
| 69 | static MemoryRegion *system_memory; |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 70 | static MemoryRegion *system_io; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 71 | |
Avi Kivity | f6790af | 2012-10-02 20:13:51 +0200 | [diff] [blame] | 72 | AddressSpace address_space_io; |
| 73 | AddressSpace address_space_memory; |
Avi Kivity | 2673a5d | 2012-10-02 18:49:28 +0200 | [diff] [blame] | 74 | |
Paolo Bonzini | 0844e00 | 2013-05-24 14:37:28 +0200 | [diff] [blame] | 75 | MemoryRegion io_mem_rom, io_mem_notdirty; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 76 | static MemoryRegion io_mem_unassigned; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 77 | |
Paolo Bonzini | 7bd4f43 | 2014-05-14 17:43:22 +0800 | [diff] [blame] | 78 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
| 79 | #define RAM_PREALLOC (1 << 0) |
| 80 | |
Paolo Bonzini | dbcb898 | 2014-06-10 19:15:24 +0800 | [diff] [blame] | 81 | /* RAM is mmap-ed with MAP_SHARED */ |
| 82 | #define RAM_SHARED (1 << 1) |
| 83 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 84 | /* Only a portion of RAM (used_length) is actually used, and migrated. |
| 85 | * This used_length size can change across reboots. |
| 86 | */ |
| 87 | #define RAM_RESIZEABLE (1 << 2) |
| 88 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 89 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 90 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 91 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 92 | /* current CPU in the current thread. It is only valid inside |
| 93 | cpu_exec() */ |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 94 | DEFINE_TLS(CPUState *, current_cpu); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 95 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 96 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 97 | 2 = Adaptive rate instruction counting. */ |
Paolo Bonzini | 5708fc6 | 2012-11-26 15:36:40 +0100 | [diff] [blame] | 98 | int use_icount; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 99 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 100 | #if !defined(CONFIG_USER_ONLY) |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 101 | |
Paolo Bonzini | 1db8abb | 2013-05-21 12:07:21 +0200 | [diff] [blame] | 102 | typedef struct PhysPageEntry PhysPageEntry; |
| 103 | |
| 104 | struct PhysPageEntry { |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 105 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
Michael S. Tsirkin | 8b79576 | 2013-11-11 14:51:56 +0200 | [diff] [blame] | 106 | uint32_t skip : 6; |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 107 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
Michael S. Tsirkin | 8b79576 | 2013-11-11 14:51:56 +0200 | [diff] [blame] | 108 | uint32_t ptr : 26; |
Paolo Bonzini | 1db8abb | 2013-05-21 12:07:21 +0200 | [diff] [blame] | 109 | }; |
| 110 | |
Michael S. Tsirkin | 8b79576 | 2013-11-11 14:51:56 +0200 | [diff] [blame] | 111 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
| 112 | |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 113 | /* Size of the L2 (and L3, etc) page tables. */ |
Paolo Bonzini | 57271d6 | 2013-11-07 17:14:37 +0100 | [diff] [blame] | 114 | #define ADDR_SPACE_BITS 64 |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 115 | |
Michael S. Tsirkin | 026736c | 2013-11-13 20:13:03 +0200 | [diff] [blame] | 116 | #define P_L2_BITS 9 |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 117 | #define P_L2_SIZE (1 << P_L2_BITS) |
| 118 | |
| 119 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) |
| 120 | |
| 121 | typedef PhysPageEntry Node[P_L2_SIZE]; |
Paolo Bonzini | 0475d94 | 2013-05-29 12:28:21 +0200 | [diff] [blame] | 122 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 123 | typedef struct PhysPageMap { |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 124 | struct rcu_head rcu; |
| 125 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 126 | unsigned sections_nb; |
| 127 | unsigned sections_nb_alloc; |
| 128 | unsigned nodes_nb; |
| 129 | unsigned nodes_nb_alloc; |
| 130 | Node *nodes; |
| 131 | MemoryRegionSection *sections; |
| 132 | } PhysPageMap; |
| 133 | |
Paolo Bonzini | 1db8abb | 2013-05-21 12:07:21 +0200 | [diff] [blame] | 134 | struct AddressSpaceDispatch { |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 135 | struct rcu_head rcu; |
| 136 | |
Paolo Bonzini | 1db8abb | 2013-05-21 12:07:21 +0200 | [diff] [blame] | 137 | /* This is a multi-level map on the physical address space. |
| 138 | * The bottom level has pointers to MemoryRegionSections. |
| 139 | */ |
| 140 | PhysPageEntry phys_map; |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 141 | PhysPageMap map; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 142 | AddressSpace *as; |
Paolo Bonzini | 1db8abb | 2013-05-21 12:07:21 +0200 | [diff] [blame] | 143 | }; |
| 144 | |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 145 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 146 | typedef struct subpage_t { |
| 147 | MemoryRegion iomem; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 148 | AddressSpace *as; |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 149 | hwaddr base; |
| 150 | uint16_t sub_section[TARGET_PAGE_SIZE]; |
| 151 | } subpage_t; |
| 152 | |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 153 | #define PHYS_SECTION_UNASSIGNED 0 |
| 154 | #define PHYS_SECTION_NOTDIRTY 1 |
| 155 | #define PHYS_SECTION_ROM 2 |
| 156 | #define PHYS_SECTION_WATCH 3 |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 157 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 158 | static void io_mem_init(void); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 159 | static void memory_map_init(void); |
Edgar E. Iglesias | 09daed8 | 2013-12-17 13:06:51 +1000 | [diff] [blame] | 160 | static void tcg_commit(MemoryListener *listener); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 161 | |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 162 | static MemoryRegion io_mem_watch; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 163 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 164 | |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 165 | #if !defined(CONFIG_USER_ONLY) |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 166 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 167 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 168 | { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 169 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
| 170 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc * 2, 16); |
| 171 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
| 172 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 173 | } |
| 174 | } |
| 175 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 176 | static uint32_t phys_map_node_alloc(PhysPageMap *map) |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 177 | { |
| 178 | unsigned i; |
Michael S. Tsirkin | 8b79576 | 2013-11-11 14:51:56 +0200 | [diff] [blame] | 179 | uint32_t ret; |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 180 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 181 | ret = map->nodes_nb++; |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 182 | assert(ret != PHYS_MAP_NODE_NIL); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 183 | assert(ret != map->nodes_nb_alloc); |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 184 | for (i = 0; i < P_L2_SIZE; ++i) { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 185 | map->nodes[ret][i].skip = 1; |
| 186 | map->nodes[ret][i].ptr = PHYS_MAP_NODE_NIL; |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 187 | } |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 188 | return ret; |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame] | 189 | } |
| 190 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 191 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
| 192 | hwaddr *index, hwaddr *nb, uint16_t leaf, |
Avi Kivity | 2999097 | 2012-02-13 20:21:20 +0200 | [diff] [blame] | 193 | int level) |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 194 | { |
| 195 | PhysPageEntry *p; |
| 196 | int i; |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 197 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 198 | |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 199 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 200 | lp->ptr = phys_map_node_alloc(map); |
| 201 | p = map->nodes[lp->ptr]; |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 202 | if (level == 0) { |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 203 | for (i = 0; i < P_L2_SIZE; i++) { |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 204 | p[i].skip = 0; |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 205 | p[i].ptr = PHYS_SECTION_UNASSIGNED; |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 206 | } |
| 207 | } |
| 208 | } else { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 209 | p = map->nodes[lp->ptr]; |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 210 | } |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 211 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 212 | |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 213 | while (*nb && lp < &p[P_L2_SIZE]) { |
Avi Kivity | 07f07b3 | 2012-02-13 20:45:32 +0200 | [diff] [blame] | 214 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 215 | lp->skip = 0; |
Avi Kivity | c19e880 | 2012-02-13 20:25:31 +0200 | [diff] [blame] | 216 | lp->ptr = leaf; |
Avi Kivity | 07f07b3 | 2012-02-13 20:45:32 +0200 | [diff] [blame] | 217 | *index += step; |
| 218 | *nb -= step; |
Avi Kivity | 2999097 | 2012-02-13 20:21:20 +0200 | [diff] [blame] | 219 | } else { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 220 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
Avi Kivity | 2999097 | 2012-02-13 20:21:20 +0200 | [diff] [blame] | 221 | } |
| 222 | ++lp; |
Avi Kivity | f7bf546 | 2012-02-13 20:12:05 +0200 | [diff] [blame] | 223 | } |
| 224 | } |
| 225 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 226 | static void phys_page_set(AddressSpaceDispatch *d, |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 227 | hwaddr index, hwaddr nb, |
Avi Kivity | 2999097 | 2012-02-13 20:21:20 +0200 | [diff] [blame] | 228 | uint16_t leaf) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 229 | { |
Avi Kivity | 2999097 | 2012-02-13 20:21:20 +0200 | [diff] [blame] | 230 | /* Wildly overreserve - it doesn't matter much. */ |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 231 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 232 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 233 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 234 | } |
| 235 | |
Michael S. Tsirkin | b35ba30 | 2013-11-11 17:52:07 +0200 | [diff] [blame] | 236 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
| 237 | * and update our entry so we can skip it and go directly to the destination. |
| 238 | */ |
| 239 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *compacted) |
| 240 | { |
| 241 | unsigned valid_ptr = P_L2_SIZE; |
| 242 | int valid = 0; |
| 243 | PhysPageEntry *p; |
| 244 | int i; |
| 245 | |
| 246 | if (lp->ptr == PHYS_MAP_NODE_NIL) { |
| 247 | return; |
| 248 | } |
| 249 | |
| 250 | p = nodes[lp->ptr]; |
| 251 | for (i = 0; i < P_L2_SIZE; i++) { |
| 252 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { |
| 253 | continue; |
| 254 | } |
| 255 | |
| 256 | valid_ptr = i; |
| 257 | valid++; |
| 258 | if (p[i].skip) { |
| 259 | phys_page_compact(&p[i], nodes, compacted); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | /* We can only compress if there's only one child. */ |
| 264 | if (valid != 1) { |
| 265 | return; |
| 266 | } |
| 267 | |
| 268 | assert(valid_ptr < P_L2_SIZE); |
| 269 | |
| 270 | /* Don't compress if it won't fit in the # of bits we have. */ |
| 271 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { |
| 272 | return; |
| 273 | } |
| 274 | |
| 275 | lp->ptr = p[valid_ptr].ptr; |
| 276 | if (!p[valid_ptr].skip) { |
| 277 | /* If our only child is a leaf, make this a leaf. */ |
| 278 | /* By design, we should have made this node a leaf to begin with so we |
| 279 | * should never reach here. |
| 280 | * But since it's so simple to handle this, let's do it just in case we |
| 281 | * change this rule. |
| 282 | */ |
| 283 | lp->skip = 0; |
| 284 | } else { |
| 285 | lp->skip += p[valid_ptr].skip; |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb) |
| 290 | { |
| 291 | DECLARE_BITMAP(compacted, nodes_nb); |
| 292 | |
| 293 | if (d->phys_map.skip) { |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 294 | phys_page_compact(&d->phys_map, d->map.nodes, compacted); |
Michael S. Tsirkin | b35ba30 | 2013-11-11 17:52:07 +0200 | [diff] [blame] | 295 | } |
| 296 | } |
| 297 | |
Michael S. Tsirkin | 97115a8 | 2013-11-13 20:08:19 +0200 | [diff] [blame] | 298 | static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr, |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 299 | Node *nodes, MemoryRegionSection *sections) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 300 | { |
Avi Kivity | 31ab2b4 | 2012-02-13 16:44:19 +0200 | [diff] [blame] | 301 | PhysPageEntry *p; |
Michael S. Tsirkin | 97115a8 | 2013-11-13 20:08:19 +0200 | [diff] [blame] | 302 | hwaddr index = addr >> TARGET_PAGE_BITS; |
Avi Kivity | 31ab2b4 | 2012-02-13 16:44:19 +0200 | [diff] [blame] | 303 | int i; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 304 | |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 305 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
Avi Kivity | c19e880 | 2012-02-13 20:25:31 +0200 | [diff] [blame] | 306 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 307 | return §ions[PHYS_SECTION_UNASSIGNED]; |
Avi Kivity | 31ab2b4 | 2012-02-13 16:44:19 +0200 | [diff] [blame] | 308 | } |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 309 | p = nodes[lp.ptr]; |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 310 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 311 | } |
Michael S. Tsirkin | b35ba30 | 2013-11-11 17:52:07 +0200 | [diff] [blame] | 312 | |
| 313 | if (sections[lp.ptr].size.hi || |
| 314 | range_covers_byte(sections[lp.ptr].offset_within_address_space, |
| 315 | sections[lp.ptr].size.lo, addr)) { |
| 316 | return §ions[lp.ptr]; |
| 317 | } else { |
| 318 | return §ions[PHYS_SECTION_UNASSIGNED]; |
| 319 | } |
Avi Kivity | f3705d5 | 2012-03-08 16:16:34 +0200 | [diff] [blame] | 320 | } |
| 321 | |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 322 | bool memory_region_is_unassigned(MemoryRegion *mr) |
| 323 | { |
Paolo Bonzini | 2a8e749 | 2013-05-24 14:34:08 +0200 | [diff] [blame] | 324 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 325 | && mr != &io_mem_watch; |
| 326 | } |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 327 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 328 | /* Called from RCU critical section */ |
Paolo Bonzini | c7086b4 | 2013-06-02 15:27:39 +0200 | [diff] [blame] | 329 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 330 | hwaddr addr, |
| 331 | bool resolve_subpage) |
Jan Kiszka | 9f02960 | 2013-05-06 16:48:02 +0200 | [diff] [blame] | 332 | { |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 333 | MemoryRegionSection *section; |
| 334 | subpage_t *subpage; |
| 335 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 336 | section = phys_page_find(d->phys_map, addr, d->map.nodes, d->map.sections); |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 337 | if (resolve_subpage && section->mr->subpage) { |
| 338 | subpage = container_of(section->mr, subpage_t, iomem); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 339 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 340 | } |
| 341 | return section; |
Jan Kiszka | 9f02960 | 2013-05-06 16:48:02 +0200 | [diff] [blame] | 342 | } |
| 343 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 344 | /* Called from RCU critical section */ |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 345 | static MemoryRegionSection * |
Paolo Bonzini | c7086b4 | 2013-06-02 15:27:39 +0200 | [diff] [blame] | 346 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 347 | hwaddr *plen, bool resolve_subpage) |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 348 | { |
| 349 | MemoryRegionSection *section; |
Paolo Bonzini | a87f395 | 2014-02-07 15:47:46 +0100 | [diff] [blame] | 350 | Int128 diff; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 351 | |
Paolo Bonzini | c7086b4 | 2013-06-02 15:27:39 +0200 | [diff] [blame] | 352 | section = address_space_lookup_region(d, addr, resolve_subpage); |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 353 | /* Compute offset within MemoryRegionSection */ |
| 354 | addr -= section->offset_within_address_space; |
| 355 | |
| 356 | /* Compute offset within MemoryRegion */ |
| 357 | *xlat = addr + section->offset_within_region; |
| 358 | |
| 359 | diff = int128_sub(section->mr->size, int128_make64(addr)); |
Peter Maydell | 3752a03 | 2013-06-20 15:18:04 +0100 | [diff] [blame] | 360 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 361 | return section; |
| 362 | } |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 363 | |
Paolo Bonzini | a87f395 | 2014-02-07 15:47:46 +0100 | [diff] [blame] | 364 | static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) |
| 365 | { |
| 366 | if (memory_region_is_ram(mr)) { |
| 367 | return !(is_write && mr->readonly); |
| 368 | } |
| 369 | if (memory_region_is_romd(mr)) { |
| 370 | return !is_write; |
| 371 | } |
| 372 | |
| 373 | return false; |
| 374 | } |
| 375 | |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 376 | MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, |
| 377 | hwaddr *xlat, hwaddr *plen, |
| 378 | bool is_write) |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 379 | { |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 380 | IOMMUTLBEntry iotlb; |
| 381 | MemoryRegionSection *section; |
| 382 | MemoryRegion *mr; |
Paolo Bonzini | 4025446 | 2015-04-01 09:57:45 +0200 | [diff] [blame] | 383 | hwaddr len = *plen; |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 384 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 385 | rcu_read_lock(); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 386 | for (;;) { |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 387 | AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch); |
| 388 | section = address_space_translate_internal(d, addr, &addr, plen, true); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 389 | mr = section->mr; |
| 390 | |
| 391 | if (!mr->iommu_ops) { |
| 392 | break; |
| 393 | } |
| 394 | |
Le Tan | 8d7b8cb | 2014-08-16 13:55:37 +0800 | [diff] [blame] | 395 | iotlb = mr->iommu_ops->translate(mr, addr, is_write); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 396 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) |
| 397 | | (addr & iotlb.addr_mask)); |
Paolo Bonzini | 4025446 | 2015-04-01 09:57:45 +0200 | [diff] [blame] | 398 | len = MIN(len, (addr | iotlb.addr_mask) - addr + 1); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 399 | if (!(iotlb.perm & (1 << is_write))) { |
| 400 | mr = &io_mem_unassigned; |
| 401 | break; |
| 402 | } |
| 403 | |
| 404 | as = iotlb.target_as; |
| 405 | } |
| 406 | |
Alexey Kardashevskiy | fe680d0 | 2014-05-07 13:40:39 +0000 | [diff] [blame] | 407 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
Paolo Bonzini | a87f395 | 2014-02-07 15:47:46 +0100 | [diff] [blame] | 408 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
Paolo Bonzini | 4025446 | 2015-04-01 09:57:45 +0200 | [diff] [blame] | 409 | len = MIN(page, len); |
Paolo Bonzini | a87f395 | 2014-02-07 15:47:46 +0100 | [diff] [blame] | 410 | } |
| 411 | |
Paolo Bonzini | 4025446 | 2015-04-01 09:57:45 +0200 | [diff] [blame] | 412 | *plen = len; |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 413 | *xlat = addr; |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 414 | rcu_read_unlock(); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 415 | return mr; |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 416 | } |
| 417 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 418 | /* Called from RCU critical section */ |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 419 | MemoryRegionSection * |
Paolo Bonzini | 9d82b5a | 2013-08-16 08:26:30 +0200 | [diff] [blame] | 420 | address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr, |
| 421 | hwaddr *xlat, hwaddr *plen) |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 422 | { |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 423 | MemoryRegionSection *section; |
Paolo Bonzini | 9d82b5a | 2013-08-16 08:26:30 +0200 | [diff] [blame] | 424 | section = address_space_translate_internal(cpu->memory_dispatch, |
| 425 | addr, xlat, plen, false); |
Avi Kivity | 3095115 | 2012-10-30 13:47:46 +0200 | [diff] [blame] | 426 | |
| 427 | assert(!section->mr->iommu_ops); |
| 428 | return section; |
Jan Kiszka | 90260c6 | 2013-05-26 21:46:51 +0200 | [diff] [blame] | 429 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 430 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 431 | |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 432 | void cpu_exec_init_all(void) |
| 433 | { |
| 434 | #if !defined(CONFIG_USER_ONLY) |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 435 | qemu_mutex_init(&ram_list.mutex); |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 436 | memory_map_init(); |
| 437 | io_mem_init(); |
| 438 | #endif |
| 439 | } |
| 440 | |
Andreas Färber | b170fce | 2013-01-20 20:23:22 +0100 | [diff] [blame] | 441 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 442 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 443 | static int cpu_common_post_load(void *opaque, int version_id) |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 444 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 445 | CPUState *cpu = opaque; |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 446 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 447 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
| 448 | version_id is increased. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 449 | cpu->interrupt_request &= ~0x01; |
Christian Borntraeger | c01a71c | 2014-03-17 17:13:12 +0100 | [diff] [blame] | 450 | tlb_flush(cpu, 1); |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 451 | |
| 452 | return 0; |
| 453 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 454 | |
Pavel Dovgaluk | 6c3bff0 | 2014-07-31 09:41:17 +0400 | [diff] [blame] | 455 | static int cpu_common_pre_load(void *opaque) |
| 456 | { |
| 457 | CPUState *cpu = opaque; |
| 458 | |
Paolo Bonzini | adee642 | 2014-12-19 12:53:14 +0100 | [diff] [blame] | 459 | cpu->exception_index = -1; |
Pavel Dovgaluk | 6c3bff0 | 2014-07-31 09:41:17 +0400 | [diff] [blame] | 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | static bool cpu_common_exception_index_needed(void *opaque) |
| 465 | { |
| 466 | CPUState *cpu = opaque; |
| 467 | |
Paolo Bonzini | adee642 | 2014-12-19 12:53:14 +0100 | [diff] [blame] | 468 | return tcg_enabled() && cpu->exception_index != -1; |
Pavel Dovgaluk | 6c3bff0 | 2014-07-31 09:41:17 +0400 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | static const VMStateDescription vmstate_cpu_common_exception_index = { |
| 472 | .name = "cpu_common/exception_index", |
| 473 | .version_id = 1, |
| 474 | .minimum_version_id = 1, |
| 475 | .fields = (VMStateField[]) { |
| 476 | VMSTATE_INT32(exception_index, CPUState), |
| 477 | VMSTATE_END_OF_LIST() |
| 478 | } |
| 479 | }; |
| 480 | |
Andreas Färber | 1a1562f | 2013-06-17 04:09:11 +0200 | [diff] [blame] | 481 | const VMStateDescription vmstate_cpu_common = { |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 482 | .name = "cpu_common", |
| 483 | .version_id = 1, |
| 484 | .minimum_version_id = 1, |
Pavel Dovgaluk | 6c3bff0 | 2014-07-31 09:41:17 +0400 | [diff] [blame] | 485 | .pre_load = cpu_common_pre_load, |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 486 | .post_load = cpu_common_post_load, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 487 | .fields = (VMStateField[]) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 488 | VMSTATE_UINT32(halted, CPUState), |
| 489 | VMSTATE_UINT32(interrupt_request, CPUState), |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 490 | VMSTATE_END_OF_LIST() |
Pavel Dovgaluk | 6c3bff0 | 2014-07-31 09:41:17 +0400 | [diff] [blame] | 491 | }, |
| 492 | .subsections = (VMStateSubsection[]) { |
| 493 | { |
| 494 | .vmsd = &vmstate_cpu_common_exception_index, |
| 495 | .needed = cpu_common_exception_index_needed, |
| 496 | } , { |
| 497 | /* empty */ |
| 498 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 499 | } |
| 500 | }; |
Andreas Färber | 1a1562f | 2013-06-17 04:09:11 +0200 | [diff] [blame] | 501 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 502 | #endif |
| 503 | |
Andreas Färber | 38d8f5c | 2012-12-17 19:47:15 +0100 | [diff] [blame] | 504 | CPUState *qemu_get_cpu(int index) |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 505 | { |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 506 | CPUState *cpu; |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 507 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 508 | CPU_FOREACH(cpu) { |
Andreas Färber | 55e5c28 | 2012-12-17 06:18:02 +0100 | [diff] [blame] | 509 | if (cpu->cpu_index == index) { |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 510 | return cpu; |
Andreas Färber | 55e5c28 | 2012-12-17 06:18:02 +0100 | [diff] [blame] | 511 | } |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 512 | } |
| 513 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 514 | return NULL; |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 515 | } |
| 516 | |
Edgar E. Iglesias | 09daed8 | 2013-12-17 13:06:51 +1000 | [diff] [blame] | 517 | #if !defined(CONFIG_USER_ONLY) |
| 518 | void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as) |
| 519 | { |
| 520 | /* We only support one address space per cpu at the moment. */ |
| 521 | assert(cpu->as == as); |
| 522 | |
| 523 | if (cpu->tcg_as_listener) { |
| 524 | memory_listener_unregister(cpu->tcg_as_listener); |
| 525 | } else { |
| 526 | cpu->tcg_as_listener = g_new0(MemoryListener, 1); |
| 527 | } |
| 528 | cpu->tcg_as_listener->commit = tcg_commit; |
| 529 | memory_listener_register(cpu->tcg_as_listener, as); |
| 530 | } |
| 531 | #endif |
| 532 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 533 | void cpu_exec_init(CPUArchState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 534 | { |
Andreas Färber | 9f09e18 | 2012-05-03 06:59:07 +0200 | [diff] [blame] | 535 | CPUState *cpu = ENV_GET_CPU(env); |
Andreas Färber | b170fce | 2013-01-20 20:23:22 +0100 | [diff] [blame] | 536 | CPUClass *cc = CPU_GET_CLASS(cpu); |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 537 | CPUState *some_cpu; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 538 | int cpu_index; |
| 539 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 540 | #if defined(CONFIG_USER_ONLY) |
| 541 | cpu_list_lock(); |
| 542 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 543 | cpu_index = 0; |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 544 | CPU_FOREACH(some_cpu) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 545 | cpu_index++; |
| 546 | } |
Andreas Färber | 55e5c28 | 2012-12-17 06:18:02 +0100 | [diff] [blame] | 547 | cpu->cpu_index = cpu_index; |
Andreas Färber | 1b1ed8d | 2012-12-17 04:22:03 +0100 | [diff] [blame] | 548 | cpu->numa_node = 0; |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 549 | QTAILQ_INIT(&cpu->breakpoints); |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 550 | QTAILQ_INIT(&cpu->watchpoints); |
Jan Kiszka | dc7a09c | 2011-03-15 12:26:31 +0100 | [diff] [blame] | 551 | #ifndef CONFIG_USER_ONLY |
Edgar E. Iglesias | 09daed8 | 2013-12-17 13:06:51 +1000 | [diff] [blame] | 552 | cpu->as = &address_space_memory; |
Andreas Färber | 9f09e18 | 2012-05-03 06:59:07 +0200 | [diff] [blame] | 553 | cpu->thread_id = qemu_get_thread_id(); |
Paolo Bonzini | cba7054 | 2015-03-09 15:28:37 +0100 | [diff] [blame] | 554 | cpu_reload_memory_map(cpu); |
Jan Kiszka | dc7a09c | 2011-03-15 12:26:31 +0100 | [diff] [blame] | 555 | #endif |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 556 | QTAILQ_INSERT_TAIL(&cpus, cpu, node); |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 557 | #if defined(CONFIG_USER_ONLY) |
| 558 | cpu_list_unlock(); |
| 559 | #endif |
Andreas Färber | e0d4794 | 2013-07-29 04:07:50 +0200 | [diff] [blame] | 560 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
| 561 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu); |
| 562 | } |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 563 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
Alex Williamson | 0be71e3 | 2010-06-25 11:09:07 -0600 | [diff] [blame] | 564 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 565 | cpu_save, cpu_load, env); |
Andreas Färber | b170fce | 2013-01-20 20:23:22 +0100 | [diff] [blame] | 566 | assert(cc->vmsd == NULL); |
Andreas Färber | e0d4794 | 2013-07-29 04:07:50 +0200 | [diff] [blame] | 567 | assert(qdev_get_vmsd(DEVICE(cpu)) == NULL); |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 568 | #endif |
Andreas Färber | b170fce | 2013-01-20 20:23:22 +0100 | [diff] [blame] | 569 | if (cc->vmsd != NULL) { |
| 570 | vmstate_register(NULL, cpu_index, cc->vmsd, cpu); |
| 571 | } |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 574 | #if defined(CONFIG_USER_ONLY) |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 575 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 576 | { |
| 577 | tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 578 | } |
| 579 | #else |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 580 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
Max Filippov | 1e7855a | 2012-04-10 02:48:17 +0400 | [diff] [blame] | 581 | { |
Max Filippov | e8262a1 | 2013-09-27 22:29:17 +0400 | [diff] [blame] | 582 | hwaddr phys = cpu_get_phys_page_debug(cpu, pc); |
| 583 | if (phys != -1) { |
Edgar E. Iglesias | 09daed8 | 2013-12-17 13:06:51 +1000 | [diff] [blame] | 584 | tb_invalidate_phys_addr(cpu->as, |
Edgar E. Iglesias | 29d8ec7 | 2013-11-07 19:43:10 +0100 | [diff] [blame] | 585 | phys | (pc & ~TARGET_PAGE_MASK)); |
Max Filippov | e8262a1 | 2013-09-27 22:29:17 +0400 | [diff] [blame] | 586 | } |
Max Filippov | 1e7855a | 2012-04-10 02:48:17 +0400 | [diff] [blame] | 587 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 588 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 589 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 590 | #if defined(CONFIG_USER_ONLY) |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 591 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 592 | |
| 593 | { |
| 594 | } |
| 595 | |
Peter Maydell | 3ee887e | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 596 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
| 597 | int flags) |
| 598 | { |
| 599 | return -ENOSYS; |
| 600 | } |
| 601 | |
| 602 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
| 603 | { |
| 604 | } |
| 605 | |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 606 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 607 | int flags, CPUWatchpoint **watchpoint) |
| 608 | { |
| 609 | return -ENOSYS; |
| 610 | } |
| 611 | #else |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 612 | /* Add a watchpoint. */ |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 613 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 614 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 615 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 616 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 617 | |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 618 | /* forbid ranges which are empty or run off the end of the address space */ |
Max Filippov | 07e2863 | 2014-09-17 22:03:36 -0700 | [diff] [blame] | 619 | if (len == 0 || (addr + len - 1) < addr) { |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 620 | error_report("tried to set invalid watchpoint at %" |
| 621 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 622 | return -EINVAL; |
| 623 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 624 | wp = g_malloc(sizeof(*wp)); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 625 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 626 | wp->vaddr = addr; |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 627 | wp->len = len; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 628 | wp->flags = flags; |
| 629 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 630 | /* keep all GDB-injected watchpoints in front */ |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 631 | if (flags & BP_GDB) { |
| 632 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); |
| 633 | } else { |
| 634 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); |
| 635 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 636 | |
Andreas Färber | 31b030d | 2013-09-04 01:29:02 +0200 | [diff] [blame] | 637 | tlb_flush_page(cpu, addr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 638 | |
| 639 | if (watchpoint) |
| 640 | *watchpoint = wp; |
| 641 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 642 | } |
| 643 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 644 | /* Remove a specific watchpoint. */ |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 645 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 646 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 647 | { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 648 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 649 | |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 650 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 651 | if (addr == wp->vaddr && len == wp->len |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 652 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 653 | cpu_watchpoint_remove_by_ref(cpu, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 654 | return 0; |
| 655 | } |
| 656 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 657 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 658 | } |
| 659 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 660 | /* Remove a specific watchpoint by reference. */ |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 661 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 662 | { |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 663 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 664 | |
Andreas Färber | 31b030d | 2013-09-04 01:29:02 +0200 | [diff] [blame] | 665 | tlb_flush_page(cpu, watchpoint->vaddr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 666 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 667 | g_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 668 | } |
| 669 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 670 | /* Remove all matching watchpoints. */ |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 671 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 672 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 673 | CPUWatchpoint *wp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 674 | |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 675 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
Andreas Färber | 75a3403 | 2013-09-02 16:57:02 +0200 | [diff] [blame] | 676 | if (wp->flags & mask) { |
| 677 | cpu_watchpoint_remove_by_ref(cpu, wp); |
| 678 | } |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 679 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 680 | } |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 681 | |
| 682 | /* Return true if this watchpoint address matches the specified |
| 683 | * access (ie the address range covered by the watchpoint overlaps |
| 684 | * partially or completely with the address range covered by the |
| 685 | * access). |
| 686 | */ |
| 687 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, |
| 688 | vaddr addr, |
| 689 | vaddr len) |
| 690 | { |
| 691 | /* We know the lengths are non-zero, but a little caution is |
| 692 | * required to avoid errors in the case where the range ends |
| 693 | * exactly at the top of the address space and so addr + len |
| 694 | * wraps round to zero. |
| 695 | */ |
| 696 | vaddr wpend = wp->vaddr + wp->len - 1; |
| 697 | vaddr addrend = addr + len - 1; |
| 698 | |
| 699 | return !(addr > wpend || wp->vaddr > addrend); |
| 700 | } |
| 701 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 702 | #endif |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 703 | |
| 704 | /* Add a breakpoint. */ |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 705 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 706 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 707 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 708 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 709 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 710 | bp = g_malloc(sizeof(*bp)); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 711 | |
| 712 | bp->pc = pc; |
| 713 | bp->flags = flags; |
| 714 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 715 | /* keep all GDB-injected breakpoints in front */ |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 716 | if (flags & BP_GDB) { |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 717 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 718 | } else { |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 719 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 720 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 721 | |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 722 | breakpoint_invalidate(cpu, pc); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 723 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 724 | if (breakpoint) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 725 | *breakpoint = bp; |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 726 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 727 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | /* Remove a specific breakpoint. */ |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 731 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 732 | { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 733 | CPUBreakpoint *bp; |
| 734 | |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 735 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 736 | if (bp->pc == pc && bp->flags == flags) { |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 737 | cpu_breakpoint_remove_by_ref(cpu, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 738 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 739 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 740 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 741 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 742 | } |
| 743 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 744 | /* Remove a specific breakpoint by reference. */ |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 745 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 746 | { |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 747 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
| 748 | |
| 749 | breakpoint_invalidate(cpu, breakpoint->pc); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 750 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 751 | g_free(breakpoint); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 752 | } |
| 753 | |
| 754 | /* Remove all matching breakpoints. */ |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 755 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 756 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 757 | CPUBreakpoint *bp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 758 | |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 759 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
Andreas Färber | b3310ab | 2013-09-02 17:26:20 +0200 | [diff] [blame] | 760 | if (bp->flags & mask) { |
| 761 | cpu_breakpoint_remove_by_ref(cpu, bp); |
| 762 | } |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 763 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 764 | } |
| 765 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 766 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 767 | CPU loop after each instruction */ |
Andreas Färber | 3825b28 | 2013-06-24 18:41:06 +0200 | [diff] [blame] | 768 | void cpu_single_step(CPUState *cpu, int enabled) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 769 | { |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 770 | if (cpu->singlestep_enabled != enabled) { |
| 771 | cpu->singlestep_enabled = enabled; |
| 772 | if (kvm_enabled()) { |
Stefan Weil | 38e478e | 2013-07-25 20:50:21 +0200 | [diff] [blame] | 773 | kvm_update_guest_debug(cpu, 0); |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 774 | } else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 775 | /* must flush all the translated code to avoid inconsistencies */ |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 776 | /* XXX: only flush what is necessary */ |
Stefan Weil | 38e478e | 2013-07-25 20:50:21 +0200 | [diff] [blame] | 777 | CPUArchState *env = cpu->env_ptr; |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 778 | tb_flush(env); |
| 779 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 780 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 781 | } |
| 782 | |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 783 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 784 | { |
| 785 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 786 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 787 | |
| 788 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 789 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 790 | fprintf(stderr, "qemu: fatal: "); |
| 791 | vfprintf(stderr, fmt, ap); |
| 792 | fprintf(stderr, "\n"); |
Andreas Färber | 878096e | 2013-05-27 01:33:50 +0200 | [diff] [blame] | 793 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 794 | if (qemu_log_enabled()) { |
| 795 | qemu_log("qemu: fatal: "); |
| 796 | qemu_log_vprintf(fmt, ap2); |
| 797 | qemu_log("\n"); |
Andreas Färber | a076285 | 2013-06-16 07:28:50 +0200 | [diff] [blame] | 798 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
aliguori | 31b1a7b | 2009-01-15 22:35:09 +0000 | [diff] [blame] | 799 | qemu_log_flush(); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 800 | qemu_log_close(); |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 801 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 802 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 803 | va_end(ap); |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 804 | #if defined(CONFIG_USER_ONLY) |
| 805 | { |
| 806 | struct sigaction act; |
| 807 | sigfillset(&act.sa_mask); |
| 808 | act.sa_handler = SIG_DFL; |
| 809 | sigaction(SIGABRT, &act, NULL); |
| 810 | } |
| 811 | #endif |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 812 | abort(); |
| 813 | } |
| 814 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 815 | #if !defined(CONFIG_USER_ONLY) |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 816 | /* Called from RCU critical section */ |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 817 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
| 818 | { |
| 819 | RAMBlock *block; |
| 820 | |
Paolo Bonzini | 4377153 | 2013-09-09 17:58:40 +0200 | [diff] [blame] | 821 | block = atomic_rcu_read(&ram_list.mru_block); |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 822 | if (block && addr - block->offset < block->max_length) { |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 823 | goto found; |
| 824 | } |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 825 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 826 | if (addr - block->offset < block->max_length) { |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 827 | goto found; |
| 828 | } |
| 829 | } |
| 830 | |
| 831 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 832 | abort(); |
| 833 | |
| 834 | found: |
Paolo Bonzini | 4377153 | 2013-09-09 17:58:40 +0200 | [diff] [blame] | 835 | /* It is safe to write mru_block outside the iothread lock. This |
| 836 | * is what happens: |
| 837 | * |
| 838 | * mru_block = xxx |
| 839 | * rcu_read_unlock() |
| 840 | * xxx removed from list |
| 841 | * rcu_read_lock() |
| 842 | * read mru_block |
| 843 | * mru_block = NULL; |
| 844 | * call_rcu(reclaim_ramblock, xxx); |
| 845 | * rcu_read_unlock() |
| 846 | * |
| 847 | * atomic_rcu_set is not needed here. The block was already published |
| 848 | * when it was placed into the list. Here we're just making an extra |
| 849 | * copy of the pointer. |
| 850 | */ |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 851 | ram_list.mru_block = block; |
| 852 | return block; |
| 853 | } |
| 854 | |
Juan Quintela | a2f4d5b | 2013-10-10 11:49:53 +0200 | [diff] [blame] | 855 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 856 | { |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 857 | ram_addr_t start1; |
Juan Quintela | a2f4d5b | 2013-10-10 11:49:53 +0200 | [diff] [blame] | 858 | RAMBlock *block; |
| 859 | ram_addr_t end; |
| 860 | |
| 861 | end = TARGET_PAGE_ALIGN(start + length); |
| 862 | start &= TARGET_PAGE_MASK; |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 863 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 864 | rcu_read_lock(); |
Paolo Bonzini | 041603f | 2013-09-09 17:49:45 +0200 | [diff] [blame] | 865 | block = qemu_get_ram_block(start); |
| 866 | assert(block == qemu_get_ram_block(end - 1)); |
Michael S. Tsirkin | 1240be2 | 2014-11-12 11:44:41 +0200 | [diff] [blame] | 867 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 868 | cpu_tlb_reset_dirty_all(start1, length); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 869 | rcu_read_unlock(); |
Juan Quintela | d24981d | 2012-05-22 00:42:40 +0200 | [diff] [blame] | 870 | } |
| 871 | |
| 872 | /* Note: start and end must be within the same ram block. */ |
Juan Quintela | a2f4d5b | 2013-10-10 11:49:53 +0200 | [diff] [blame] | 873 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length, |
Juan Quintela | 5215919 | 2013-10-08 12:44:04 +0200 | [diff] [blame] | 874 | unsigned client) |
Juan Quintela | d24981d | 2012-05-22 00:42:40 +0200 | [diff] [blame] | 875 | { |
Juan Quintela | d24981d | 2012-05-22 00:42:40 +0200 | [diff] [blame] | 876 | if (length == 0) |
| 877 | return; |
Michael S. Tsirkin | c8d6f66 | 2014-11-17 17:54:07 +0200 | [diff] [blame] | 878 | cpu_physical_memory_clear_dirty_range_type(start, length, client); |
Juan Quintela | d24981d | 2012-05-22 00:42:40 +0200 | [diff] [blame] | 879 | |
| 880 | if (tcg_enabled()) { |
Juan Quintela | a2f4d5b | 2013-10-10 11:49:53 +0200 | [diff] [blame] | 881 | tlb_reset_dirty_range_all(start, length); |
Juan Quintela | d24981d | 2012-05-22 00:42:40 +0200 | [diff] [blame] | 882 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 883 | } |
| 884 | |
Juan Quintela | 981fdf2 | 2013-10-10 11:54:09 +0200 | [diff] [blame] | 885 | static void cpu_physical_memory_set_dirty_tracking(bool enable) |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 886 | { |
| 887 | in_migration = enable; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 888 | } |
| 889 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 890 | /* Called from RCU critical section */ |
Andreas Färber | bb0e627 | 2013-09-03 13:32:01 +0200 | [diff] [blame] | 891 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 892 | MemoryRegionSection *section, |
| 893 | target_ulong vaddr, |
| 894 | hwaddr paddr, hwaddr xlat, |
| 895 | int prot, |
| 896 | target_ulong *address) |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 897 | { |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 898 | hwaddr iotlb; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 899 | CPUWatchpoint *wp; |
| 900 | |
Blue Swirl | cc5bea6 | 2012-04-14 14:56:48 +0000 | [diff] [blame] | 901 | if (memory_region_is_ram(section->mr)) { |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 902 | /* Normal RAM. */ |
| 903 | iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 904 | + xlat; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 905 | if (!section->readonly) { |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 906 | iotlb |= PHYS_SECTION_NOTDIRTY; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 907 | } else { |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 908 | iotlb |= PHYS_SECTION_ROM; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 909 | } |
| 910 | } else { |
Edgar E. Iglesias | 1b3fb98 | 2013-11-07 18:43:28 +0100 | [diff] [blame] | 911 | iotlb = section - section->address_space->dispatch->map.sections; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 912 | iotlb += xlat; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 913 | } |
| 914 | |
| 915 | /* Make accesses to pages with watchpoints go via the |
| 916 | watchpoint trap routines. */ |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 917 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 918 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 919 | /* Avoid trapping reads of pages with a write breakpoint. */ |
| 920 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 921 | iotlb = PHYS_SECTION_WATCH + paddr; |
Blue Swirl | e554861 | 2012-04-21 13:08:33 +0000 | [diff] [blame] | 922 | *address |= TLB_MMIO; |
| 923 | break; |
| 924 | } |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | return iotlb; |
| 929 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 930 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 931 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 932 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 933 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 934 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 935 | uint16_t section); |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 936 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base); |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 937 | |
Igor Mammedov | a2b257d | 2014-10-31 16:38:37 +0000 | [diff] [blame] | 938 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align) = |
| 939 | qemu_anon_ram_alloc; |
Markus Armbruster | 9113803 | 2013-07-31 15:11:08 +0200 | [diff] [blame] | 940 | |
| 941 | /* |
| 942 | * Set a custom physical guest memory alloator. |
| 943 | * Accelerators with unusual needs may need this. Hopefully, we can |
| 944 | * get rid of it eventually. |
| 945 | */ |
Igor Mammedov | a2b257d | 2014-10-31 16:38:37 +0000 | [diff] [blame] | 946 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)) |
Markus Armbruster | 9113803 | 2013-07-31 15:11:08 +0200 | [diff] [blame] | 947 | { |
| 948 | phys_mem_alloc = alloc; |
| 949 | } |
| 950 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 951 | static uint16_t phys_section_add(PhysPageMap *map, |
| 952 | MemoryRegionSection *section) |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 953 | { |
Paolo Bonzini | 68f3f65 | 2013-05-07 11:30:23 +0200 | [diff] [blame] | 954 | /* The physical section number is ORed with a page-aligned |
| 955 | * pointer to produce the iotlb entries. Thus it should |
| 956 | * never overflow into the page-aligned value. |
| 957 | */ |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 958 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
Paolo Bonzini | 68f3f65 | 2013-05-07 11:30:23 +0200 | [diff] [blame] | 959 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 960 | if (map->sections_nb == map->sections_nb_alloc) { |
| 961 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); |
| 962 | map->sections = g_renew(MemoryRegionSection, map->sections, |
| 963 | map->sections_nb_alloc); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 964 | } |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 965 | map->sections[map->sections_nb] = *section; |
Paolo Bonzini | dfde4e6 | 2013-05-06 10:46:11 +0200 | [diff] [blame] | 966 | memory_region_ref(section->mr); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 967 | return map->sections_nb++; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 968 | } |
| 969 | |
Paolo Bonzini | 058bc4b | 2013-06-25 09:30:48 +0200 | [diff] [blame] | 970 | static void phys_section_destroy(MemoryRegion *mr) |
| 971 | { |
Paolo Bonzini | dfde4e6 | 2013-05-06 10:46:11 +0200 | [diff] [blame] | 972 | memory_region_unref(mr); |
| 973 | |
Paolo Bonzini | 058bc4b | 2013-06-25 09:30:48 +0200 | [diff] [blame] | 974 | if (mr->subpage) { |
| 975 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
Peter Crosthwaite | b4fefef | 2014-06-05 23:15:52 -0700 | [diff] [blame] | 976 | object_unref(OBJECT(&subpage->iomem)); |
Paolo Bonzini | 058bc4b | 2013-06-25 09:30:48 +0200 | [diff] [blame] | 977 | g_free(subpage); |
| 978 | } |
| 979 | } |
| 980 | |
Paolo Bonzini | 6092666 | 2013-05-29 12:30:26 +0200 | [diff] [blame] | 981 | static void phys_sections_free(PhysPageMap *map) |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 982 | { |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 983 | while (map->sections_nb > 0) { |
| 984 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; |
Paolo Bonzini | 058bc4b | 2013-06-25 09:30:48 +0200 | [diff] [blame] | 985 | phys_section_destroy(section->mr); |
| 986 | } |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 987 | g_free(map->sections); |
| 988 | g_free(map->nodes); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 989 | } |
| 990 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 991 | static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section) |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 992 | { |
| 993 | subpage_t *subpage; |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 994 | hwaddr base = section->offset_within_address_space |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 995 | & TARGET_PAGE_MASK; |
Michael S. Tsirkin | 97115a8 | 2013-11-13 20:08:19 +0200 | [diff] [blame] | 996 | MemoryRegionSection *existing = phys_page_find(d->phys_map, base, |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 997 | d->map.nodes, d->map.sections); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 998 | MemoryRegionSection subsection = { |
| 999 | .offset_within_address_space = base, |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1000 | .size = int128_make64(TARGET_PAGE_SIZE), |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1001 | }; |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 1002 | hwaddr start, end; |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1003 | |
Avi Kivity | f3705d5 | 2012-03-08 16:16:34 +0200 | [diff] [blame] | 1004 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1005 | |
Avi Kivity | f3705d5 | 2012-03-08 16:16:34 +0200 | [diff] [blame] | 1006 | if (!(existing->mr->subpage)) { |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1007 | subpage = subpage_init(d->as, base); |
Edgar E. Iglesias | 3be91e8 | 2013-11-07 18:42:51 +0100 | [diff] [blame] | 1008 | subsection.address_space = d->as; |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1009 | subsection.mr = &subpage->iomem; |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 1010 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 1011 | phys_section_add(&d->map, &subsection)); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1012 | } else { |
Avi Kivity | f3705d5 | 2012-03-08 16:16:34 +0200 | [diff] [blame] | 1013 | subpage = container_of(existing->mr, subpage_t, iomem); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1014 | } |
| 1015 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1016 | end = start + int128_get64(section->size) - 1; |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 1017 | subpage_register(subpage, start, end, |
| 1018 | phys_section_add(&d->map, section)); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1019 | } |
| 1020 | |
| 1021 | |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1022 | static void register_multipage(AddressSpaceDispatch *d, |
| 1023 | MemoryRegionSection *section) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1024 | { |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 1025 | hwaddr start_addr = section->offset_within_address_space; |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 1026 | uint16_t section_index = phys_section_add(&d->map, section); |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1027 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
| 1028 | TARGET_PAGE_BITS)); |
Avi Kivity | dd81124 | 2012-01-02 12:17:03 +0200 | [diff] [blame] | 1029 | |
Paolo Bonzini | 733d5ef | 2013-05-27 10:47:10 +0200 | [diff] [blame] | 1030 | assert(num_pages); |
| 1031 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1032 | } |
| 1033 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 1034 | static void mem_add(MemoryListener *listener, MemoryRegionSection *section) |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1035 | { |
Paolo Bonzini | 89ae337 | 2013-06-02 10:39:07 +0200 | [diff] [blame] | 1036 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 1037 | AddressSpaceDispatch *d = as->next_dispatch; |
Paolo Bonzini | 99b9cc0 | 2013-05-27 13:18:01 +0200 | [diff] [blame] | 1038 | MemoryRegionSection now = *section, remain = *section; |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1039 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1040 | |
Paolo Bonzini | 733d5ef | 2013-05-27 10:47:10 +0200 | [diff] [blame] | 1041 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
| 1042 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) |
| 1043 | - now.offset_within_address_space; |
| 1044 | |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1045 | now.size = int128_min(int128_make64(left), now.size); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 1046 | register_subpage(d, &now); |
Paolo Bonzini | 733d5ef | 2013-05-27 10:47:10 +0200 | [diff] [blame] | 1047 | } else { |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1048 | now.size = int128_zero(); |
Paolo Bonzini | 733d5ef | 2013-05-27 10:47:10 +0200 | [diff] [blame] | 1049 | } |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1050 | while (int128_ne(remain.size, now.size)) { |
| 1051 | remain.size = int128_sub(remain.size, now.size); |
| 1052 | remain.offset_within_address_space += int128_get64(now.size); |
| 1053 | remain.offset_within_region += int128_get64(now.size); |
Tyler Hall | 69b6764 | 2012-07-25 18:45:04 -0400 | [diff] [blame] | 1054 | now = remain; |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1055 | if (int128_lt(remain.size, page_size)) { |
Paolo Bonzini | 733d5ef | 2013-05-27 10:47:10 +0200 | [diff] [blame] | 1056 | register_subpage(d, &now); |
Hu Tao | 8826624 | 2013-08-29 18:21:16 +0800 | [diff] [blame] | 1057 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1058 | now.size = page_size; |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 1059 | register_subpage(d, &now); |
Tyler Hall | 69b6764 | 2012-07-25 18:45:04 -0400 | [diff] [blame] | 1060 | } else { |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 1061 | now.size = int128_and(now.size, int128_neg(page_size)); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 1062 | register_multipage(d, &now); |
Tyler Hall | 69b6764 | 2012-07-25 18:45:04 -0400 | [diff] [blame] | 1063 | } |
Avi Kivity | 0f0cb16 | 2012-02-13 17:14:32 +0200 | [diff] [blame] | 1064 | } |
| 1065 | } |
| 1066 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 1067 | void qemu_flush_coalesced_mmio_buffer(void) |
| 1068 | { |
| 1069 | if (kvm_enabled()) |
| 1070 | kvm_flush_coalesced_mmio_buffer(); |
| 1071 | } |
| 1072 | |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1073 | void qemu_mutex_lock_ramlist(void) |
| 1074 | { |
| 1075 | qemu_mutex_lock(&ram_list.mutex); |
| 1076 | } |
| 1077 | |
| 1078 | void qemu_mutex_unlock_ramlist(void) |
| 1079 | { |
| 1080 | qemu_mutex_unlock(&ram_list.mutex); |
| 1081 | } |
| 1082 | |
Markus Armbruster | e1e84ba | 2013-07-31 15:11:10 +0200 | [diff] [blame] | 1083 | #ifdef __linux__ |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1084 | |
| 1085 | #include <sys/vfs.h> |
| 1086 | |
| 1087 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 1088 | |
Hu Tao | fc7a580 | 2014-09-09 13:28:01 +0800 | [diff] [blame] | 1089 | static long gethugepagesize(const char *path, Error **errp) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1090 | { |
| 1091 | struct statfs fs; |
| 1092 | int ret; |
| 1093 | |
| 1094 | do { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1095 | ret = statfs(path, &fs); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1096 | } while (ret != 0 && errno == EINTR); |
| 1097 | |
| 1098 | if (ret != 0) { |
Hu Tao | fc7a580 | 2014-09-09 13:28:01 +0800 | [diff] [blame] | 1099 | error_setg_errno(errp, errno, "failed to get page size of file %s", |
| 1100 | path); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1101 | return 0; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1102 | } |
| 1103 | |
| 1104 | if (fs.f_type != HUGETLBFS_MAGIC) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1105 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1106 | |
| 1107 | return fs.f_bsize; |
| 1108 | } |
| 1109 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1110 | static void *file_ram_alloc(RAMBlock *block, |
| 1111 | ram_addr_t memory, |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1112 | const char *path, |
| 1113 | Error **errp) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1114 | { |
| 1115 | char *filename; |
Peter Feiner | 8ca761f | 2013-03-04 13:54:25 -0500 | [diff] [blame] | 1116 | char *sanitized_name; |
| 1117 | char *c; |
Hu Tao | 557529d | 2014-09-09 13:28:00 +0800 | [diff] [blame] | 1118 | void *area = NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1119 | int fd; |
Hu Tao | 557529d | 2014-09-09 13:28:00 +0800 | [diff] [blame] | 1120 | uint64_t hpagesize; |
Hu Tao | fc7a580 | 2014-09-09 13:28:01 +0800 | [diff] [blame] | 1121 | Error *local_err = NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1122 | |
Hu Tao | fc7a580 | 2014-09-09 13:28:01 +0800 | [diff] [blame] | 1123 | hpagesize = gethugepagesize(path, &local_err); |
| 1124 | if (local_err) { |
| 1125 | error_propagate(errp, local_err); |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1126 | goto error; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1127 | } |
Igor Mammedov | a2b257d | 2014-10-31 16:38:37 +0000 | [diff] [blame] | 1128 | block->mr->align = hpagesize; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1129 | |
| 1130 | if (memory < hpagesize) { |
Hu Tao | 557529d | 2014-09-09 13:28:00 +0800 | [diff] [blame] | 1131 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
| 1132 | "or larger than huge page size 0x%" PRIx64, |
| 1133 | memory, hpagesize); |
| 1134 | goto error; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1135 | } |
| 1136 | |
| 1137 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1138 | error_setg(errp, |
| 1139 | "host lacks kvm mmu notifiers, -mem-path unsupported"); |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1140 | goto error; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1141 | } |
| 1142 | |
Peter Feiner | 8ca761f | 2013-03-04 13:54:25 -0500 | [diff] [blame] | 1143 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ |
Peter Crosthwaite | 83234bf | 2014-08-14 23:54:29 -0700 | [diff] [blame] | 1144 | sanitized_name = g_strdup(memory_region_name(block->mr)); |
Peter Feiner | 8ca761f | 2013-03-04 13:54:25 -0500 | [diff] [blame] | 1145 | for (c = sanitized_name; *c != '\0'; c++) { |
| 1146 | if (*c == '/') |
| 1147 | *c = '_'; |
| 1148 | } |
| 1149 | |
| 1150 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
| 1151 | sanitized_name); |
| 1152 | g_free(sanitized_name); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1153 | |
| 1154 | fd = mkstemp(filename); |
| 1155 | if (fd < 0) { |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1156 | error_setg_errno(errp, errno, |
| 1157 | "unable to create backing store for hugepages"); |
Stefan Weil | e4ada48 | 2013-01-16 18:37:23 +0100 | [diff] [blame] | 1158 | g_free(filename); |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1159 | goto error; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1160 | } |
| 1161 | unlink(filename); |
Stefan Weil | e4ada48 | 2013-01-16 18:37:23 +0100 | [diff] [blame] | 1162 | g_free(filename); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1163 | |
| 1164 | memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 1165 | |
| 1166 | /* |
| 1167 | * ftruncate is not supported by hugetlbfs in older |
| 1168 | * hosts, so don't bother bailing out on errors. |
| 1169 | * If anything goes wrong with it under other filesystems, |
| 1170 | * mmap will fail. |
| 1171 | */ |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1172 | if (ftruncate(fd, memory)) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1173 | perror("ftruncate"); |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1174 | } |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1175 | |
Paolo Bonzini | dbcb898 | 2014-06-10 19:15:24 +0800 | [diff] [blame] | 1176 | area = mmap(0, memory, PROT_READ | PROT_WRITE, |
| 1177 | (block->flags & RAM_SHARED ? MAP_SHARED : MAP_PRIVATE), |
| 1178 | fd, 0); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1179 | if (area == MAP_FAILED) { |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1180 | error_setg_errno(errp, errno, |
| 1181 | "unable to map backing store for hugepages"); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1182 | close(fd); |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1183 | goto error; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1184 | } |
Marcelo Tosatti | ef36fa1 | 2013-10-28 18:51:46 -0200 | [diff] [blame] | 1185 | |
| 1186 | if (mem_prealloc) { |
Paolo Bonzini | 3818331 | 2014-05-14 17:43:21 +0800 | [diff] [blame] | 1187 | os_mem_prealloc(fd, area, memory); |
Marcelo Tosatti | ef36fa1 | 2013-10-28 18:51:46 -0200 | [diff] [blame] | 1188 | } |
| 1189 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1190 | block->fd = fd; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1191 | return area; |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1192 | |
| 1193 | error: |
| 1194 | if (mem_prealloc) { |
Gonglei | 81b0735 | 2015-02-25 12:22:31 +0800 | [diff] [blame] | 1195 | error_report("%s", error_get_pretty(*errp)); |
Marcelo Tosatti | f9a49df | 2014-02-04 13:41:53 -0500 | [diff] [blame] | 1196 | exit(1); |
| 1197 | } |
| 1198 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 1199 | } |
| 1200 | #endif |
| 1201 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1202 | /* Called with the ramlist lock held. */ |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 1203 | static ram_addr_t find_ram_offset(ram_addr_t size) |
| 1204 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1205 | RAMBlock *block, *next_block; |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 1206 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1207 | |
Stefan Hajnoczi | 49cd9ac | 2013-03-11 10:20:21 +0100 | [diff] [blame] | 1208 | assert(size != 0); /* it would hand out same offset multiple times */ |
| 1209 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1210 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1211 | return 0; |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1212 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1213 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1214 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 1215 | ram_addr_t end, next = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1216 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1217 | end = block->offset + block->max_length; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1218 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1219 | QLIST_FOREACH_RCU(next_block, &ram_list.blocks, next) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1220 | if (next_block->offset >= end) { |
| 1221 | next = MIN(next, next_block->offset); |
| 1222 | } |
| 1223 | } |
| 1224 | if (next - end >= size && next - end < mingap) { |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 1225 | offset = end; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1226 | mingap = next - end; |
| 1227 | } |
| 1228 | } |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 1229 | |
| 1230 | if (offset == RAM_ADDR_MAX) { |
| 1231 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", |
| 1232 | (uint64_t)size); |
| 1233 | abort(); |
| 1234 | } |
| 1235 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1236 | return offset; |
| 1237 | } |
| 1238 | |
Juan Quintela | 652d7ec | 2012-07-20 10:37:54 +0200 | [diff] [blame] | 1239 | ram_addr_t last_ram_offset(void) |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1240 | { |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 1241 | RAMBlock *block; |
| 1242 | ram_addr_t last = 0; |
| 1243 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1244 | rcu_read_lock(); |
| 1245 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1246 | last = MAX(last, block->offset + block->max_length); |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1247 | } |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1248 | rcu_read_unlock(); |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 1249 | return last; |
| 1250 | } |
| 1251 | |
Jason Baron | ddb97f1 | 2012-08-02 15:44:16 -0400 | [diff] [blame] | 1252 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
| 1253 | { |
| 1254 | int ret; |
Jason Baron | ddb97f1 | 2012-08-02 15:44:16 -0400 | [diff] [blame] | 1255 | |
| 1256 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ |
Marcel Apfelbaum | 47c8ca5 | 2015-02-04 17:43:54 +0200 | [diff] [blame] | 1257 | if (!machine_dump_guest_core(current_machine)) { |
Jason Baron | ddb97f1 | 2012-08-02 15:44:16 -0400 | [diff] [blame] | 1258 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
| 1259 | if (ret) { |
| 1260 | perror("qemu_madvise"); |
| 1261 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " |
| 1262 | "but dump_guest_core=off specified\n"); |
| 1263 | } |
| 1264 | } |
| 1265 | } |
| 1266 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1267 | /* Called within an RCU critical section, or while the ramlist lock |
| 1268 | * is held. |
| 1269 | */ |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1270 | static RAMBlock *find_ram_block(ram_addr_t addr) |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1271 | { |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1272 | RAMBlock *block; |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1273 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1274 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1275 | if (block->offset == addr) { |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1276 | return block; |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1277 | } |
| 1278 | } |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1279 | |
| 1280 | return NULL; |
| 1281 | } |
| 1282 | |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1283 | /* Called with iothread lock held. */ |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1284 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
| 1285 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1286 | RAMBlock *new_block, *block; |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1287 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1288 | rcu_read_lock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1289 | new_block = find_ram_block(addr); |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1290 | assert(new_block); |
| 1291 | assert(!new_block->idstr[0]); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1292 | |
Anthony Liguori | 09e5ab6 | 2012-02-03 12:28:43 -0600 | [diff] [blame] | 1293 | if (dev) { |
| 1294 | char *id = qdev_get_dev_path(dev); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1295 | if (id) { |
| 1296 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1297 | g_free(id); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1298 | } |
| 1299 | } |
| 1300 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); |
| 1301 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1302 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1303 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1304 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
| 1305 | new_block->idstr); |
| 1306 | abort(); |
| 1307 | } |
| 1308 | } |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1309 | rcu_read_unlock(); |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1310 | } |
| 1311 | |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1312 | /* Called with iothread lock held. */ |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1313 | void qemu_ram_unset_idstr(ram_addr_t addr) |
| 1314 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1315 | RAMBlock *block; |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1316 | |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1317 | /* FIXME: arch_init.c assumes that this is not called throughout |
| 1318 | * migration. Ignore the problem since hot-unplug during migration |
| 1319 | * does not work anyway. |
| 1320 | */ |
| 1321 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1322 | rcu_read_lock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1323 | block = find_ram_block(addr); |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1324 | if (block) { |
| 1325 | memset(block->idstr, 0, sizeof(block->idstr)); |
| 1326 | } |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1327 | rcu_read_unlock(); |
Hu Tao | 20cfe88 | 2014-04-02 15:13:26 +0800 | [diff] [blame] | 1328 | } |
| 1329 | |
Luiz Capitulino | 8490fc7 | 2012-09-05 16:50:16 -0300 | [diff] [blame] | 1330 | static int memory_try_enable_merging(void *addr, size_t len) |
| 1331 | { |
Marcel Apfelbaum | 75cc7f0 | 2015-02-04 17:43:55 +0200 | [diff] [blame] | 1332 | if (!machine_mem_merge(current_machine)) { |
Luiz Capitulino | 8490fc7 | 2012-09-05 16:50:16 -0300 | [diff] [blame] | 1333 | /* disabled by the user */ |
| 1334 | return 0; |
| 1335 | } |
| 1336 | |
| 1337 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); |
| 1338 | } |
| 1339 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1340 | /* Only legal before guest might have detected the memory size: e.g. on |
| 1341 | * incoming migration, or right after reset. |
| 1342 | * |
| 1343 | * As memory core doesn't know how is memory accessed, it is up to |
| 1344 | * resize callback to update device state and/or add assertions to detect |
| 1345 | * misuse, if necessary. |
| 1346 | */ |
| 1347 | int qemu_ram_resize(ram_addr_t base, ram_addr_t newsize, Error **errp) |
| 1348 | { |
| 1349 | RAMBlock *block = find_ram_block(base); |
| 1350 | |
| 1351 | assert(block); |
| 1352 | |
Michael S. Tsirkin | 129ddaf | 2015-02-17 10:15:30 +0100 | [diff] [blame] | 1353 | newsize = TARGET_PAGE_ALIGN(newsize); |
| 1354 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1355 | if (block->used_length == newsize) { |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
| 1359 | if (!(block->flags & RAM_RESIZEABLE)) { |
| 1360 | error_setg_errno(errp, EINVAL, |
| 1361 | "Length mismatch: %s: 0x" RAM_ADDR_FMT |
| 1362 | " in != 0x" RAM_ADDR_FMT, block->idstr, |
| 1363 | newsize, block->used_length); |
| 1364 | return -EINVAL; |
| 1365 | } |
| 1366 | |
| 1367 | if (block->max_length < newsize) { |
| 1368 | error_setg_errno(errp, EINVAL, |
| 1369 | "Length too large: %s: 0x" RAM_ADDR_FMT |
| 1370 | " > 0x" RAM_ADDR_FMT, block->idstr, |
| 1371 | newsize, block->max_length); |
| 1372 | return -EINVAL; |
| 1373 | } |
| 1374 | |
| 1375 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); |
| 1376 | block->used_length = newsize; |
| 1377 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length); |
| 1378 | memory_region_set_size(block->mr, newsize); |
| 1379 | if (block->resized) { |
| 1380 | block->resized(block->idstr, newsize, block->host); |
| 1381 | } |
| 1382 | return 0; |
| 1383 | } |
| 1384 | |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1385 | static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp) |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1386 | { |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1387 | RAMBlock *block; |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1388 | RAMBlock *last_block = NULL; |
Juan Quintela | 2152f5c | 2013-10-08 13:52:02 +0200 | [diff] [blame] | 1389 | ram_addr_t old_ram_size, new_ram_size; |
| 1390 | |
| 1391 | old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS; |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 1392 | |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1393 | qemu_mutex_lock_ramlist(); |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1394 | new_block->offset = find_ram_offset(new_block->max_length); |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1395 | |
| 1396 | if (!new_block->host) { |
| 1397 | if (xen_enabled()) { |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1398 | xen_ram_alloc(new_block->offset, new_block->max_length, |
| 1399 | new_block->mr); |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1400 | } else { |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1401 | new_block->host = phys_mem_alloc(new_block->max_length, |
Igor Mammedov | a2b257d | 2014-10-31 16:38:37 +0000 | [diff] [blame] | 1402 | &new_block->mr->align); |
Markus Armbruster | 3922825 | 2013-07-31 15:11:11 +0200 | [diff] [blame] | 1403 | if (!new_block->host) { |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1404 | error_setg_errno(errp, errno, |
| 1405 | "cannot set up guest memory '%s'", |
| 1406 | memory_region_name(new_block->mr)); |
| 1407 | qemu_mutex_unlock_ramlist(); |
| 1408 | return -1; |
Markus Armbruster | 3922825 | 2013-07-31 15:11:11 +0200 | [diff] [blame] | 1409 | } |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1410 | memory_try_enable_merging(new_block->host, new_block->max_length); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 1411 | } |
| 1412 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1413 | |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1414 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
| 1415 | * QLIST (which has an RCU-friendly variant) does not have insertion at |
| 1416 | * tail, so save the last element in last_block. |
| 1417 | */ |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1418 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1419 | last_block = block; |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1420 | if (block->max_length < new_block->max_length) { |
Paolo Bonzini | abb26d6 | 2012-11-14 16:00:51 +0100 | [diff] [blame] | 1421 | break; |
| 1422 | } |
| 1423 | } |
| 1424 | if (block) { |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1425 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1426 | } else if (last_block) { |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1427 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
Mike Day | 0d53d9f | 2015-01-21 13:45:24 +0100 | [diff] [blame] | 1428 | } else { /* list is empty */ |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1429 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
Paolo Bonzini | abb26d6 | 2012-11-14 16:00:51 +0100 | [diff] [blame] | 1430 | } |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1431 | ram_list.mru_block = NULL; |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1432 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1433 | /* Write list before version */ |
| 1434 | smp_wmb(); |
Umesh Deshpande | f798b07 | 2011-08-18 11:41:17 -0700 | [diff] [blame] | 1435 | ram_list.version++; |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1436 | qemu_mutex_unlock_ramlist(); |
Umesh Deshpande | f798b07 | 2011-08-18 11:41:17 -0700 | [diff] [blame] | 1437 | |
Juan Quintela | 2152f5c | 2013-10-08 13:52:02 +0200 | [diff] [blame] | 1438 | new_ram_size = last_ram_offset() >> TARGET_PAGE_BITS; |
| 1439 | |
| 1440 | if (new_ram_size > old_ram_size) { |
Juan Quintela | 1ab4c8c | 2013-10-08 16:14:39 +0200 | [diff] [blame] | 1441 | int i; |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1442 | |
| 1443 | /* ram_list.dirty_memory[] is protected by the iothread lock. */ |
Juan Quintela | 1ab4c8c | 2013-10-08 16:14:39 +0200 | [diff] [blame] | 1444 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { |
| 1445 | ram_list.dirty_memory[i] = |
| 1446 | bitmap_zero_extend(ram_list.dirty_memory[i], |
| 1447 | old_ram_size, new_ram_size); |
| 1448 | } |
Juan Quintela | 2152f5c | 2013-10-08 13:52:02 +0200 | [diff] [blame] | 1449 | } |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1450 | cpu_physical_memory_set_dirty_range(new_block->offset, |
| 1451 | new_block->used_length); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1452 | |
Paolo Bonzini | a904c91 | 2015-01-21 16:18:35 +0100 | [diff] [blame] | 1453 | if (new_block->host) { |
| 1454 | qemu_ram_setup_dump(new_block->host, new_block->max_length); |
| 1455 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); |
| 1456 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); |
| 1457 | if (kvm_enabled()) { |
| 1458 | kvm_setup_guest_memory(new_block->host, new_block->max_length); |
| 1459 | } |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1460 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 1461 | |
| 1462 | return new_block->offset; |
| 1463 | } |
| 1464 | |
Paolo Bonzini | 0b183fc | 2014-05-14 17:43:19 +0800 | [diff] [blame] | 1465 | #ifdef __linux__ |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1466 | ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, |
Paolo Bonzini | dbcb898 | 2014-06-10 19:15:24 +0800 | [diff] [blame] | 1467 | bool share, const char *mem_path, |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1468 | Error **errp) |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1469 | { |
| 1470 | RAMBlock *new_block; |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1471 | ram_addr_t addr; |
| 1472 | Error *local_err = NULL; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1473 | |
| 1474 | if (xen_enabled()) { |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1475 | error_setg(errp, "-mem-path not supported with Xen"); |
| 1476 | return -1; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1477 | } |
| 1478 | |
| 1479 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
| 1480 | /* |
| 1481 | * file_ram_alloc() needs to allocate just like |
| 1482 | * phys_mem_alloc, but we haven't bothered to provide |
| 1483 | * a hook there. |
| 1484 | */ |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1485 | error_setg(errp, |
| 1486 | "-mem-path not supported with this accelerator"); |
| 1487 | return -1; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1488 | } |
| 1489 | |
| 1490 | size = TARGET_PAGE_ALIGN(size); |
| 1491 | new_block = g_malloc0(sizeof(*new_block)); |
| 1492 | new_block->mr = mr; |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1493 | new_block->used_length = size; |
| 1494 | new_block->max_length = size; |
Paolo Bonzini | dbcb898 | 2014-06-10 19:15:24 +0800 | [diff] [blame] | 1495 | new_block->flags = share ? RAM_SHARED : 0; |
Paolo Bonzini | 7f56e74 | 2014-05-14 17:43:20 +0800 | [diff] [blame] | 1496 | new_block->host = file_ram_alloc(new_block, size, |
| 1497 | mem_path, errp); |
| 1498 | if (!new_block->host) { |
| 1499 | g_free(new_block); |
| 1500 | return -1; |
| 1501 | } |
| 1502 | |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1503 | addr = ram_block_add(new_block, &local_err); |
| 1504 | if (local_err) { |
| 1505 | g_free(new_block); |
| 1506 | error_propagate(errp, local_err); |
| 1507 | return -1; |
| 1508 | } |
| 1509 | return addr; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1510 | } |
Paolo Bonzini | 0b183fc | 2014-05-14 17:43:19 +0800 | [diff] [blame] | 1511 | #endif |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1512 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1513 | static |
| 1514 | ram_addr_t qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
| 1515 | void (*resized)(const char*, |
| 1516 | uint64_t length, |
| 1517 | void *host), |
| 1518 | void *host, bool resizeable, |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1519 | MemoryRegion *mr, Error **errp) |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1520 | { |
| 1521 | RAMBlock *new_block; |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1522 | ram_addr_t addr; |
| 1523 | Error *local_err = NULL; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1524 | |
| 1525 | size = TARGET_PAGE_ALIGN(size); |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1526 | max_size = TARGET_PAGE_ALIGN(max_size); |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1527 | new_block = g_malloc0(sizeof(*new_block)); |
| 1528 | new_block->mr = mr; |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1529 | new_block->resized = resized; |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1530 | new_block->used_length = size; |
| 1531 | new_block->max_length = max_size; |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1532 | assert(max_size >= size); |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1533 | new_block->fd = -1; |
| 1534 | new_block->host = host; |
| 1535 | if (host) { |
Paolo Bonzini | 7bd4f43 | 2014-05-14 17:43:22 +0800 | [diff] [blame] | 1536 | new_block->flags |= RAM_PREALLOC; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1537 | } |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1538 | if (resizeable) { |
| 1539 | new_block->flags |= RAM_RESIZEABLE; |
| 1540 | } |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1541 | addr = ram_block_add(new_block, &local_err); |
| 1542 | if (local_err) { |
| 1543 | g_free(new_block); |
| 1544 | error_propagate(errp, local_err); |
| 1545 | return -1; |
| 1546 | } |
| 1547 | return addr; |
Paolo Bonzini | e1c57ab | 2014-05-14 17:43:18 +0800 | [diff] [blame] | 1548 | } |
| 1549 | |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1550 | ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
| 1551 | MemoryRegion *mr, Error **errp) |
| 1552 | { |
| 1553 | return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); |
| 1554 | } |
| 1555 | |
Hu Tao | ef701d7 | 2014-09-09 13:27:54 +0800 | [diff] [blame] | 1556 | ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 1557 | { |
Michael S. Tsirkin | 62be4e3 | 2014-11-12 14:27:41 +0200 | [diff] [blame] | 1558 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); |
| 1559 | } |
| 1560 | |
| 1561 | ram_addr_t qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
| 1562 | void (*resized)(const char*, |
| 1563 | uint64_t length, |
| 1564 | void *host), |
| 1565 | MemoryRegion *mr, Error **errp) |
| 1566 | { |
| 1567 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 1568 | } |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 1569 | |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 1570 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
| 1571 | { |
| 1572 | RAMBlock *block; |
| 1573 | |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1574 | qemu_mutex_lock_ramlist(); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1575 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 1576 | if (addr == block->offset) { |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1577 | QLIST_REMOVE_RCU(block, next); |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1578 | ram_list.mru_block = NULL; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1579 | /* Write list before version */ |
| 1580 | smp_wmb(); |
Umesh Deshpande | f798b07 | 2011-08-18 11:41:17 -0700 | [diff] [blame] | 1581 | ram_list.version++; |
Paolo Bonzini | 4377153 | 2013-09-09 17:58:40 +0200 | [diff] [blame] | 1582 | g_free_rcu(block, rcu); |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1583 | break; |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 1584 | } |
| 1585 | } |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1586 | qemu_mutex_unlock_ramlist(); |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 1587 | } |
| 1588 | |
Paolo Bonzini | 4377153 | 2013-09-09 17:58:40 +0200 | [diff] [blame] | 1589 | static void reclaim_ramblock(RAMBlock *block) |
| 1590 | { |
| 1591 | if (block->flags & RAM_PREALLOC) { |
| 1592 | ; |
| 1593 | } else if (xen_enabled()) { |
| 1594 | xen_invalidate_map_cache_entry(block->host); |
| 1595 | #ifndef _WIN32 |
| 1596 | } else if (block->fd >= 0) { |
| 1597 | munmap(block->host, block->max_length); |
| 1598 | close(block->fd); |
| 1599 | #endif |
| 1600 | } else { |
| 1601 | qemu_anon_ram_free(block->host, block->max_length); |
| 1602 | } |
| 1603 | g_free(block); |
| 1604 | } |
| 1605 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1606 | void qemu_ram_free(ram_addr_t addr) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 1607 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1608 | RAMBlock *block; |
| 1609 | |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1610 | qemu_mutex_lock_ramlist(); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1611 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1612 | if (addr == block->offset) { |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1613 | QLIST_REMOVE_RCU(block, next); |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1614 | ram_list.mru_block = NULL; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1615 | /* Write list before version */ |
| 1616 | smp_wmb(); |
Umesh Deshpande | f798b07 | 2011-08-18 11:41:17 -0700 | [diff] [blame] | 1617 | ram_list.version++; |
Paolo Bonzini | 4377153 | 2013-09-09 17:58:40 +0200 | [diff] [blame] | 1618 | call_rcu(block, reclaim_ramblock, rcu); |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1619 | break; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 1620 | } |
| 1621 | } |
Umesh Deshpande | b2a8658 | 2011-08-17 00:01:33 -0700 | [diff] [blame] | 1622 | qemu_mutex_unlock_ramlist(); |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 1623 | } |
| 1624 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1625 | #ifndef _WIN32 |
| 1626 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) |
| 1627 | { |
| 1628 | RAMBlock *block; |
| 1629 | ram_addr_t offset; |
| 1630 | int flags; |
| 1631 | void *area, *vaddr; |
| 1632 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1633 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1634 | offset = addr - block->offset; |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1635 | if (offset < block->max_length) { |
Michael S. Tsirkin | 1240be2 | 2014-11-12 11:44:41 +0200 | [diff] [blame] | 1636 | vaddr = ramblock_ptr(block, offset); |
Paolo Bonzini | 7bd4f43 | 2014-05-14 17:43:22 +0800 | [diff] [blame] | 1637 | if (block->flags & RAM_PREALLOC) { |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1638 | ; |
Markus Armbruster | dfeaf2a | 2013-07-31 15:11:05 +0200 | [diff] [blame] | 1639 | } else if (xen_enabled()) { |
| 1640 | abort(); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1641 | } else { |
| 1642 | flags = MAP_FIXED; |
Markus Armbruster | 3435f39 | 2013-07-31 15:11:07 +0200 | [diff] [blame] | 1643 | if (block->fd >= 0) { |
Paolo Bonzini | dbcb898 | 2014-06-10 19:15:24 +0800 | [diff] [blame] | 1644 | flags |= (block->flags & RAM_SHARED ? |
| 1645 | MAP_SHARED : MAP_PRIVATE); |
Markus Armbruster | 3435f39 | 2013-07-31 15:11:07 +0200 | [diff] [blame] | 1646 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 1647 | flags, block->fd, offset); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1648 | } else { |
Markus Armbruster | 2eb9fba | 2013-07-31 15:11:09 +0200 | [diff] [blame] | 1649 | /* |
| 1650 | * Remap needs to match alloc. Accelerators that |
| 1651 | * set phys_mem_alloc never remap. If they did, |
| 1652 | * we'd need a remap hook here. |
| 1653 | */ |
| 1654 | assert(phys_mem_alloc == qemu_anon_ram_alloc); |
| 1655 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1656 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 1657 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 1658 | flags, -1, 0); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1659 | } |
| 1660 | if (area != vaddr) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 1661 | fprintf(stderr, "Could not remap addr: " |
| 1662 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1663 | length, addr); |
| 1664 | exit(1); |
| 1665 | } |
Luiz Capitulino | 8490fc7 | 2012-09-05 16:50:16 -0300 | [diff] [blame] | 1666 | memory_try_enable_merging(vaddr, length); |
Jason Baron | ddb97f1 | 2012-08-02 15:44:16 -0400 | [diff] [blame] | 1667 | qemu_ram_setup_dump(vaddr, length); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1668 | } |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 1669 | } |
| 1670 | } |
| 1671 | } |
| 1672 | #endif /* !_WIN32 */ |
| 1673 | |
Paolo Bonzini | a35ba7b | 2014-06-10 19:15:23 +0800 | [diff] [blame] | 1674 | int qemu_get_ram_fd(ram_addr_t addr) |
| 1675 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1676 | RAMBlock *block; |
| 1677 | int fd; |
Paolo Bonzini | a35ba7b | 2014-06-10 19:15:23 +0800 | [diff] [blame] | 1678 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1679 | rcu_read_lock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1680 | block = qemu_get_ram_block(addr); |
| 1681 | fd = block->fd; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1682 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1683 | return fd; |
Paolo Bonzini | a35ba7b | 2014-06-10 19:15:23 +0800 | [diff] [blame] | 1684 | } |
| 1685 | |
Damjan Marion | 3fd74b8 | 2014-06-26 23:01:32 +0200 | [diff] [blame] | 1686 | void *qemu_get_ram_block_host_ptr(ram_addr_t addr) |
| 1687 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1688 | RAMBlock *block; |
| 1689 | void *ptr; |
Damjan Marion | 3fd74b8 | 2014-06-26 23:01:32 +0200 | [diff] [blame] | 1690 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1691 | rcu_read_lock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1692 | block = qemu_get_ram_block(addr); |
| 1693 | ptr = ramblock_ptr(block, 0); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1694 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1695 | return ptr; |
Damjan Marion | 3fd74b8 | 2014-06-26 23:01:32 +0200 | [diff] [blame] | 1696 | } |
| 1697 | |
Paolo Bonzini | 1b5ec23 | 2013-05-06 14:36:15 +0200 | [diff] [blame] | 1698 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1699 | * This should not be used for general purpose DMA. Use address_space_map |
| 1700 | * or address_space_rw instead. For local memory (e.g. video ram) that the |
| 1701 | * device owns, use memory_region_get_ram_ptr. |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1702 | * |
| 1703 | * By the time this function returns, the returned pointer is not protected |
| 1704 | * by RCU anymore. If the caller is not within an RCU critical section and |
| 1705 | * does not hold the iothread lock, it must have other means of protecting the |
| 1706 | * pointer, such as a reference to the region that includes the incoming |
| 1707 | * ram_addr_t. |
Paolo Bonzini | 1b5ec23 | 2013-05-06 14:36:15 +0200 | [diff] [blame] | 1708 | */ |
| 1709 | void *qemu_get_ram_ptr(ram_addr_t addr) |
| 1710 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1711 | RAMBlock *block; |
| 1712 | void *ptr; |
Paolo Bonzini | 1b5ec23 | 2013-05-06 14:36:15 +0200 | [diff] [blame] | 1713 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1714 | rcu_read_lock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1715 | block = qemu_get_ram_block(addr); |
| 1716 | |
| 1717 | if (xen_enabled() && block->host == NULL) { |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1718 | /* We need to check if the requested address is in the RAM |
| 1719 | * because we don't want to map the entire memory in QEMU. |
| 1720 | * In that case just map until the end of the page. |
| 1721 | */ |
| 1722 | if (block->offset == 0) { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1723 | ptr = xen_map_cache(addr, 0, 0); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1724 | goto unlock; |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1725 | } |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1726 | |
| 1727 | block->host = xen_map_cache(block->offset, block->max_length, 1); |
Paolo Bonzini | 0d6d3c8 | 2012-11-14 15:45:02 +0100 | [diff] [blame] | 1728 | } |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1729 | ptr = ramblock_ptr(block, addr - block->offset); |
| 1730 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1731 | unlock: |
| 1732 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1733 | return ptr; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 1734 | } |
| 1735 | |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 1736 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1737 | * but takes a size argument. |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1738 | * |
| 1739 | * By the time this function returns, the returned pointer is not protected |
| 1740 | * by RCU anymore. If the caller is not within an RCU critical section and |
| 1741 | * does not hold the iothread lock, it must have other means of protecting the |
| 1742 | * pointer, such as a reference to the region that includes the incoming |
| 1743 | * ram_addr_t. |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1744 | */ |
Peter Maydell | cb85f7a | 2013-07-08 09:44:04 +0100 | [diff] [blame] | 1745 | static void *qemu_ram_ptr_length(ram_addr_t addr, hwaddr *size) |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 1746 | { |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1747 | void *ptr; |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 1748 | if (*size == 0) { |
| 1749 | return NULL; |
| 1750 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 1751 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 1752 | return xen_map_cache(addr, *size, 1); |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 1753 | } else { |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 1754 | RAMBlock *block; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1755 | rcu_read_lock(); |
| 1756 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1757 | if (addr - block->offset < block->max_length) { |
| 1758 | if (addr - block->offset + *size > block->max_length) |
| 1759 | *size = block->max_length - addr + block->offset; |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1760 | ptr = ramblock_ptr(block, addr - block->offset); |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1761 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1762 | return ptr; |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 1767 | abort(); |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 1768 | } |
| 1769 | } |
| 1770 | |
Paolo Bonzini | 7443b43 | 2013-06-03 12:44:02 +0200 | [diff] [blame] | 1771 | /* Some of the softmmu routines need to translate from a host pointer |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1772 | * (typically a TLB entry) back to a ram offset. |
| 1773 | * |
| 1774 | * By the time this function returns, the returned pointer is not protected |
| 1775 | * by RCU anymore. If the caller is not within an RCU critical section and |
| 1776 | * does not hold the iothread lock, it must have other means of protecting the |
| 1777 | * pointer, such as a reference to the region that includes the incoming |
| 1778 | * ram_addr_t. |
| 1779 | */ |
Paolo Bonzini | 1b5ec23 | 2013-05-06 14:36:15 +0200 | [diff] [blame] | 1780 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 1781 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 1782 | RAMBlock *block; |
| 1783 | uint8_t *host = ptr; |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1784 | MemoryRegion *mr; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 1785 | |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 1786 | if (xen_enabled()) { |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1787 | rcu_read_lock(); |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 1788 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1789 | mr = qemu_get_ram_block(*ram_addr)->mr; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1790 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1791 | return mr; |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 1792 | } |
| 1793 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1794 | rcu_read_lock(); |
| 1795 | block = atomic_rcu_read(&ram_list.mru_block); |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1796 | if (block && block->host && host - block->host < block->max_length) { |
Paolo Bonzini | 23887b7 | 2013-05-06 14:28:39 +0200 | [diff] [blame] | 1797 | goto found; |
| 1798 | } |
| 1799 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1800 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 1801 | /* This case append when the block is not mapped. */ |
| 1802 | if (block->host == NULL) { |
| 1803 | continue; |
| 1804 | } |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 1805 | if (host - block->host < block->max_length) { |
Paolo Bonzini | 23887b7 | 2013-05-06 14:28:39 +0200 | [diff] [blame] | 1806 | goto found; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 1807 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 1808 | } |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 1809 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1810 | rcu_read_unlock(); |
Paolo Bonzini | 1b5ec23 | 2013-05-06 14:36:15 +0200 | [diff] [blame] | 1811 | return NULL; |
Paolo Bonzini | 23887b7 | 2013-05-06 14:28:39 +0200 | [diff] [blame] | 1812 | |
| 1813 | found: |
| 1814 | *ram_addr = block->offset + (host - block->host); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1815 | mr = block->mr; |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1816 | rcu_read_unlock(); |
Mike Day | ae3a704 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 1817 | return mr; |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 1818 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 1819 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 1820 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1821 | uint64_t val, unsigned size) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1822 | { |
Juan Quintela | 5215919 | 2013-10-08 12:44:04 +0200 | [diff] [blame] | 1823 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1824 | tb_invalidate_phys_page_fast(ram_addr, size); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1825 | } |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1826 | switch (size) { |
| 1827 | case 1: |
| 1828 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
| 1829 | break; |
| 1830 | case 2: |
| 1831 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
| 1832 | break; |
| 1833 | case 4: |
| 1834 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
| 1835 | break; |
| 1836 | default: |
| 1837 | abort(); |
| 1838 | } |
Paolo Bonzini | 6886867 | 2014-07-21 16:45:18 +0200 | [diff] [blame] | 1839 | cpu_physical_memory_set_dirty_range_nocode(ram_addr, size); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 1840 | /* we remove the notdirty callback only if the code has been |
| 1841 | flushed */ |
Juan Quintela | a2cd8c8 | 2013-10-10 11:20:22 +0200 | [diff] [blame] | 1842 | if (!cpu_physical_memory_is_clean(ram_addr)) { |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 1843 | CPUArchState *env = current_cpu->env_ptr; |
Andreas Färber | 93afead | 2013-08-26 03:41:01 +0200 | [diff] [blame] | 1844 | tlb_set_dirty(env, current_cpu->mem_io_vaddr); |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 1845 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1846 | } |
| 1847 | |
Paolo Bonzini | b018ddf | 2013-05-24 14:48:38 +0200 | [diff] [blame] | 1848 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
| 1849 | unsigned size, bool is_write) |
| 1850 | { |
| 1851 | return is_write; |
| 1852 | } |
| 1853 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1854 | static const MemoryRegionOps notdirty_mem_ops = { |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1855 | .write = notdirty_mem_write, |
Paolo Bonzini | b018ddf | 2013-05-24 14:48:38 +0200 | [diff] [blame] | 1856 | .valid.accepts = notdirty_mem_accepts, |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 1857 | .endianness = DEVICE_NATIVE_ENDIAN, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1858 | }; |
| 1859 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1860 | /* Generate a debug exception if a watchpoint has been hit. */ |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 1861 | static void check_watchpoint(int offset, int len, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1862 | { |
Andreas Färber | 93afead | 2013-08-26 03:41:01 +0200 | [diff] [blame] | 1863 | CPUState *cpu = current_cpu; |
| 1864 | CPUArchState *env = cpu->env_ptr; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 1865 | target_ulong pc, cs_base; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1866 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1867 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 1868 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1869 | |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 1870 | if (cpu->watchpoint_hit) { |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 1871 | /* We re-entered the check after replacing the TB. Now raise |
| 1872 | * the debug interrupt so that is will trigger after the |
| 1873 | * current instruction. */ |
Andreas Färber | 93afead | 2013-08-26 03:41:01 +0200 | [diff] [blame] | 1874 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 1875 | return; |
| 1876 | } |
Andreas Färber | 93afead | 2013-08-26 03:41:01 +0200 | [diff] [blame] | 1877 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 1878 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 1879 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
| 1880 | && (wp->flags & flags)) { |
Peter Maydell | 0822567 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 1881 | if (flags == BP_MEM_READ) { |
| 1882 | wp->flags |= BP_WATCHPOINT_HIT_READ; |
| 1883 | } else { |
| 1884 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; |
| 1885 | } |
| 1886 | wp->hitaddr = vaddr; |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 1887 | if (!cpu->watchpoint_hit) { |
| 1888 | cpu->watchpoint_hit = wp; |
Andreas Färber | 239c51a | 2013-09-01 17:12:23 +0200 | [diff] [blame] | 1889 | tb_check_watchpoint(cpu); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1890 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 1891 | cpu->exception_index = EXCP_DEBUG; |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 1892 | cpu_loop_exit(cpu); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1893 | } else { |
| 1894 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
Andreas Färber | 648f034 | 2013-09-01 17:43:17 +0200 | [diff] [blame] | 1895 | tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); |
Andreas Färber | 0ea8cb8 | 2013-09-03 02:12:23 +0200 | [diff] [blame] | 1896 | cpu_resume_from_signal(cpu, NULL); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1897 | } |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 1898 | } |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1899 | } else { |
| 1900 | wp->flags &= ~BP_WATCHPOINT_HIT; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1901 | } |
| 1902 | } |
| 1903 | } |
| 1904 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1905 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 1906 | so these check for a hit then pass through to the normal out-of-line |
| 1907 | phys routines. */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 1908 | static uint64_t watch_mem_read(void *opaque, hwaddr addr, |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1909 | unsigned size) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1910 | { |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 1911 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, BP_MEM_READ); |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1912 | switch (size) { |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 1913 | case 1: return ldub_phys(&address_space_memory, addr); |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 1914 | case 2: return lduw_phys(&address_space_memory, addr); |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 1915 | case 4: return ldl_phys(&address_space_memory, addr); |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1916 | default: abort(); |
| 1917 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1918 | } |
| 1919 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 1920 | static void watch_mem_write(void *opaque, hwaddr addr, |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1921 | uint64_t val, unsigned size) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1922 | { |
Peter Maydell | 05068c0 | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 1923 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, BP_MEM_WRITE); |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1924 | switch (size) { |
Max Filippov | 6736415 | 2012-01-29 00:01:40 +0400 | [diff] [blame] | 1925 | case 1: |
Edgar E. Iglesias | db3be60 | 2013-12-17 15:29:06 +1000 | [diff] [blame] | 1926 | stb_phys(&address_space_memory, addr, val); |
Max Filippov | 6736415 | 2012-01-29 00:01:40 +0400 | [diff] [blame] | 1927 | break; |
| 1928 | case 2: |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 1929 | stw_phys(&address_space_memory, addr, val); |
Max Filippov | 6736415 | 2012-01-29 00:01:40 +0400 | [diff] [blame] | 1930 | break; |
| 1931 | case 4: |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 1932 | stl_phys(&address_space_memory, addr, val); |
Max Filippov | 6736415 | 2012-01-29 00:01:40 +0400 | [diff] [blame] | 1933 | break; |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1934 | default: abort(); |
| 1935 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1936 | } |
| 1937 | |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 1938 | static const MemoryRegionOps watch_mem_ops = { |
| 1939 | .read = watch_mem_read, |
| 1940 | .write = watch_mem_write, |
| 1941 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1942 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1943 | |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1944 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
| 1945 | unsigned len, MemTxAttrs attrs) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1946 | { |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1947 | subpage_t *subpage = opaque; |
Paolo Bonzini | ff6cff7 | 2014-12-22 13:11:39 +0100 | [diff] [blame] | 1948 | uint8_t buf[8]; |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1949 | MemTxResult res; |
Paolo Bonzini | 791af8c | 2013-05-24 16:10:39 +0200 | [diff] [blame] | 1950 | |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1951 | #if defined(DEBUG_SUBPAGE) |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 1952 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1953 | subpage, len, addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1954 | #endif |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1955 | res = address_space_read(subpage->as, addr + subpage->base, |
| 1956 | attrs, buf, len); |
| 1957 | if (res) { |
| 1958 | return res; |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1959 | } |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1960 | switch (len) { |
| 1961 | case 1: |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1962 | *data = ldub_p(buf); |
| 1963 | return MEMTX_OK; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1964 | case 2: |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1965 | *data = lduw_p(buf); |
| 1966 | return MEMTX_OK; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1967 | case 4: |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1968 | *data = ldl_p(buf); |
| 1969 | return MEMTX_OK; |
Paolo Bonzini | ff6cff7 | 2014-12-22 13:11:39 +0100 | [diff] [blame] | 1970 | case 8: |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1971 | *data = ldq_p(buf); |
| 1972 | return MEMTX_OK; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1973 | default: |
| 1974 | abort(); |
| 1975 | } |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1976 | } |
| 1977 | |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 1978 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
| 1979 | uint64_t value, unsigned len, MemTxAttrs attrs) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1980 | { |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1981 | subpage_t *subpage = opaque; |
Paolo Bonzini | ff6cff7 | 2014-12-22 13:11:39 +0100 | [diff] [blame] | 1982 | uint8_t buf[8]; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1983 | |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1984 | #if defined(DEBUG_SUBPAGE) |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 1985 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1986 | " value %"PRIx64"\n", |
| 1987 | __func__, subpage, len, addr, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 1988 | #endif |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 1989 | switch (len) { |
| 1990 | case 1: |
| 1991 | stb_p(buf, value); |
| 1992 | break; |
| 1993 | case 2: |
| 1994 | stw_p(buf, value); |
| 1995 | break; |
| 1996 | case 4: |
| 1997 | stl_p(buf, value); |
| 1998 | break; |
Paolo Bonzini | ff6cff7 | 2014-12-22 13:11:39 +0100 | [diff] [blame] | 1999 | case 8: |
| 2000 | stq_p(buf, value); |
| 2001 | break; |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2002 | default: |
| 2003 | abort(); |
| 2004 | } |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2005 | return address_space_write(subpage->as, addr + subpage->base, |
| 2006 | attrs, buf, len); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2007 | } |
| 2008 | |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2009 | static bool subpage_accepts(void *opaque, hwaddr addr, |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 2010 | unsigned len, bool is_write) |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2011 | { |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2012 | subpage_t *subpage = opaque; |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2013 | #if defined(DEBUG_SUBPAGE) |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 2014 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2015 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2016 | #endif |
| 2017 | |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2018 | return address_space_access_valid(subpage->as, addr + subpage->base, |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 2019 | len, is_write); |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2020 | } |
| 2021 | |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 2022 | static const MemoryRegionOps subpage_ops = { |
Peter Maydell | f25a49e | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2023 | .read_with_attrs = subpage_read, |
| 2024 | .write_with_attrs = subpage_write, |
Paolo Bonzini | ff6cff7 | 2014-12-22 13:11:39 +0100 | [diff] [blame] | 2025 | .impl.min_access_size = 1, |
| 2026 | .impl.max_access_size = 8, |
| 2027 | .valid.min_access_size = 1, |
| 2028 | .valid.max_access_size = 8, |
Paolo Bonzini | c353e4c | 2013-05-24 14:02:39 +0200 | [diff] [blame] | 2029 | .valid.accepts = subpage_accepts, |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 2030 | .endianness = DEVICE_NATIVE_ENDIAN, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2031 | }; |
| 2032 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2033 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2034 | uint16_t section) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2035 | { |
| 2036 | int idx, eidx; |
| 2037 | |
| 2038 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 2039 | return -1; |
| 2040 | idx = SUBPAGE_IDX(start); |
| 2041 | eidx = SUBPAGE_IDX(end); |
| 2042 | #if defined(DEBUG_SUBPAGE) |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 2043 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
| 2044 | __func__, mmio, start, end, idx, eidx, section); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2045 | #endif |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2046 | for (; idx <= eidx; idx++) { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2047 | mmio->sub_section[idx] = section; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2048 | } |
| 2049 | |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2053 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2054 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2055 | subpage_t *mmio; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2056 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2057 | mmio = g_malloc0(sizeof(subpage_t)); |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 2058 | |
Jan Kiszka | acc9d80 | 2013-05-26 21:55:37 +0200 | [diff] [blame] | 2059 | mmio->as = as; |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 2060 | mmio->base = base; |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 2061 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
Peter Crosthwaite | b4fefef | 2014-06-05 23:15:52 -0700 | [diff] [blame] | 2062 | NULL, TARGET_PAGE_SIZE); |
Avi Kivity | b3b00c7 | 2012-01-02 13:20:11 +0200 | [diff] [blame] | 2063 | mmio->iomem.subpage = true; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2064 | #if defined(DEBUG_SUBPAGE) |
Amos Kong | 016e9d6 | 2013-09-27 09:25:38 +0800 | [diff] [blame] | 2065 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
| 2066 | mmio, base, TARGET_PAGE_SIZE); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2067 | #endif |
Liu Ping Fan | b41aac4 | 2013-05-29 11:09:17 +0200 | [diff] [blame] | 2068 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2069 | |
| 2070 | return mmio; |
| 2071 | } |
| 2072 | |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2073 | static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as, |
| 2074 | MemoryRegion *mr) |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2075 | { |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2076 | assert(as); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2077 | MemoryRegionSection section = { |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2078 | .address_space = as, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2079 | .mr = mr, |
| 2080 | .offset_within_address_space = 0, |
| 2081 | .offset_within_region = 0, |
Paolo Bonzini | 052e87b | 2013-05-27 10:08:27 +0200 | [diff] [blame] | 2082 | .size = int128_2_64(), |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2083 | }; |
| 2084 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2085 | return phys_section_add(map, §ion); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2086 | } |
| 2087 | |
Paolo Bonzini | 9d82b5a | 2013-08-16 08:26:30 +0200 | [diff] [blame] | 2088 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index) |
Avi Kivity | aa10223 | 2012-03-08 17:06:55 +0200 | [diff] [blame] | 2089 | { |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 2090 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->memory_dispatch); |
| 2091 | MemoryRegionSection *sections = d->map.sections; |
Paolo Bonzini | 9d82b5a | 2013-08-16 08:26:30 +0200 | [diff] [blame] | 2092 | |
| 2093 | return sections[index & ~TARGET_PAGE_MASK].mr; |
Avi Kivity | aa10223 | 2012-03-08 17:06:55 +0200 | [diff] [blame] | 2094 | } |
| 2095 | |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 2096 | static void io_mem_init(void) |
| 2097 | { |
Paolo Bonzini | 1f6245e | 2014-06-13 10:48:06 +0200 | [diff] [blame] | 2098 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 2099 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
Paolo Bonzini | 1f6245e | 2014-06-13 10:48:06 +0200 | [diff] [blame] | 2100 | NULL, UINT64_MAX); |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 2101 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
Paolo Bonzini | 1f6245e | 2014-06-13 10:48:06 +0200 | [diff] [blame] | 2102 | NULL, UINT64_MAX); |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 2103 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
Paolo Bonzini | 1f6245e | 2014-06-13 10:48:06 +0200 | [diff] [blame] | 2104 | NULL, UINT64_MAX); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 2105 | } |
| 2106 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2107 | static void mem_begin(MemoryListener *listener) |
| 2108 | { |
Paolo Bonzini | 89ae337 | 2013-06-02 10:39:07 +0200 | [diff] [blame] | 2109 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2110 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
| 2111 | uint16_t n; |
| 2112 | |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2113 | n = dummy_section(&d->map, as, &io_mem_unassigned); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2114 | assert(n == PHYS_SECTION_UNASSIGNED); |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2115 | n = dummy_section(&d->map, as, &io_mem_notdirty); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2116 | assert(n == PHYS_SECTION_NOTDIRTY); |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2117 | n = dummy_section(&d->map, as, &io_mem_rom); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2118 | assert(n == PHYS_SECTION_ROM); |
Peter Crosthwaite | a656e22 | 2014-06-02 19:08:44 -0700 | [diff] [blame] | 2119 | n = dummy_section(&d->map, as, &io_mem_watch); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2120 | assert(n == PHYS_SECTION_WATCH); |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 2121 | |
Michael S. Tsirkin | 9736e55 | 2013-11-11 14:42:43 +0200 | [diff] [blame] | 2122 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 2123 | d->as = as; |
| 2124 | as->next_dispatch = d; |
| 2125 | } |
| 2126 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 2127 | static void address_space_dispatch_free(AddressSpaceDispatch *d) |
| 2128 | { |
| 2129 | phys_sections_free(&d->map); |
| 2130 | g_free(d); |
| 2131 | } |
| 2132 | |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 2133 | static void mem_commit(MemoryListener *listener) |
| 2134 | { |
| 2135 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
Paolo Bonzini | 0475d94 | 2013-05-29 12:28:21 +0200 | [diff] [blame] | 2136 | AddressSpaceDispatch *cur = as->dispatch; |
| 2137 | AddressSpaceDispatch *next = as->next_dispatch; |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2138 | |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2139 | phys_page_compact_all(next, next->map.nodes_nb); |
Michael S. Tsirkin | b35ba30 | 2013-11-11 17:52:07 +0200 | [diff] [blame] | 2140 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 2141 | atomic_rcu_set(&as->dispatch, next); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2142 | if (cur) { |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 2143 | call_rcu(cur, address_space_dispatch_free, rcu); |
Marcel Apfelbaum | 53cb28c | 2013-12-01 14:02:23 +0200 | [diff] [blame] | 2144 | } |
Paolo Bonzini | 9affd6f | 2013-05-29 12:09:47 +0200 | [diff] [blame] | 2145 | } |
| 2146 | |
Avi Kivity | 1d71148 | 2012-10-02 18:54:45 +0200 | [diff] [blame] | 2147 | static void tcg_commit(MemoryListener *listener) |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 2148 | { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 2149 | CPUState *cpu; |
Avi Kivity | 117712c | 2012-02-12 21:23:17 +0200 | [diff] [blame] | 2150 | |
| 2151 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2152 | reset the modified entries */ |
| 2153 | /* XXX: slow ! */ |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 2154 | CPU_FOREACH(cpu) { |
Edgar E. Iglesias | 33bde2e | 2013-11-21 19:06:30 +0100 | [diff] [blame] | 2155 | /* FIXME: Disentangle the cpu.h circular files deps so we can |
| 2156 | directly get the right CPU from listener. */ |
| 2157 | if (cpu->tcg_as_listener != listener) { |
| 2158 | continue; |
| 2159 | } |
Paolo Bonzini | 76e5c76 | 2015-01-15 12:46:47 +0100 | [diff] [blame] | 2160 | cpu_reload_memory_map(cpu); |
Avi Kivity | 117712c | 2012-02-12 21:23:17 +0200 | [diff] [blame] | 2161 | } |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 2162 | } |
| 2163 | |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2164 | static void core_log_global_start(MemoryListener *listener) |
| 2165 | { |
Juan Quintela | 981fdf2 | 2013-10-10 11:54:09 +0200 | [diff] [blame] | 2166 | cpu_physical_memory_set_dirty_tracking(true); |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2167 | } |
| 2168 | |
| 2169 | static void core_log_global_stop(MemoryListener *listener) |
| 2170 | { |
Juan Quintela | 981fdf2 | 2013-10-10 11:54:09 +0200 | [diff] [blame] | 2171 | cpu_physical_memory_set_dirty_tracking(false); |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2172 | } |
| 2173 | |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2174 | static MemoryListener core_memory_listener = { |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2175 | .log_global_start = core_log_global_start, |
| 2176 | .log_global_stop = core_log_global_stop, |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2177 | .priority = 1, |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2178 | }; |
| 2179 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2180 | void address_space_init_dispatch(AddressSpace *as) |
| 2181 | { |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 2182 | as->dispatch = NULL; |
Paolo Bonzini | 89ae337 | 2013-06-02 10:39:07 +0200 | [diff] [blame] | 2183 | as->dispatch_listener = (MemoryListener) { |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2184 | .begin = mem_begin, |
Paolo Bonzini | 0075270 | 2013-05-29 12:13:54 +0200 | [diff] [blame] | 2185 | .commit = mem_commit, |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2186 | .region_add = mem_add, |
| 2187 | .region_nop = mem_add, |
| 2188 | .priority = 0, |
| 2189 | }; |
Paolo Bonzini | 89ae337 | 2013-06-02 10:39:07 +0200 | [diff] [blame] | 2190 | memory_listener_register(&as->dispatch_listener, as); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2191 | } |
| 2192 | |
Paolo Bonzini | 6e48e8f | 2015-02-10 10:25:44 -0700 | [diff] [blame] | 2193 | void address_space_unregister(AddressSpace *as) |
| 2194 | { |
| 2195 | memory_listener_unregister(&as->dispatch_listener); |
| 2196 | } |
| 2197 | |
Avi Kivity | 83f3c25 | 2012-10-07 12:59:55 +0200 | [diff] [blame] | 2198 | void address_space_destroy_dispatch(AddressSpace *as) |
| 2199 | { |
| 2200 | AddressSpaceDispatch *d = as->dispatch; |
| 2201 | |
Paolo Bonzini | 79e2b9a | 2015-01-21 12:09:14 +0100 | [diff] [blame] | 2202 | atomic_rcu_set(&as->dispatch, NULL); |
| 2203 | if (d) { |
| 2204 | call_rcu(d, address_space_dispatch_free, rcu); |
| 2205 | } |
Avi Kivity | 83f3c25 | 2012-10-07 12:59:55 +0200 | [diff] [blame] | 2206 | } |
| 2207 | |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 2208 | static void memory_map_init(void) |
| 2209 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2210 | system_memory = g_malloc(sizeof(*system_memory)); |
Paolo Bonzini | 03f4995 | 2013-11-07 17:14:36 +0100 | [diff] [blame] | 2211 | |
Paolo Bonzini | 57271d6 | 2013-11-07 17:14:37 +0100 | [diff] [blame] | 2212 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
Alexey Kardashevskiy | 7dca804 | 2013-04-29 16:25:51 +0000 | [diff] [blame] | 2213 | address_space_init(&address_space_memory, system_memory, "memory"); |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 2214 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2215 | system_io = g_malloc(sizeof(*system_io)); |
Jan Kiszka | 3bb28b7 | 2013-09-02 18:43:30 +0200 | [diff] [blame] | 2216 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
| 2217 | 65536); |
Alexey Kardashevskiy | 7dca804 | 2013-04-29 16:25:51 +0000 | [diff] [blame] | 2218 | address_space_init(&address_space_io, system_io, "I/O"); |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 2219 | |
Avi Kivity | f6790af | 2012-10-02 20:13:51 +0200 | [diff] [blame] | 2220 | memory_listener_register(&core_memory_listener, &address_space_memory); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 2221 | } |
| 2222 | |
| 2223 | MemoryRegion *get_system_memory(void) |
| 2224 | { |
| 2225 | return system_memory; |
| 2226 | } |
| 2227 | |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 2228 | MemoryRegion *get_system_io(void) |
| 2229 | { |
| 2230 | return system_io; |
| 2231 | } |
| 2232 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2233 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 2234 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2235 | /* physical memory access (slow version, mainly for debug) */ |
| 2236 | #if defined(CONFIG_USER_ONLY) |
Andreas Färber | f17ec44 | 2013-06-29 19:40:58 +0200 | [diff] [blame] | 2237 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2238 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2239 | { |
| 2240 | int l, flags; |
| 2241 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2242 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2243 | |
| 2244 | while (len > 0) { |
| 2245 | page = addr & TARGET_PAGE_MASK; |
| 2246 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 2247 | if (l > len) |
| 2248 | l = len; |
| 2249 | flags = page_get_flags(page); |
| 2250 | if (!(flags & PAGE_VALID)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2251 | return -1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2252 | if (is_write) { |
| 2253 | if (!(flags & PAGE_WRITE)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2254 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2255 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2256 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2257 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2258 | memcpy(p, buf, l); |
| 2259 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2260 | } else { |
| 2261 | if (!(flags & PAGE_READ)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2262 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2263 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2264 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2265 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2266 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 2267 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2268 | } |
| 2269 | len -= l; |
| 2270 | buf += l; |
| 2271 | addr += l; |
| 2272 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 2273 | return 0; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2274 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2275 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2276 | #else |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 2277 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2278 | static void invalidate_and_set_dirty(hwaddr addr, |
| 2279 | hwaddr length) |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 2280 | { |
Peter Maydell | f874bf9 | 2014-11-16 19:44:21 +0000 | [diff] [blame] | 2281 | if (cpu_physical_memory_range_includes_clean(addr, length)) { |
| 2282 | tb_invalidate_phys_range(addr, addr + length, 0); |
Paolo Bonzini | 6886867 | 2014-07-21 16:45:18 +0200 | [diff] [blame] | 2283 | cpu_physical_memory_set_dirty_range_nocode(addr, length); |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 2284 | } |
Anthony PERARD | e226939 | 2012-10-03 13:49:22 +0000 | [diff] [blame] | 2285 | xen_modified_memory(addr, length); |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 2286 | } |
| 2287 | |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2288 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
Paolo Bonzini | 82f2563 | 2013-05-24 11:59:43 +0200 | [diff] [blame] | 2289 | { |
Paolo Bonzini | e1622f4 | 2013-07-17 13:17:41 +0200 | [diff] [blame] | 2290 | unsigned access_size_max = mr->ops->valid.max_access_size; |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2291 | |
| 2292 | /* Regions are assumed to support 1-4 byte accesses unless |
| 2293 | otherwise specified. */ |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2294 | if (access_size_max == 0) { |
| 2295 | access_size_max = 4; |
Paolo Bonzini | 82f2563 | 2013-05-24 11:59:43 +0200 | [diff] [blame] | 2296 | } |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2297 | |
| 2298 | /* Bound the maximum access by the alignment of the address. */ |
| 2299 | if (!mr->ops->impl.unaligned) { |
| 2300 | unsigned align_size_max = addr & -addr; |
| 2301 | if (align_size_max != 0 && align_size_max < access_size_max) { |
| 2302 | access_size_max = align_size_max; |
| 2303 | } |
| 2304 | } |
| 2305 | |
| 2306 | /* Don't attempt accesses larger than the maximum. */ |
| 2307 | if (l > access_size_max) { |
| 2308 | l = access_size_max; |
| 2309 | } |
Paolo Bonzini | 098178f | 2013-07-29 14:27:39 +0200 | [diff] [blame] | 2310 | if (l & (l - 1)) { |
| 2311 | l = 1 << (qemu_fls(l) - 1); |
| 2312 | } |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2313 | |
| 2314 | return l; |
Paolo Bonzini | 82f2563 | 2013-05-24 11:59:43 +0200 | [diff] [blame] | 2315 | } |
| 2316 | |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2317 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
| 2318 | uint8_t *buf, int len, bool is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2319 | { |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2320 | hwaddr l; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2321 | uint8_t *ptr; |
Paolo Bonzini | 791af8c | 2013-05-24 16:10:39 +0200 | [diff] [blame] | 2322 | uint64_t val; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2323 | hwaddr addr1; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2324 | MemoryRegion *mr; |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2325 | MemTxResult result = MEMTX_OK; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2326 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2327 | while (len > 0) { |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2328 | l = len; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2329 | mr = address_space_translate(as, addr, &addr1, &l, is_write); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2330 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2331 | if (is_write) { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2332 | if (!memory_access_is_direct(mr, is_write)) { |
| 2333 | l = memory_access_size(mr, l, addr1); |
Andreas Färber | 4917cf4 | 2013-05-27 05:17:50 +0200 | [diff] [blame] | 2334 | /* XXX: could force current_cpu to NULL to avoid |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2335 | potential bugs */ |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2336 | switch (l) { |
| 2337 | case 8: |
| 2338 | /* 64 bit write access */ |
| 2339 | val = ldq_p(buf); |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2340 | result |= memory_region_dispatch_write(mr, addr1, val, 8, |
| 2341 | attrs); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2342 | break; |
| 2343 | case 4: |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2344 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2345 | val = ldl_p(buf); |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2346 | result |= memory_region_dispatch_write(mr, addr1, val, 4, |
| 2347 | attrs); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2348 | break; |
| 2349 | case 2: |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2350 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2351 | val = lduw_p(buf); |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2352 | result |= memory_region_dispatch_write(mr, addr1, val, 2, |
| 2353 | attrs); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2354 | break; |
| 2355 | case 1: |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2356 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2357 | val = ldub_p(buf); |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2358 | result |= memory_region_dispatch_write(mr, addr1, val, 1, |
| 2359 | attrs); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2360 | break; |
| 2361 | default: |
| 2362 | abort(); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2363 | } |
Paolo Bonzini | 2bbfa05 | 2013-05-24 12:29:54 +0200 | [diff] [blame] | 2364 | } else { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2365 | addr1 += memory_region_get_ram_addr(mr); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2366 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2367 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2368 | memcpy(ptr, buf, l); |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 2369 | invalidate_and_set_dirty(addr1, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2370 | } |
| 2371 | } else { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2372 | if (!memory_access_is_direct(mr, is_write)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2373 | /* I/O case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2374 | l = memory_access_size(mr, l, addr1); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2375 | switch (l) { |
| 2376 | case 8: |
| 2377 | /* 64 bit read access */ |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2378 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, |
| 2379 | attrs); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2380 | stq_p(buf, val); |
| 2381 | break; |
| 2382 | case 4: |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2383 | /* 32 bit read access */ |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2384 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, |
| 2385 | attrs); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2386 | stl_p(buf, val); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2387 | break; |
| 2388 | case 2: |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2389 | /* 16 bit read access */ |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2390 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, |
| 2391 | attrs); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2392 | stw_p(buf, val); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2393 | break; |
| 2394 | case 1: |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2395 | /* 8 bit read access */ |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2396 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, |
| 2397 | attrs); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2398 | stb_p(buf, val); |
Richard Henderson | 2332616 | 2013-07-08 14:55:59 -0700 | [diff] [blame] | 2399 | break; |
| 2400 | default: |
| 2401 | abort(); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2402 | } |
| 2403 | } else { |
| 2404 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2405 | ptr = qemu_get_ram_ptr(mr->ram_addr + addr1); |
Avi Kivity | f3705d5 | 2012-03-08 16:16:34 +0200 | [diff] [blame] | 2406 | memcpy(buf, ptr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2407 | } |
| 2408 | } |
| 2409 | len -= l; |
| 2410 | buf += l; |
| 2411 | addr += l; |
| 2412 | } |
Paolo Bonzini | fd8aaa7 | 2013-05-21 09:56:55 +0200 | [diff] [blame] | 2413 | |
Peter Maydell | 3b64349 | 2015-04-26 16:49:23 +0100 | [diff] [blame] | 2414 | return result; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2415 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2416 | |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2417 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
| 2418 | const uint8_t *buf, int len) |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2419 | { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2420 | return address_space_rw(as, addr, attrs, (uint8_t *)buf, len, true); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2421 | } |
| 2422 | |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2423 | MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
| 2424 | uint8_t *buf, int len) |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2425 | { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2426 | return address_space_rw(as, addr, attrs, buf, len, false); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2427 | } |
| 2428 | |
| 2429 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2430 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2431 | int len, int is_write) |
| 2432 | { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2433 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
| 2434 | buf, len, is_write); |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2435 | } |
| 2436 | |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2437 | enum write_rom_type { |
| 2438 | WRITE_DATA, |
| 2439 | FLUSH_CACHE, |
| 2440 | }; |
| 2441 | |
Edgar E. Iglesias | 2a22165 | 2013-12-13 16:28:52 +1000 | [diff] [blame] | 2442 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2443 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2444 | { |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2445 | hwaddr l; |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2446 | uint8_t *ptr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2447 | hwaddr addr1; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2448 | MemoryRegion *mr; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2449 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2450 | while (len > 0) { |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2451 | l = len; |
Edgar E. Iglesias | 2a22165 | 2013-12-13 16:28:52 +1000 | [diff] [blame] | 2452 | mr = address_space_translate(as, addr, &addr1, &l, true); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2453 | |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2454 | if (!(memory_region_is_ram(mr) || |
| 2455 | memory_region_is_romd(mr))) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2456 | /* do nothing */ |
| 2457 | } else { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2458 | addr1 += memory_region_get_ram_addr(mr); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2459 | /* ROM/RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2460 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2461 | switch (type) { |
| 2462 | case WRITE_DATA: |
| 2463 | memcpy(ptr, buf, l); |
| 2464 | invalidate_and_set_dirty(addr1, l); |
| 2465 | break; |
| 2466 | case FLUSH_CACHE: |
| 2467 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); |
| 2468 | break; |
| 2469 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2470 | } |
| 2471 | len -= l; |
| 2472 | buf += l; |
| 2473 | addr += l; |
| 2474 | } |
| 2475 | } |
| 2476 | |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2477 | /* used for ROM loading : can write in RAM and ROM */ |
Edgar E. Iglesias | 2a22165 | 2013-12-13 16:28:52 +1000 | [diff] [blame] | 2478 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2479 | const uint8_t *buf, int len) |
| 2480 | { |
Edgar E. Iglesias | 2a22165 | 2013-12-13 16:28:52 +1000 | [diff] [blame] | 2481 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2482 | } |
| 2483 | |
| 2484 | void cpu_flush_icache_range(hwaddr start, int len) |
| 2485 | { |
| 2486 | /* |
| 2487 | * This function should do the same thing as an icache flush that was |
| 2488 | * triggered from within the guest. For TCG we are always cache coherent, |
| 2489 | * so there is no need to flush anything. For KVM / Xen we need to flush |
| 2490 | * the host's instruction cache at least. |
| 2491 | */ |
| 2492 | if (tcg_enabled()) { |
| 2493 | return; |
| 2494 | } |
| 2495 | |
Edgar E. Iglesias | 2a22165 | 2013-12-13 16:28:52 +1000 | [diff] [blame] | 2496 | cpu_physical_memory_write_rom_internal(&address_space_memory, |
| 2497 | start, NULL, len, FLUSH_CACHE); |
Alexander Graf | 582b55a | 2013-12-11 14:17:44 +0100 | [diff] [blame] | 2498 | } |
| 2499 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2500 | typedef struct { |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2501 | MemoryRegion *mr; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2502 | void *buffer; |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2503 | hwaddr addr; |
| 2504 | hwaddr len; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2505 | } BounceBuffer; |
| 2506 | |
| 2507 | static BounceBuffer bounce; |
| 2508 | |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2509 | typedef struct MapClient { |
| 2510 | void *opaque; |
| 2511 | void (*callback)(void *opaque); |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2512 | QLIST_ENTRY(MapClient) link; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2513 | } MapClient; |
| 2514 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2515 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
| 2516 | = QLIST_HEAD_INITIALIZER(map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2517 | |
| 2518 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 2519 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2520 | MapClient *client = g_malloc(sizeof(*client)); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2521 | |
| 2522 | client->opaque = opaque; |
| 2523 | client->callback = callback; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2524 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2525 | return client; |
| 2526 | } |
| 2527 | |
Blue Swirl | 8b9c99d | 2012-10-28 11:04:51 +0000 | [diff] [blame] | 2528 | static void cpu_unregister_map_client(void *_client) |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2529 | { |
| 2530 | MapClient *client = (MapClient *)_client; |
| 2531 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2532 | QLIST_REMOVE(client, link); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2533 | g_free(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2534 | } |
| 2535 | |
| 2536 | static void cpu_notify_map_clients(void) |
| 2537 | { |
| 2538 | MapClient *client; |
| 2539 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2540 | while (!QLIST_EMPTY(&map_client_list)) { |
| 2541 | client = QLIST_FIRST(&map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2542 | client->callback(client->opaque); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 2543 | cpu_unregister_map_client(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2544 | } |
| 2545 | } |
| 2546 | |
Paolo Bonzini | 51644ab | 2013-04-11 15:40:59 +0200 | [diff] [blame] | 2547 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write) |
| 2548 | { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2549 | MemoryRegion *mr; |
Paolo Bonzini | 51644ab | 2013-04-11 15:40:59 +0200 | [diff] [blame] | 2550 | hwaddr l, xlat; |
| 2551 | |
| 2552 | while (len > 0) { |
| 2553 | l = len; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2554 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2555 | if (!memory_access_is_direct(mr, is_write)) { |
| 2556 | l = memory_access_size(mr, l, addr); |
| 2557 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { |
Paolo Bonzini | 51644ab | 2013-04-11 15:40:59 +0200 | [diff] [blame] | 2558 | return false; |
| 2559 | } |
| 2560 | } |
| 2561 | |
| 2562 | len -= l; |
| 2563 | addr += l; |
| 2564 | } |
| 2565 | return true; |
| 2566 | } |
| 2567 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2568 | /* Map a physical memory region into a host virtual address. |
| 2569 | * May map a subset of the requested range, given by and returned in *plen. |
| 2570 | * May return NULL if resources needed to perform the mapping are exhausted. |
| 2571 | * Use only for reads OR writes - not for read-modify-write operations. |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2572 | * Use cpu_register_map_client() to know when retrying the map operation is |
| 2573 | * likely to succeed. |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2574 | */ |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2575 | void *address_space_map(AddressSpace *as, |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2576 | hwaddr addr, |
| 2577 | hwaddr *plen, |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2578 | bool is_write) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2579 | { |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2580 | hwaddr len = *plen; |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2581 | hwaddr done = 0; |
| 2582 | hwaddr l, xlat, base; |
| 2583 | MemoryRegion *mr, *this_mr; |
| 2584 | ram_addr_t raddr; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2585 | |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2586 | if (len == 0) { |
| 2587 | return NULL; |
| 2588 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2589 | |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2590 | l = len; |
| 2591 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2592 | if (!memory_access_is_direct(mr, is_write)) { |
| 2593 | if (bounce.buffer) { |
| 2594 | return NULL; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2595 | } |
Kevin Wolf | e85d9db | 2013-07-22 14:30:23 +0200 | [diff] [blame] | 2596 | /* Avoid unbounded allocations */ |
| 2597 | l = MIN(l, TARGET_PAGE_SIZE); |
| 2598 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2599 | bounce.addr = addr; |
| 2600 | bounce.len = l; |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2601 | |
| 2602 | memory_region_ref(mr); |
| 2603 | bounce.mr = mr; |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2604 | if (!is_write) { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2605 | address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED, |
| 2606 | bounce.buffer, l); |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 2607 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2608 | |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2609 | *plen = l; |
| 2610 | return bounce.buffer; |
| 2611 | } |
| 2612 | |
| 2613 | base = xlat; |
| 2614 | raddr = memory_region_get_ram_addr(mr); |
| 2615 | |
| 2616 | for (;;) { |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2617 | len -= l; |
| 2618 | addr += l; |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2619 | done += l; |
| 2620 | if (len == 0) { |
| 2621 | break; |
| 2622 | } |
| 2623 | |
| 2624 | l = len; |
| 2625 | this_mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2626 | if (this_mr != mr || xlat != base + done) { |
| 2627 | break; |
| 2628 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2629 | } |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2630 | |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2631 | memory_region_ref(mr); |
Paolo Bonzini | e3127ae | 2013-06-28 17:29:27 +0200 | [diff] [blame] | 2632 | *plen = done; |
| 2633 | return qemu_ram_ptr_length(raddr + base, plen); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2634 | } |
| 2635 | |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2636 | /* Unmaps a memory region previously mapped by address_space_map(). |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2637 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
| 2638 | * the amount of memory that was actually read or written by the caller. |
| 2639 | */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2640 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
| 2641 | int is_write, hwaddr access_len) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2642 | { |
| 2643 | if (buffer != bounce.buffer) { |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2644 | MemoryRegion *mr; |
| 2645 | ram_addr_t addr1; |
| 2646 | |
| 2647 | mr = qemu_ram_addr_from_host(buffer, &addr1); |
| 2648 | assert(mr != NULL); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2649 | if (is_write) { |
Paolo Bonzini | 6886867 | 2014-07-21 16:45:18 +0200 | [diff] [blame] | 2650 | invalidate_and_set_dirty(addr1, access_len); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2651 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 2652 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 2653 | xen_invalidate_map_cache_entry(buffer); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 2654 | } |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2655 | memory_region_unref(mr); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2656 | return; |
| 2657 | } |
| 2658 | if (is_write) { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 2659 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
| 2660 | bounce.buffer, access_len); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2661 | } |
Herve Poussineau | f8a8324 | 2010-01-24 21:23:56 +0000 | [diff] [blame] | 2662 | qemu_vfree(bounce.buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2663 | bounce.buffer = NULL; |
Paolo Bonzini | d3e7155 | 2013-06-28 17:33:29 +0200 | [diff] [blame] | 2664 | memory_region_unref(bounce.mr); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 2665 | cpu_notify_map_clients(); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 2666 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2667 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2668 | void *cpu_physical_memory_map(hwaddr addr, |
| 2669 | hwaddr *plen, |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2670 | int is_write) |
| 2671 | { |
| 2672 | return address_space_map(&address_space_memory, addr, plen, is_write); |
| 2673 | } |
| 2674 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 2675 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
| 2676 | int is_write, hwaddr access_len) |
Avi Kivity | ac1970f | 2012-10-03 16:22:53 +0200 | [diff] [blame] | 2677 | { |
| 2678 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); |
| 2679 | } |
| 2680 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2681 | /* warning: addr must be aligned */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2682 | static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr, |
| 2683 | MemTxAttrs attrs, |
| 2684 | MemTxResult *result, |
| 2685 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2686 | { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2687 | uint8_t *ptr; |
Paolo Bonzini | 791af8c | 2013-05-24 16:10:39 +0200 | [diff] [blame] | 2688 | uint64_t val; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2689 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2690 | hwaddr l = 4; |
| 2691 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2692 | MemTxResult r; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2693 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 2694 | mr = address_space_translate(as, addr, &addr1, &l, false); |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2695 | if (l < 4 || !memory_access_is_direct(mr, false)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2696 | /* I/O case */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2697 | r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2698 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 2699 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 2700 | val = bswap32(val); |
| 2701 | } |
| 2702 | #else |
| 2703 | if (endian == DEVICE_BIG_ENDIAN) { |
| 2704 | val = bswap32(val); |
| 2705 | } |
| 2706 | #endif |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2707 | } else { |
| 2708 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2709 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
Avi Kivity | 06ef352 | 2012-02-13 16:11:22 +0200 | [diff] [blame] | 2710 | & TARGET_PAGE_MASK) |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2711 | + addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2712 | switch (endian) { |
| 2713 | case DEVICE_LITTLE_ENDIAN: |
| 2714 | val = ldl_le_p(ptr); |
| 2715 | break; |
| 2716 | case DEVICE_BIG_ENDIAN: |
| 2717 | val = ldl_be_p(ptr); |
| 2718 | break; |
| 2719 | default: |
| 2720 | val = ldl_p(ptr); |
| 2721 | break; |
| 2722 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2723 | r = MEMTX_OK; |
| 2724 | } |
| 2725 | if (result) { |
| 2726 | *result = r; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2727 | } |
| 2728 | return val; |
| 2729 | } |
| 2730 | |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2731 | uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, |
| 2732 | MemTxAttrs attrs, MemTxResult *result) |
| 2733 | { |
| 2734 | return address_space_ldl_internal(as, addr, attrs, result, |
| 2735 | DEVICE_NATIVE_ENDIAN); |
| 2736 | } |
| 2737 | |
| 2738 | uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, |
| 2739 | MemTxAttrs attrs, MemTxResult *result) |
| 2740 | { |
| 2741 | return address_space_ldl_internal(as, addr, attrs, result, |
| 2742 | DEVICE_LITTLE_ENDIAN); |
| 2743 | } |
| 2744 | |
| 2745 | uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, |
| 2746 | MemTxAttrs attrs, MemTxResult *result) |
| 2747 | { |
| 2748 | return address_space_ldl_internal(as, addr, attrs, result, |
| 2749 | DEVICE_BIG_ENDIAN); |
| 2750 | } |
| 2751 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 2752 | uint32_t ldl_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2753 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2754 | return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2755 | } |
| 2756 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 2757 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2758 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2759 | return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2760 | } |
| 2761 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 2762 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2763 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2764 | return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2765 | } |
| 2766 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2767 | /* warning: addr must be aligned */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2768 | static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr, |
| 2769 | MemTxAttrs attrs, |
| 2770 | MemTxResult *result, |
| 2771 | enum device_endian endian) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2772 | { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2773 | uint8_t *ptr; |
| 2774 | uint64_t val; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2775 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2776 | hwaddr l = 8; |
| 2777 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2778 | MemTxResult r; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2779 | |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 2780 | mr = address_space_translate(as, addr, &addr1, &l, |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2781 | false); |
| 2782 | if (l < 8 || !memory_access_is_direct(mr, false)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2783 | /* I/O case */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2784 | r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs); |
Paolo Bonzini | 968a562 | 2013-05-24 17:58:37 +0200 | [diff] [blame] | 2785 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 2786 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 2787 | val = bswap64(val); |
| 2788 | } |
| 2789 | #else |
| 2790 | if (endian == DEVICE_BIG_ENDIAN) { |
| 2791 | val = bswap64(val); |
| 2792 | } |
| 2793 | #endif |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2794 | } else { |
| 2795 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2796 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
Avi Kivity | 06ef352 | 2012-02-13 16:11:22 +0200 | [diff] [blame] | 2797 | & TARGET_PAGE_MASK) |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2798 | + addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2799 | switch (endian) { |
| 2800 | case DEVICE_LITTLE_ENDIAN: |
| 2801 | val = ldq_le_p(ptr); |
| 2802 | break; |
| 2803 | case DEVICE_BIG_ENDIAN: |
| 2804 | val = ldq_be_p(ptr); |
| 2805 | break; |
| 2806 | default: |
| 2807 | val = ldq_p(ptr); |
| 2808 | break; |
| 2809 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2810 | r = MEMTX_OK; |
| 2811 | } |
| 2812 | if (result) { |
| 2813 | *result = r; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2814 | } |
| 2815 | return val; |
| 2816 | } |
| 2817 | |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2818 | uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, |
| 2819 | MemTxAttrs attrs, MemTxResult *result) |
| 2820 | { |
| 2821 | return address_space_ldq_internal(as, addr, attrs, result, |
| 2822 | DEVICE_NATIVE_ENDIAN); |
| 2823 | } |
| 2824 | |
| 2825 | uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, |
| 2826 | MemTxAttrs attrs, MemTxResult *result) |
| 2827 | { |
| 2828 | return address_space_ldq_internal(as, addr, attrs, result, |
| 2829 | DEVICE_LITTLE_ENDIAN); |
| 2830 | } |
| 2831 | |
| 2832 | uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, |
| 2833 | MemTxAttrs attrs, MemTxResult *result) |
| 2834 | { |
| 2835 | return address_space_ldq_internal(as, addr, attrs, result, |
| 2836 | DEVICE_BIG_ENDIAN); |
| 2837 | } |
| 2838 | |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 2839 | uint64_t ldq_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2840 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2841 | return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2842 | } |
| 2843 | |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 2844 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2845 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2846 | return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2847 | } |
| 2848 | |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 2849 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2850 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2851 | return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2852 | } |
| 2853 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 2854 | /* XXX: optimize */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2855 | uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, |
| 2856 | MemTxAttrs attrs, MemTxResult *result) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 2857 | { |
| 2858 | uint8_t val; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2859 | MemTxResult r; |
| 2860 | |
| 2861 | r = address_space_rw(as, addr, attrs, &val, 1, 0); |
| 2862 | if (result) { |
| 2863 | *result = r; |
| 2864 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 2865 | return val; |
| 2866 | } |
| 2867 | |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2868 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr) |
| 2869 | { |
| 2870 | return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
| 2871 | } |
| 2872 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2873 | /* warning: addr must be aligned */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2874 | static inline uint32_t address_space_lduw_internal(AddressSpace *as, |
| 2875 | hwaddr addr, |
| 2876 | MemTxAttrs attrs, |
| 2877 | MemTxResult *result, |
| 2878 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 2879 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2880 | uint8_t *ptr; |
| 2881 | uint64_t val; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2882 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2883 | hwaddr l = 2; |
| 2884 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2885 | MemTxResult r; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2886 | |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 2887 | mr = address_space_translate(as, addr, &addr1, &l, |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2888 | false); |
| 2889 | if (l < 2 || !memory_access_is_direct(mr, false)) { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2890 | /* I/O case */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2891 | r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2892 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 2893 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 2894 | val = bswap16(val); |
| 2895 | } |
| 2896 | #else |
| 2897 | if (endian == DEVICE_BIG_ENDIAN) { |
| 2898 | val = bswap16(val); |
| 2899 | } |
| 2900 | #endif |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2901 | } else { |
| 2902 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2903 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
Avi Kivity | 06ef352 | 2012-02-13 16:11:22 +0200 | [diff] [blame] | 2904 | & TARGET_PAGE_MASK) |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2905 | + addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2906 | switch (endian) { |
| 2907 | case DEVICE_LITTLE_ENDIAN: |
| 2908 | val = lduw_le_p(ptr); |
| 2909 | break; |
| 2910 | case DEVICE_BIG_ENDIAN: |
| 2911 | val = lduw_be_p(ptr); |
| 2912 | break; |
| 2913 | default: |
| 2914 | val = lduw_p(ptr); |
| 2915 | break; |
| 2916 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2917 | r = MEMTX_OK; |
| 2918 | } |
| 2919 | if (result) { |
| 2920 | *result = r; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 2921 | } |
| 2922 | return val; |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 2923 | } |
| 2924 | |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2925 | uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, |
| 2926 | MemTxAttrs attrs, MemTxResult *result) |
| 2927 | { |
| 2928 | return address_space_lduw_internal(as, addr, attrs, result, |
| 2929 | DEVICE_NATIVE_ENDIAN); |
| 2930 | } |
| 2931 | |
| 2932 | uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, |
| 2933 | MemTxAttrs attrs, MemTxResult *result) |
| 2934 | { |
| 2935 | return address_space_lduw_internal(as, addr, attrs, result, |
| 2936 | DEVICE_LITTLE_ENDIAN); |
| 2937 | } |
| 2938 | |
| 2939 | uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, |
| 2940 | MemTxAttrs attrs, MemTxResult *result) |
| 2941 | { |
| 2942 | return address_space_lduw_internal(as, addr, attrs, result, |
| 2943 | DEVICE_BIG_ENDIAN); |
| 2944 | } |
| 2945 | |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 2946 | uint32_t lduw_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2947 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2948 | return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2949 | } |
| 2950 | |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 2951 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2952 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2953 | return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2954 | } |
| 2955 | |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 2956 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2957 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2958 | return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 2959 | } |
| 2960 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2961 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 2962 | and the code inside is not invalidated. It is useful if the dirty |
| 2963 | bits are used to track modified PTEs */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2964 | void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, |
| 2965 | MemTxAttrs attrs, MemTxResult *result) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2966 | { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2967 | uint8_t *ptr; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2968 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 2969 | hwaddr l = 4; |
| 2970 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2971 | MemTxResult r; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2972 | |
Edgar E. Iglesias | 2198a12 | 2013-11-28 10:13:41 +0100 | [diff] [blame] | 2973 | mr = address_space_translate(as, addr, &addr1, &l, |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2974 | true); |
| 2975 | if (l < 4 || !memory_access_is_direct(mr, true)) { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2976 | r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2977 | } else { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 2978 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2979 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2980 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2981 | |
| 2982 | if (unlikely(in_migration)) { |
Juan Quintela | a2cd8c8 | 2013-10-10 11:20:22 +0200 | [diff] [blame] | 2983 | if (cpu_physical_memory_is_clean(addr1)) { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2984 | /* invalidate code */ |
| 2985 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 2986 | /* set dirty bit */ |
Paolo Bonzini | 6886867 | 2014-07-21 16:45:18 +0200 | [diff] [blame] | 2987 | cpu_physical_memory_set_dirty_range_nocode(addr1, 4); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2988 | } |
| 2989 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2990 | r = MEMTX_OK; |
| 2991 | } |
| 2992 | if (result) { |
| 2993 | *result = r; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2994 | } |
| 2995 | } |
| 2996 | |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 2997 | void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) |
| 2998 | { |
| 2999 | address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
| 3000 | } |
| 3001 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3002 | /* warning: addr must be aligned */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3003 | static inline void address_space_stl_internal(AddressSpace *as, |
| 3004 | hwaddr addr, uint32_t val, |
| 3005 | MemTxAttrs attrs, |
| 3006 | MemTxResult *result, |
| 3007 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3008 | { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3009 | uint8_t *ptr; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3010 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 3011 | hwaddr l = 4; |
| 3012 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3013 | MemTxResult r; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3014 | |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 3015 | mr = address_space_translate(as, addr, &addr1, &l, |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3016 | true); |
| 3017 | if (l < 4 || !memory_access_is_direct(mr, true)) { |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3018 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 3019 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 3020 | val = bswap32(val); |
| 3021 | } |
| 3022 | #else |
| 3023 | if (endian == DEVICE_BIG_ENDIAN) { |
| 3024 | val = bswap32(val); |
| 3025 | } |
| 3026 | #endif |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3027 | r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3028 | } else { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3029 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3030 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3031 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3032 | switch (endian) { |
| 3033 | case DEVICE_LITTLE_ENDIAN: |
| 3034 | stl_le_p(ptr, val); |
| 3035 | break; |
| 3036 | case DEVICE_BIG_ENDIAN: |
| 3037 | stl_be_p(ptr, val); |
| 3038 | break; |
| 3039 | default: |
| 3040 | stl_p(ptr, val); |
| 3041 | break; |
| 3042 | } |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 3043 | invalidate_and_set_dirty(addr1, 4); |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3044 | r = MEMTX_OK; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3045 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3046 | if (result) { |
| 3047 | *result = r; |
| 3048 | } |
| 3049 | } |
| 3050 | |
| 3051 | void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3052 | MemTxAttrs attrs, MemTxResult *result) |
| 3053 | { |
| 3054 | address_space_stl_internal(as, addr, val, attrs, result, |
| 3055 | DEVICE_NATIVE_ENDIAN); |
| 3056 | } |
| 3057 | |
| 3058 | void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3059 | MemTxAttrs attrs, MemTxResult *result) |
| 3060 | { |
| 3061 | address_space_stl_internal(as, addr, val, attrs, result, |
| 3062 | DEVICE_LITTLE_ENDIAN); |
| 3063 | } |
| 3064 | |
| 3065 | void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3066 | MemTxAttrs attrs, MemTxResult *result) |
| 3067 | { |
| 3068 | address_space_stl_internal(as, addr, val, attrs, result, |
| 3069 | DEVICE_BIG_ENDIAN); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3070 | } |
| 3071 | |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 3072 | void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3073 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3074 | address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3075 | } |
| 3076 | |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 3077 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3078 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3079 | address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3080 | } |
| 3081 | |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 3082 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3083 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3084 | address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3085 | } |
| 3086 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3087 | /* XXX: optimize */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3088 | void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3089 | MemTxAttrs attrs, MemTxResult *result) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3090 | { |
| 3091 | uint8_t v = val; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3092 | MemTxResult r; |
| 3093 | |
| 3094 | r = address_space_rw(as, addr, attrs, &v, 1, 1); |
| 3095 | if (result) { |
| 3096 | *result = r; |
| 3097 | } |
| 3098 | } |
| 3099 | |
| 3100 | void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
| 3101 | { |
| 3102 | address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3103 | } |
| 3104 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3105 | /* warning: addr must be aligned */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3106 | static inline void address_space_stw_internal(AddressSpace *as, |
| 3107 | hwaddr addr, uint32_t val, |
| 3108 | MemTxAttrs attrs, |
| 3109 | MemTxResult *result, |
| 3110 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3111 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3112 | uint8_t *ptr; |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3113 | MemoryRegion *mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 3114 | hwaddr l = 2; |
| 3115 | hwaddr addr1; |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3116 | MemTxResult r; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3117 | |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 3118 | mr = address_space_translate(as, addr, &addr1, &l, true); |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3119 | if (l < 2 || !memory_access_is_direct(mr, true)) { |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3120 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 3121 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 3122 | val = bswap16(val); |
| 3123 | } |
| 3124 | #else |
| 3125 | if (endian == DEVICE_BIG_ENDIAN) { |
| 3126 | val = bswap16(val); |
| 3127 | } |
| 3128 | #endif |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3129 | r = memory_region_dispatch_write(mr, addr1, val, 2, attrs); |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3130 | } else { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3131 | /* RAM case */ |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3132 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3133 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3134 | switch (endian) { |
| 3135 | case DEVICE_LITTLE_ENDIAN: |
| 3136 | stw_le_p(ptr, val); |
| 3137 | break; |
| 3138 | case DEVICE_BIG_ENDIAN: |
| 3139 | stw_be_p(ptr, val); |
| 3140 | break; |
| 3141 | default: |
| 3142 | stw_p(ptr, val); |
| 3143 | break; |
| 3144 | } |
Anthony PERARD | 51d7a9e | 2012-10-03 13:49:05 +0000 | [diff] [blame] | 3145 | invalidate_and_set_dirty(addr1, 2); |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3146 | r = MEMTX_OK; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3147 | } |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3148 | if (result) { |
| 3149 | *result = r; |
| 3150 | } |
| 3151 | } |
| 3152 | |
| 3153 | void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3154 | MemTxAttrs attrs, MemTxResult *result) |
| 3155 | { |
| 3156 | address_space_stw_internal(as, addr, val, attrs, result, |
| 3157 | DEVICE_NATIVE_ENDIAN); |
| 3158 | } |
| 3159 | |
| 3160 | void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3161 | MemTxAttrs attrs, MemTxResult *result) |
| 3162 | { |
| 3163 | address_space_stw_internal(as, addr, val, attrs, result, |
| 3164 | DEVICE_LITTLE_ENDIAN); |
| 3165 | } |
| 3166 | |
| 3167 | void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, |
| 3168 | MemTxAttrs attrs, MemTxResult *result) |
| 3169 | { |
| 3170 | address_space_stw_internal(as, addr, val, attrs, result, |
| 3171 | DEVICE_BIG_ENDIAN); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3172 | } |
| 3173 | |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 3174 | void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3175 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3176 | address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3177 | } |
| 3178 | |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 3179 | void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3180 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3181 | address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3182 | } |
| 3183 | |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 3184 | void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3185 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3186 | address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3187 | } |
| 3188 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3189 | /* XXX: optimize */ |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3190 | void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, |
| 3191 | MemTxAttrs attrs, MemTxResult *result) |
| 3192 | { |
| 3193 | MemTxResult r; |
| 3194 | val = tswap64(val); |
| 3195 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); |
| 3196 | if (result) { |
| 3197 | *result = r; |
| 3198 | } |
| 3199 | } |
| 3200 | |
| 3201 | void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, |
| 3202 | MemTxAttrs attrs, MemTxResult *result) |
| 3203 | { |
| 3204 | MemTxResult r; |
| 3205 | val = cpu_to_le64(val); |
| 3206 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); |
| 3207 | if (result) { |
| 3208 | *result = r; |
| 3209 | } |
| 3210 | } |
| 3211 | void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, |
| 3212 | MemTxAttrs attrs, MemTxResult *result) |
| 3213 | { |
| 3214 | MemTxResult r; |
| 3215 | val = cpu_to_be64(val); |
| 3216 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); |
| 3217 | if (result) { |
| 3218 | *result = r; |
| 3219 | } |
| 3220 | } |
| 3221 | |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 3222 | void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3223 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3224 | address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3225 | } |
| 3226 | |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 3227 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3228 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3229 | address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3230 | } |
| 3231 | |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 3232 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3233 | { |
Peter Maydell | 5001311 | 2015-04-26 16:49:24 +0100 | [diff] [blame^] | 3234 | address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 3235 | } |
| 3236 | |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 3237 | /* virtual memory access for debug (includes writing to ROM) */ |
Andreas Färber | f17ec44 | 2013-06-29 19:40:58 +0200 | [diff] [blame] | 3238 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3239 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3240 | { |
| 3241 | int l; |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 3242 | hwaddr phys_addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 3243 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3244 | |
| 3245 | while (len > 0) { |
| 3246 | page = addr & TARGET_PAGE_MASK; |
Andreas Färber | f17ec44 | 2013-06-29 19:40:58 +0200 | [diff] [blame] | 3247 | phys_addr = cpu_get_phys_page_debug(cpu, page); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3248 | /* if no physical page mapped, return an error */ |
| 3249 | if (phys_addr == -1) |
| 3250 | return -1; |
| 3251 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3252 | if (l > len) |
| 3253 | l = len; |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 3254 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
Edgar E. Iglesias | 2e38847 | 2013-12-13 16:31:02 +1000 | [diff] [blame] | 3255 | if (is_write) { |
| 3256 | cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l); |
| 3257 | } else { |
Peter Maydell | 5c9eb02 | 2015-04-26 16:49:24 +0100 | [diff] [blame] | 3258 | address_space_rw(cpu->as, phys_addr, MEMTXATTRS_UNSPECIFIED, |
| 3259 | buf, l, 0); |
Edgar E. Iglesias | 2e38847 | 2013-12-13 16:31:02 +1000 | [diff] [blame] | 3260 | } |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3261 | len -= l; |
| 3262 | buf += l; |
| 3263 | addr += l; |
| 3264 | } |
| 3265 | return 0; |
| 3266 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3267 | #endif |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3268 | |
Blue Swirl | 8e4a424 | 2013-01-06 18:30:17 +0000 | [diff] [blame] | 3269 | /* |
| 3270 | * A helper function for the _utterly broken_ virtio device model to find out if |
| 3271 | * it's running on a big endian machine. Don't do this at home kids! |
| 3272 | */ |
Greg Kurz | 98ed8ec | 2014-06-24 19:26:29 +0200 | [diff] [blame] | 3273 | bool target_words_bigendian(void); |
| 3274 | bool target_words_bigendian(void) |
Blue Swirl | 8e4a424 | 2013-01-06 18:30:17 +0000 | [diff] [blame] | 3275 | { |
| 3276 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 3277 | return true; |
| 3278 | #else |
| 3279 | return false; |
| 3280 | #endif |
| 3281 | } |
| 3282 | |
Wen Congyang | 76f3553 | 2012-05-07 12:04:18 +0800 | [diff] [blame] | 3283 | #ifndef CONFIG_USER_ONLY |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 3284 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
Wen Congyang | 76f3553 | 2012-05-07 12:04:18 +0800 | [diff] [blame] | 3285 | { |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3286 | MemoryRegion*mr; |
Paolo Bonzini | 149f54b | 2013-05-24 12:59:37 +0200 | [diff] [blame] | 3287 | hwaddr l = 1; |
Wen Congyang | 76f3553 | 2012-05-07 12:04:18 +0800 | [diff] [blame] | 3288 | |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3289 | mr = address_space_translate(&address_space_memory, |
| 3290 | phys_addr, &phys_addr, &l, false); |
Wen Congyang | 76f3553 | 2012-05-07 12:04:18 +0800 | [diff] [blame] | 3291 | |
Paolo Bonzini | 5c8a00c | 2013-05-29 12:42:00 +0200 | [diff] [blame] | 3292 | return !(memory_region_is_ram(mr) || |
| 3293 | memory_region_is_romd(mr)); |
Wen Congyang | 76f3553 | 2012-05-07 12:04:18 +0800 | [diff] [blame] | 3294 | } |
Michael R. Hines | bd2fa51 | 2013-06-25 21:35:34 -0400 | [diff] [blame] | 3295 | |
| 3296 | void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
| 3297 | { |
| 3298 | RAMBlock *block; |
| 3299 | |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 3300 | rcu_read_lock(); |
| 3301 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
Michael S. Tsirkin | 9b8424d | 2014-12-15 22:55:32 +0200 | [diff] [blame] | 3302 | func(block->host, block->offset, block->used_length, opaque); |
Michael R. Hines | bd2fa51 | 2013-06-25 21:35:34 -0400 | [diff] [blame] | 3303 | } |
Mike Day | 0dc3f44 | 2013-09-05 14:41:35 -0400 | [diff] [blame] | 3304 | rcu_read_unlock(); |
Michael R. Hines | bd2fa51 | 2013-06-25 21:35:34 -0400 | [diff] [blame] | 3305 | } |
Peter Maydell | ec3f8c9 | 2013-06-27 20:53:38 +0100 | [diff] [blame] | 3306 | #endif |