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bellard7d132992003-03-06 23:23:54 +00001/*
陳韋任e965fc32012-02-06 14:02:55 +08002 * emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
Blue Swirlcea5f9a2011-05-15 16:03:25 +000020#include "cpu.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +020021#include "disas/disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/atomic.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010024#include "sysemu/qtest.h"
bellard7d132992003-03-06 23:23:54 +000025
Andreas Färber5638d182013-08-27 17:52:12 +020026void cpu_loop_exit(CPUState *cpu)
bellarde4533c72003-06-15 19:51:39 +000027{
Andreas Färberd77953b2013-01-16 19:29:31 +010028 cpu->current_tb = NULL;
Andreas Färber6f03bef2013-08-26 06:22:03 +020029 siglongjmp(cpu->jmp_env, 1);
bellarde4533c72003-06-15 19:51:39 +000030}
thsbfed01f2007-06-03 17:44:37 +000031
bellardfbf9eeb2004-04-25 21:21:33 +000032/* exit the current TB from a signal handler. The host registers are
33 restored in a state compatible with the CPU emulator
34 */
Blue Swirl9eff14f2011-05-21 08:42:35 +000035#if defined(CONFIG_SOFTMMU)
Andreas Färber9349b4f2012-03-14 01:38:32 +010036void cpu_resume_from_signal(CPUArchState *env, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000037{
Andreas Färber6f03bef2013-08-26 06:22:03 +020038 CPUState *cpu = ENV_GET_CPU(env);
39
Blue Swirl9eff14f2011-05-21 08:42:35 +000040 /* XXX: restore cpu registers saved in host registers */
41
Andreas Färber27103422013-08-26 08:31:06 +020042 cpu->exception_index = -1;
Andreas Färber6f03bef2013-08-26 06:22:03 +020043 siglongjmp(cpu->jmp_env, 1);
Blue Swirl9eff14f2011-05-21 08:42:35 +000044}
Blue Swirl9eff14f2011-05-21 08:42:35 +000045#endif
bellardfbf9eeb2004-04-25 21:21:33 +000046
Peter Maydell77211372013-02-22 18:10:02 +000047/* Execute a TB, and fix up the CPU state afterwards if necessary */
48static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
49{
50 CPUArchState *env = cpu->env_ptr;
Richard Henderson03afa5f2013-11-06 17:29:39 +100051 uintptr_t next_tb;
52
53#if defined(DEBUG_DISAS)
54 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
55#if defined(TARGET_I386)
56 log_cpu_state(cpu, CPU_DUMP_CCOP);
57#elif defined(TARGET_M68K)
58 /* ??? Should not modify env state for dumping. */
59 cpu_m68k_flush_flags(env, env->cc_op);
60 env->cc_op = CC_OP_FLAGS;
61 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
62 log_cpu_state(cpu, 0);
63#else
64 log_cpu_state(cpu, 0);
65#endif
66 }
67#endif /* DEBUG_DISAS */
68
69 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
Peter Maydell77211372013-02-22 18:10:02 +000070 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
71 /* We didn't start executing this TB (eg because the instruction
72 * counter hit zero); we must restore the guest PC to the address
73 * of the start of the TB.
74 */
Andreas Färberbdf7ae52013-06-28 19:31:32 +020075 CPUClass *cc = CPU_GET_CLASS(cpu);
Peter Maydell77211372013-02-22 18:10:02 +000076 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
Andreas Färberbdf7ae52013-06-28 19:31:32 +020077 if (cc->synchronize_from_tb) {
78 cc->synchronize_from_tb(cpu, tb);
79 } else {
80 assert(cc->set_pc);
81 cc->set_pc(cpu, tb->pc);
82 }
Peter Maydell77211372013-02-22 18:10:02 +000083 }
Peter Maydell378df4b2013-02-22 18:10:03 +000084 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
85 /* We were asked to stop executing TBs (probably a pending
86 * interrupt. We've now stopped, so clear the flag.
87 */
88 cpu->tcg_exit_req = 0;
89 }
Peter Maydell77211372013-02-22 18:10:02 +000090 return next_tb;
91}
92
pbrook2e70f6e2008-06-29 01:03:05 +000093/* Execute the code without caching the generated code. An interpreter
94 could be used if available. */
Andreas Färber9349b4f2012-03-14 01:38:32 +010095static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000096 TranslationBlock *orig_tb)
pbrook2e70f6e2008-06-29 01:03:05 +000097{
Andreas Färberd77953b2013-01-16 19:29:31 +010098 CPUState *cpu = ENV_GET_CPU(env);
pbrook2e70f6e2008-06-29 01:03:05 +000099 TranslationBlock *tb;
100
101 /* Should never happen.
102 We only end up here when an existing TB is too long. */
103 if (max_cycles > CF_COUNT_MASK)
104 max_cycles = CF_COUNT_MASK;
105
Andreas Färber648f0342013-09-01 17:43:17 +0200106 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
pbrook2e70f6e2008-06-29 01:03:05 +0000107 max_cycles);
Andreas Färberd77953b2013-01-16 19:29:31 +0100108 cpu->current_tb = tb;
pbrook2e70f6e2008-06-29 01:03:05 +0000109 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000110 cpu_tb_exec(cpu, tb->tc_ptr);
Andreas Färberd77953b2013-01-16 19:29:31 +0100111 cpu->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000112 tb_phys_invalidate(tb, -1);
113 tb_free(tb);
114}
115
Andreas Färber9349b4f2012-03-14 01:38:32 +0100116static TranslationBlock *tb_find_slow(CPUArchState *env,
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000117 target_ulong pc,
bellard8a40a182005-11-20 10:35:40 +0000118 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +0000119 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +0000120{
Andreas Färber8cd70432013-08-26 06:03:38 +0200121 CPUState *cpu = ENV_GET_CPU(env);
bellard8a40a182005-11-20 10:35:40 +0000122 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +0000123 unsigned int h;
Blue Swirl337fc752011-09-04 11:06:22 +0000124 tb_page_addr_t phys_pc, phys_page1;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000125 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +0000126
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700127 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +0000128
bellard8a40a182005-11-20 10:35:40 +0000129 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000130 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +0000131 phys_page1 = phys_pc & TARGET_PAGE_MASK;
bellard8a40a182005-11-20 10:35:40 +0000132 h = tb_phys_hash_func(phys_pc);
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700133 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
bellard8a40a182005-11-20 10:35:40 +0000134 for(;;) {
135 tb = *ptb1;
136 if (!tb)
137 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000138 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000139 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000140 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000141 tb->flags == flags) {
142 /* check next page if needed */
143 if (tb->page_addr[1] != -1) {
Blue Swirl337fc752011-09-04 11:06:22 +0000144 tb_page_addr_t phys_page2;
145
ths5fafdf22007-09-16 21:08:06 +0000146 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000147 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000148 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000149 if (tb->page_addr[1] == phys_page2)
150 goto found;
151 } else {
152 goto found;
153 }
154 }
155 ptb1 = &tb->phys_hash_next;
156 }
157 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000158 /* if no translated code available, then translate it now */
Andreas Färber648f0342013-09-01 17:43:17 +0200159 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000160
bellard8a40a182005-11-20 10:35:40 +0000161 found:
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300162 /* Move the last found TB to the head of the list */
163 if (likely(*ptb1)) {
164 *ptb1 = tb->phys_hash_next;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700165 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
166 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300167 }
bellard8a40a182005-11-20 10:35:40 +0000168 /* we add the TB in the virtual pc hash table */
Andreas Färber8cd70432013-08-26 06:03:38 +0200169 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000170 return tb;
171}
172
Andreas Färber9349b4f2012-03-14 01:38:32 +0100173static inline TranslationBlock *tb_find_fast(CPUArchState *env)
bellard8a40a182005-11-20 10:35:40 +0000174{
Andreas Färber8cd70432013-08-26 06:03:38 +0200175 CPUState *cpu = ENV_GET_CPU(env);
bellard8a40a182005-11-20 10:35:40 +0000176 TranslationBlock *tb;
177 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000178 int flags;
bellard8a40a182005-11-20 10:35:40 +0000179
180 /* we record a subset of the CPU state. It will
181 always be the same before a given translated block
182 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000183 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
Andreas Färber8cd70432013-08-26 06:03:38 +0200184 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000185 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
186 tb->flags != flags)) {
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000187 tb = tb_find_slow(env, pc, cs_base, flags);
bellard8a40a182005-11-20 10:35:40 +0000188 }
189 return tb;
190}
191
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100192static CPUDebugExcpHandler *debug_excp_handler;
193
Igor Mammedov84e3b602012-06-21 18:29:38 +0200194void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100195{
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100196 debug_excp_handler = handler;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100197}
198
Andreas Färber9349b4f2012-03-14 01:38:32 +0100199static void cpu_handle_debug_exception(CPUArchState *env)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100200{
Andreas Färberff4700b2013-08-26 18:23:18 +0200201 CPUState *cpu = ENV_GET_CPU(env);
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100202 CPUWatchpoint *wp;
203
Andreas Färberff4700b2013-08-26 18:23:18 +0200204 if (!cpu->watchpoint_hit) {
205 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100206 wp->flags &= ~BP_WATCHPOINT_HIT;
207 }
208 }
209 if (debug_excp_handler) {
210 debug_excp_handler(env);
211 }
212}
213
bellard7d132992003-03-06 23:23:54 +0000214/* main execution loop */
215
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300216volatile sig_atomic_t exit_request;
217
Andreas Färber9349b4f2012-03-14 01:38:32 +0100218int cpu_exec(CPUArchState *env)
bellard7d132992003-03-06 23:23:54 +0000219{
Andreas Färberc356a1b2012-05-04 19:39:23 +0200220 CPUState *cpu = ENV_GET_CPU(env);
Andreas Färber97a8ea52013-02-02 10:57:51 +0100221#if !(defined(CONFIG_USER_ONLY) && \
222 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
223 CPUClass *cc = CPU_GET_CLASS(cpu);
224#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100225#ifdef TARGET_I386
226 X86CPU *x86_cpu = X86_CPU(cpu);
227#endif
bellard8a40a182005-11-20 10:35:40 +0000228 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000229 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000230 uint8_t *tc_ptr;
Richard Henderson3e9bd632013-08-20 14:40:25 -0700231 uintptr_t next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000232
Andreas Färber259186a2013-01-17 18:51:17 +0100233 if (cpu->halted) {
Andreas Färber3993c6b2012-05-03 06:43:49 +0200234 if (!cpu_has_work(cpu)) {
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100235 return EXCP_HALTED;
236 }
237
Andreas Färber259186a2013-01-17 18:51:17 +0100238 cpu->halted = 0;
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100239 }
bellard5a1e3cf2005-11-23 21:02:53 +0000240
Andreas Färber4917cf42013-05-27 05:17:50 +0200241 current_cpu = cpu;
bellarde4533c72003-06-15 19:51:39 +0000242
Andreas Färber4917cf42013-05-27 05:17:50 +0200243 /* As long as current_cpu is null, up to the assignment just above,
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200244 * requests by other threads to exit the execution loop are expected to
245 * be issued using the exit_request global. We must make sure that our
Andreas Färber4917cf42013-05-27 05:17:50 +0200246 * evaluation of the global value is performed past the current_cpu
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200247 * value transition point, which requires a memory barrier as well as
248 * an instruction scheduling constraint on modern architectures. */
249 smp_mb();
250
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200251 if (unlikely(exit_request)) {
Andreas Färberfcd7d002012-12-17 08:02:44 +0100252 cpu->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300253 }
254
thsecb644f2007-06-03 18:45:53 +0000255#if defined(TARGET_I386)
Jan Kiszka6792a572011-02-07 12:19:18 +0100256 /* put eflags in CPU temporary format */
257 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
liguang80cf2c82013-05-28 16:21:08 +0800258 env->df = 1 - (2 * ((env->eflags >> 10) & 1));
Jan Kiszka6792a572011-02-07 12:19:18 +0100259 CC_OP = CC_OP_EFLAGS;
260 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000261#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000262#elif defined(TARGET_M68K)
263 env->cc_op = CC_OP_FLAGS;
264 env->cc_dest = env->sr & 0xf;
265 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000266#elif defined(TARGET_ALPHA)
267#elif defined(TARGET_ARM)
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800268#elif defined(TARGET_UNICORE32)
thsecb644f2007-06-03 18:45:53 +0000269#elif defined(TARGET_PPC)
Elie Richa4e85f822011-07-22 05:58:39 +0000270 env->reserve_addr = -1;
Michael Walle81ea0e12011-02-17 23:45:02 +0100271#elif defined(TARGET_LM32)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200272#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000273#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400274#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800275#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000276#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000277#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100278#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400279#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000280 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000281#else
282#error unsupported target CPU
283#endif
Andreas Färber27103422013-08-26 08:31:06 +0200284 cpu->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000285
bellard7d132992003-03-06 23:23:54 +0000286 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000287 for(;;) {
Andreas Färber6f03bef2013-08-26 06:22:03 +0200288 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
bellard3fb2ded2003-06-24 13:22:59 +0000289 /* if an exception is pending, we execute it here */
Andreas Färber27103422013-08-26 08:31:06 +0200290 if (cpu->exception_index >= 0) {
291 if (cpu->exception_index >= EXCP_INTERRUPT) {
bellard3fb2ded2003-06-24 13:22:59 +0000292 /* exit request from the cpu execution loop */
Andreas Färber27103422013-08-26 08:31:06 +0200293 ret = cpu->exception_index;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100294 if (ret == EXCP_DEBUG) {
295 cpu_handle_debug_exception(env);
296 }
bellard3fb2ded2003-06-24 13:22:59 +0000297 break;
aurel3272d239e2009-01-14 19:40:27 +0000298 } else {
299#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000300 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000301 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000302 loop */
bellard83479e72003-06-25 16:12:37 +0000303#if defined(TARGET_I386)
Andreas Färber97a8ea52013-02-02 10:57:51 +0100304 cc->do_interrupt(cpu);
bellard83479e72003-06-25 16:12:37 +0000305#endif
Andreas Färber27103422013-08-26 08:31:06 +0200306 ret = cpu->exception_index;
bellard3fb2ded2003-06-24 13:22:59 +0000307 break;
aurel3272d239e2009-01-14 19:40:27 +0000308#else
Andreas Färber97a8ea52013-02-02 10:57:51 +0100309 cc->do_interrupt(cpu);
Andreas Färber27103422013-08-26 08:31:06 +0200310 cpu->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000311#endif
bellard3fb2ded2003-06-24 13:22:59 +0000312 }
ths5fafdf22007-09-16 21:08:06 +0000313 }
bellard9df217a2005-02-10 22:05:51 +0000314
blueswir1b5fc09a2008-05-04 06:38:18 +0000315 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000316 for(;;) {
Andreas Färber259186a2013-01-17 18:51:17 +0100317 interrupt_request = cpu->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000318 if (unlikely(interrupt_request)) {
Andreas Färbered2803d2013-06-21 20:20:45 +0200319 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
malce1638bd2008-11-06 18:54:46 +0000320 /* Mask out external interrupts for this step. */
Richard Henderson3125f762011-05-04 13:34:25 -0700321 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
malce1638bd2008-11-06 18:54:46 +0000322 }
pbrook6658ffb2007-03-16 23:58:11 +0000323 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
Andreas Färber259186a2013-01-17 18:51:17 +0100324 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
Andreas Färber27103422013-08-26 08:31:06 +0200325 cpu->exception_index = EXCP_DEBUG;
Andreas Färber5638d182013-08-27 17:52:12 +0200326 cpu_loop_exit(cpu);
pbrook6658ffb2007-03-16 23:58:11 +0000327 }
balroga90b7312007-05-01 01:28:01 +0000328#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200329 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800330 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
balroga90b7312007-05-01 01:28:01 +0000331 if (interrupt_request & CPU_INTERRUPT_HALT) {
Andreas Färber259186a2013-01-17 18:51:17 +0100332 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
333 cpu->halted = 1;
Andreas Färber27103422013-08-26 08:31:06 +0200334 cpu->exception_index = EXCP_HLT;
Andreas Färber5638d182013-08-27 17:52:12 +0200335 cpu_loop_exit(cpu);
balroga90b7312007-05-01 01:28:01 +0000336 }
337#endif
bellard68a79312003-06-30 13:12:32 +0000338#if defined(TARGET_I386)
Jan Kiszka5d62c432012-07-09 16:42:32 +0200339#if !defined(CONFIG_USER_ONLY)
340 if (interrupt_request & CPU_INTERRUPT_POLL) {
Andreas Färber259186a2013-01-17 18:51:17 +0100341 cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
Andreas Färber693fa552013-12-24 03:18:12 +0100342 apic_poll_irq(x86_cpu->apic_state);
Jan Kiszka5d62c432012-07-09 16:42:32 +0200343 }
344#endif
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300345 if (interrupt_request & CPU_INTERRUPT_INIT) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000346 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
347 0);
Andreas Färber693fa552013-12-24 03:18:12 +0100348 do_cpu_init(x86_cpu);
Andreas Färber27103422013-08-26 08:31:06 +0200349 cpu->exception_index = EXCP_HALTED;
Andreas Färber5638d182013-08-27 17:52:12 +0200350 cpu_loop_exit(cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300351 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
Andreas Färber693fa552013-12-24 03:18:12 +0100352 do_cpu_sipi(x86_cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300353 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000354 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
355 !(env->hflags & HF_SMM_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000356 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
357 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100358 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
Andreas Färber693fa552013-12-24 03:18:12 +0100359 do_smm_enter(x86_cpu);
bellarddb620f42008-06-04 17:02:19 +0000360 next_tb = 0;
361 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
362 !(env->hflags2 & HF2_NMI_MASK)) {
Andreas Färber259186a2013-01-17 18:51:17 +0100363 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
bellarddb620f42008-06-04 17:02:19 +0000364 env->hflags2 |= HF2_NMI_MASK;
Blue Swirle694d4e2011-05-16 19:38:48 +0000365 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
bellarddb620f42008-06-04 17:02:19 +0000366 next_tb = 0;
陳韋任e965fc32012-02-06 14:02:55 +0800367 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
Andreas Färber259186a2013-01-17 18:51:17 +0100368 cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
Blue Swirle694d4e2011-05-16 19:38:48 +0000369 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
Huang Ying79c4f6b2009-06-23 10:05:14 +0800370 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000371 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
372 (((env->hflags2 & HF2_VINTR_MASK) &&
373 (env->hflags2 & HF2_HIF_MASK)) ||
374 (!(env->hflags2 & HF2_VINTR_MASK) &&
375 (env->eflags & IF_MASK &&
376 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
377 int intno;
Blue Swirl77b2bc22012-04-28 19:35:10 +0000378 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
379 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100380 cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
381 CPU_INTERRUPT_VIRQ);
bellarddb620f42008-06-04 17:02:19 +0000382 intno = cpu_get_pic_interrupt(env);
malc4f213872012-08-27 18:33:12 +0400383 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
384 do_interrupt_x86_hardirq(env, intno, 1);
385 /* ensure that no TB jump will be modified as
386 the program flow was changed */
387 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000388#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000389 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
390 (env->eflags & IF_MASK) &&
391 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
392 int intno;
393 /* FIXME: this should respect TPR */
Blue Swirl77b2bc22012-04-28 19:35:10 +0000394 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
395 0);
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100396 intno = ldl_phys(cpu->as,
397 env->vm_vmcb
398 + offsetof(struct vmcb,
399 control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000400 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000401 do_interrupt_x86_hardirq(env, intno, 1);
Andreas Färber259186a2013-01-17 18:51:17 +0100402 cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000403 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000404#endif
bellarddb620f42008-06-04 17:02:19 +0000405 }
bellard68a79312003-06-30 13:12:32 +0000406 }
bellardce097762004-01-04 23:53:18 +0000407#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000408 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Andreas Färberc356a1b2012-05-04 19:39:23 +0200409 cpu_reset(cpu);
bellard9fddaa02004-05-21 12:59:32 +0000410 }
j_mayer47103572007-03-30 09:38:04 +0000411 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000412 ppc_hw_interrupt(env);
Andreas Färber259186a2013-01-17 18:51:17 +0100413 if (env->pending_interrupts == 0) {
414 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
415 }
blueswir1b5fc09a2008-05-04 06:38:18 +0000416 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000417 }
Michael Walle81ea0e12011-02-17 23:45:02 +0100418#elif defined(TARGET_LM32)
419 if ((interrupt_request & CPU_INTERRUPT_HARD)
420 && (env->ie & IE_IE)) {
Andreas Färber27103422013-08-26 08:31:06 +0200421 cpu->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100422 cc->do_interrupt(cpu);
Michael Walle81ea0e12011-02-17 23:45:02 +0100423 next_tb = 0;
424 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200425#elif defined(TARGET_MICROBLAZE)
426 if ((interrupt_request & CPU_INTERRUPT_HARD)
427 && (env->sregs[SR_MSR] & MSR_IE)
428 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
429 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
Andreas Färber27103422013-08-26 08:31:06 +0200430 cpu->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100431 cc->do_interrupt(cpu);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200432 next_tb = 0;
433 }
bellard6af0bf92005-07-02 14:58:51 +0000434#elif defined(TARGET_MIPS)
435 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100436 cpu_mips_hw_interrupts_pending(env)) {
bellard6af0bf92005-07-02 14:58:51 +0000437 /* Raise it */
Andreas Färber27103422013-08-26 08:31:06 +0200438 cpu->exception_index = EXCP_EXT_INTERRUPT;
bellard6af0bf92005-07-02 14:58:51 +0000439 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100440 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000441 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000442 }
Jia Liub6a71ef2012-07-20 15:50:41 +0800443#elif defined(TARGET_OPENRISC)
444 {
445 int idx = -1;
446 if ((interrupt_request & CPU_INTERRUPT_HARD)
447 && (env->sr & SR_IEE)) {
448 idx = EXCP_INT;
449 }
450 if ((interrupt_request & CPU_INTERRUPT_TIMER)
451 && (env->sr & SR_TEE)) {
452 idx = EXCP_TICK;
453 }
454 if (idx >= 0) {
Andreas Färber27103422013-08-26 08:31:06 +0200455 cpu->exception_index = idx;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100456 cc->do_interrupt(cpu);
Jia Liub6a71ef2012-07-20 15:50:41 +0800457 next_tb = 0;
458 }
459 }
bellarde95c8d52004-09-30 22:22:08 +0000460#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300461 if (interrupt_request & CPU_INTERRUPT_HARD) {
462 if (cpu_interrupts_enabled(env) &&
463 env->interrupt_index > 0) {
464 int pil = env->interrupt_index & 0xf;
465 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000466
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300467 if (((type == TT_EXTINT) &&
468 cpu_pil_allowed(env, pil)) ||
469 type != TT_EXTINT) {
Andreas Färber27103422013-08-26 08:31:06 +0200470 cpu->exception_index = env->interrupt_index;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100471 cc->do_interrupt(cpu);
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300472 next_tb = 0;
473 }
474 }
陳韋任e965fc32012-02-06 14:02:55 +0800475 }
bellardb5ff1b32005-11-26 10:38:39 +0000476#elif defined(TARGET_ARM)
477 if (interrupt_request & CPU_INTERRUPT_FIQ
Peter Maydell4cc35612014-02-26 17:20:06 +0000478 && !(env->daif & PSTATE_F)) {
Andreas Färber27103422013-08-26 08:31:06 +0200479 cpu->exception_index = EXCP_FIQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100480 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000481 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000482 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000483 /* ARMv7-M interrupt return works by loading a magic value
484 into the PC. On real hardware the load causes the
485 return to occur. The qemu implementation performs the
486 jump normally, then does the exception return when the
487 CPU tries to execute code at the magic address.
488 This will cause the magic PC value to be pushed to
Stefan Weila1c72732011-04-28 17:20:38 +0200489 the stack if an interrupt occurred at the wrong time.
pbrook9ee6e8b2007-11-11 00:04:49 +0000490 We avoid this by disabling interrupts when
491 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000492 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000493 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
Peter Maydell4cc35612014-02-26 17:20:06 +0000494 || !(env->daif & PSTATE_I))) {
Andreas Färber27103422013-08-26 08:31:06 +0200495 cpu->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100496 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000497 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000498 }
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800499#elif defined(TARGET_UNICORE32)
500 if (interrupt_request & CPU_INTERRUPT_HARD
501 && !(env->uncached_asr & ASR_I)) {
Andreas Färber27103422013-08-26 08:31:06 +0200502 cpu->exception_index = UC32_EXCP_INTR;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100503 cc->do_interrupt(cpu);
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800504 next_tb = 0;
505 }
bellardfdf9b3e2006-04-27 21:07:38 +0000506#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000507 if (interrupt_request & CPU_INTERRUPT_HARD) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100508 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000509 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000510 }
j_mayereddf68a2007-04-05 07:22:49 +0000511#elif defined(TARGET_ALPHA)
Richard Henderson6a80e082011-04-18 15:09:09 -0700512 {
513 int idx = -1;
514 /* ??? This hard-codes the OSF/1 interrupt levels. */
陳韋任e965fc32012-02-06 14:02:55 +0800515 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
Richard Henderson6a80e082011-04-18 15:09:09 -0700516 case 0 ... 3:
517 if (interrupt_request & CPU_INTERRUPT_HARD) {
518 idx = EXCP_DEV_INTERRUPT;
519 }
520 /* FALLTHRU */
521 case 4:
522 if (interrupt_request & CPU_INTERRUPT_TIMER) {
523 idx = EXCP_CLK_INTERRUPT;
524 }
525 /* FALLTHRU */
526 case 5:
527 if (interrupt_request & CPU_INTERRUPT_SMP) {
528 idx = EXCP_SMP_INTERRUPT;
529 }
530 /* FALLTHRU */
531 case 6:
532 if (interrupt_request & CPU_INTERRUPT_MCHK) {
533 idx = EXCP_MCHK;
534 }
535 }
536 if (idx >= 0) {
Andreas Färber27103422013-08-26 08:31:06 +0200537 cpu->exception_index = idx;
Richard Henderson6a80e082011-04-18 15:09:09 -0700538 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100539 cc->do_interrupt(cpu);
Richard Henderson6a80e082011-04-18 15:09:09 -0700540 next_tb = 0;
541 }
j_mayereddf68a2007-04-05 07:22:49 +0000542 }
thsf1ccf902007-10-08 13:16:14 +0000543#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000544 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100545 && (env->pregs[PR_CCS] & I_FLAG)
546 && !env->locked_irq) {
Andreas Färber27103422013-08-26 08:31:06 +0200547 cpu->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100548 cc->do_interrupt(cpu);
edgar_igl1b1a38b2008-06-09 23:18:06 +0000549 next_tb = 0;
550 }
Lars Persson82193142012-06-14 16:23:55 +0200551 if (interrupt_request & CPU_INTERRUPT_NMI) {
552 unsigned int m_flag_archval;
553 if (env->pregs[PR_VR] < 32) {
554 m_flag_archval = M_FLAG_V10;
555 } else {
556 m_flag_archval = M_FLAG_V32;
557 }
558 if ((env->pregs[PR_CCS] & m_flag_archval)) {
Andreas Färber27103422013-08-26 08:31:06 +0200559 cpu->exception_index = EXCP_NMI;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100560 cc->do_interrupt(cpu);
Lars Persson82193142012-06-14 16:23:55 +0200561 next_tb = 0;
562 }
thsf1ccf902007-10-08 13:16:14 +0000563 }
pbrook06338792007-05-23 19:58:11 +0000564#elif defined(TARGET_M68K)
565 if (interrupt_request & CPU_INTERRUPT_HARD
566 && ((env->sr & SR_I) >> SR_I_SHIFT)
567 < env->pending_level) {
568 /* Real hardware gets the interrupt vector via an
569 IACK cycle at this point. Current emulated
570 hardware doesn't rely on this, so we
571 provide/save the vector when the interrupt is
572 first signalled. */
Andreas Färber27103422013-08-26 08:31:06 +0200573 cpu->exception_index = env->pending_vector;
Blue Swirl3c688822011-05-21 07:55:24 +0000574 do_interrupt_m68k_hardirq(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000575 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000576 }
Alexander Graf3110e292011-04-15 17:32:48 +0200577#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
578 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
579 (env->psw.mask & PSW_MASK_EXT)) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100580 cc->do_interrupt(cpu);
Alexander Graf3110e292011-04-15 17:32:48 +0200581 next_tb = 0;
582 }
Max Filippov40643d72011-09-06 03:55:41 +0400583#elif defined(TARGET_XTENSA)
584 if (interrupt_request & CPU_INTERRUPT_HARD) {
Andreas Färber27103422013-08-26 08:31:06 +0200585 cpu->exception_index = EXC_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100586 cc->do_interrupt(cpu);
Max Filippov40643d72011-09-06 03:55:41 +0400587 next_tb = 0;
588 }
bellard68a79312003-06-30 13:12:32 +0000589#endif
Stefan Weilff2712b2011-04-28 17:20:35 +0200590 /* Don't use the cached interrupt_request value,
bellard9d050952006-05-22 22:03:52 +0000591 do_interrupt may have updated the EXITTB flag. */
Andreas Färber259186a2013-01-17 18:51:17 +0100592 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
593 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bellardbf3e8bf2004-02-16 21:58:54 +0000594 /* ensure that no TB jump will be modified as
595 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000596 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000597 }
aurel32be214e62009-03-06 21:48:00 +0000598 }
Andreas Färberfcd7d002012-12-17 08:02:44 +0100599 if (unlikely(cpu->exit_request)) {
600 cpu->exit_request = 0;
Andreas Färber27103422013-08-26 08:31:06 +0200601 cpu->exception_index = EXCP_INTERRUPT;
Andreas Färber5638d182013-08-27 17:52:12 +0200602 cpu_loop_exit(cpu);
bellard3fb2ded2003-06-24 13:22:59 +0000603 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700604 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000605 tb = tb_find_fast(env);
pbrookd5975362008-06-07 20:50:51 +0000606 /* Note: we do it here to avoid a gcc bug on Mac OS X when
607 doing it in tb_find_slow */
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700608 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
pbrookd5975362008-06-07 20:50:51 +0000609 /* as some TB could have been invalidated because
610 of memory exceptions while generating the code, we
611 must recompute the hash index here */
612 next_tb = 0;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700613 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000614 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100615 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
616 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
617 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
618 }
bellard8a40a182005-11-20 10:35:40 +0000619 /* see if we can patch the calling TB. When the TB
620 spans two pages, we cannot safely do a direct
621 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100622 if (next_tb != 0 && tb->page_addr[1] == -1) {
Peter Maydell09800112013-02-22 18:10:00 +0000623 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
624 next_tb & TB_EXIT_MASK, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000625 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700626 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
malc55e8b852008-11-04 14:18:13 +0000627
628 /* cpu_interrupt might be called while translating the
629 TB, but before it is linked into a potentially
630 infinite loop and becomes env->current_tb. Avoid
631 starting execution if there is a pending interrupt. */
Andreas Färberd77953b2013-01-16 19:29:31 +0100632 cpu->current_tb = tb;
Jan Kiszkab0052d12010-06-25 16:56:50 +0200633 barrier();
Andreas Färberfcd7d002012-12-17 08:02:44 +0100634 if (likely(!cpu->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000635 tc_ptr = tb->tc_ptr;
陳韋任e965fc32012-02-06 14:02:55 +0800636 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000637 next_tb = cpu_tb_exec(cpu, tc_ptr);
Peter Maydell378df4b2013-02-22 18:10:03 +0000638 switch (next_tb & TB_EXIT_MASK) {
639 case TB_EXIT_REQUESTED:
640 /* Something asked us to stop executing
641 * chained TBs; just continue round the main
642 * loop. Whatever requested the exit will also
643 * have set something else (eg exit_request or
644 * interrupt_request) which we will handle
645 * next time around the loop.
646 */
647 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
648 next_tb = 0;
649 break;
650 case TB_EXIT_ICOUNT_EXPIRED:
651 {
thsbf20dc02008-06-30 17:22:19 +0000652 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000653 int insns_left;
Peter Maydell09800112013-02-22 18:10:00 +0000654 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
Andreas Färber28ecfd72013-08-26 05:51:49 +0200655 insns_left = cpu->icount_decr.u32;
Andreas Färberefee7342013-08-26 05:39:29 +0200656 if (cpu->icount_extra && insns_left >= 0) {
pbrook2e70f6e2008-06-29 01:03:05 +0000657 /* Refill decrementer and continue execution. */
Andreas Färberefee7342013-08-26 05:39:29 +0200658 cpu->icount_extra += insns_left;
659 if (cpu->icount_extra > 0xffff) {
pbrook2e70f6e2008-06-29 01:03:05 +0000660 insns_left = 0xffff;
661 } else {
Andreas Färberefee7342013-08-26 05:39:29 +0200662 insns_left = cpu->icount_extra;
pbrook2e70f6e2008-06-29 01:03:05 +0000663 }
Andreas Färberefee7342013-08-26 05:39:29 +0200664 cpu->icount_extra -= insns_left;
Andreas Färber28ecfd72013-08-26 05:51:49 +0200665 cpu->icount_decr.u16.low = insns_left;
pbrook2e70f6e2008-06-29 01:03:05 +0000666 } else {
667 if (insns_left > 0) {
668 /* Execute remaining instructions. */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000669 cpu_exec_nocache(env, insns_left, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000670 }
Andreas Färber27103422013-08-26 08:31:06 +0200671 cpu->exception_index = EXCP_INTERRUPT;
pbrook2e70f6e2008-06-29 01:03:05 +0000672 next_tb = 0;
Andreas Färber5638d182013-08-27 17:52:12 +0200673 cpu_loop_exit(cpu);
pbrook2e70f6e2008-06-29 01:03:05 +0000674 }
Peter Maydell378df4b2013-02-22 18:10:03 +0000675 break;
676 }
677 default:
678 break;
pbrook2e70f6e2008-06-29 01:03:05 +0000679 }
680 }
Andreas Färberd77953b2013-01-16 19:29:31 +0100681 cpu->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000682 /* reset soft MMU for next block (it can currently
683 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000684 } /* for(;;) */
Jan Kiszka0d101932011-07-02 09:50:51 +0200685 } else {
686 /* Reload env after longjmp - the compiler may have smashed all
687 * local variables as longjmp is marked 'noreturn'. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200688 cpu = current_cpu;
689 env = cpu->env_ptr;
Juergen Lock6c78f292013-10-03 16:09:37 +0200690#if !(defined(CONFIG_USER_ONLY) && \
691 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
692 cc = CPU_GET_CLASS(cpu);
693#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100694#ifdef TARGET_I386
695 x86_cpu = X86_CPU(cpu);
696#endif
bellard7d132992003-03-06 23:23:54 +0000697 }
bellard3fb2ded2003-06-24 13:22:59 +0000698 } /* for(;;) */
699
bellard7d132992003-03-06 23:23:54 +0000700
bellarde4533c72003-06-15 19:51:39 +0000701#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000702 /* restore flags in standard format */
Blue Swirle694d4e2011-05-16 19:38:48 +0000703 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
liguang80cf2c82013-05-28 16:21:08 +0800704 | (env->df & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000705#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000706 /* XXX: Save/restore host fpu exception state?. */
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800707#elif defined(TARGET_UNICORE32)
bellard93ac68b2003-09-30 20:57:29 +0000708#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000709#elif defined(TARGET_PPC)
Michael Walle81ea0e12011-02-17 23:45:02 +0100710#elif defined(TARGET_LM32)
pbrooke6e59062006-10-22 00:18:54 +0000711#elif defined(TARGET_M68K)
712 cpu_m68k_flush_flags(env, env->cc_op);
713 env->cc_op = CC_OP_FLAGS;
714 env->sr = (env->sr & 0xffe0)
715 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200716#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000717#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400718#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800719#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000720#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000721#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000722#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100723#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400724#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000725 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000726#else
727#error unsupported target CPU
728#endif
pbrook1057eaa2007-02-04 13:37:44 +0000729
Andreas Färber4917cf42013-05-27 05:17:50 +0200730 /* fail safe : never use current_cpu outside cpu_exec() */
731 current_cpu = NULL;
bellard7d132992003-03-06 23:23:54 +0000732 return ret;
733}