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bellard7d132992003-03-06 23:23:54 +00001/*
陳韋任e965fc32012-02-06 14:02:55 +08002 * emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
Blue Swirlcea5f9a2011-05-15 16:03:25 +000020#include "cpu.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +020021#include "disas/disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/atomic.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010024#include "sysemu/qtest.h"
bellard7d132992003-03-06 23:23:54 +000025
Andreas Färber9349b4f2012-03-14 01:38:32 +010026void cpu_loop_exit(CPUArchState *env)
bellarde4533c72003-06-15 19:51:39 +000027{
Andreas Färberd77953b2013-01-16 19:29:31 +010028 CPUState *cpu = ENV_GET_CPU(env);
29
30 cpu->current_tb = NULL;
Peter Maydell6ab7e542013-02-20 15:21:09 +000031 siglongjmp(env->jmp_env, 1);
bellarde4533c72003-06-15 19:51:39 +000032}
thsbfed01f2007-06-03 17:44:37 +000033
bellardfbf9eeb2004-04-25 21:21:33 +000034/* exit the current TB from a signal handler. The host registers are
35 restored in a state compatible with the CPU emulator
36 */
Blue Swirl9eff14f2011-05-21 08:42:35 +000037#if defined(CONFIG_SOFTMMU)
Andreas Färber9349b4f2012-03-14 01:38:32 +010038void cpu_resume_from_signal(CPUArchState *env, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000039{
Blue Swirl9eff14f2011-05-21 08:42:35 +000040 /* XXX: restore cpu registers saved in host registers */
41
42 env->exception_index = -1;
Peter Maydell6ab7e542013-02-20 15:21:09 +000043 siglongjmp(env->jmp_env, 1);
Blue Swirl9eff14f2011-05-21 08:42:35 +000044}
Blue Swirl9eff14f2011-05-21 08:42:35 +000045#endif
bellardfbf9eeb2004-04-25 21:21:33 +000046
Peter Maydell77211372013-02-22 18:10:02 +000047/* Execute a TB, and fix up the CPU state afterwards if necessary */
48static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
49{
50 CPUArchState *env = cpu->env_ptr;
Richard Henderson03afa5f2013-11-06 17:29:39 +100051 uintptr_t next_tb;
52
53#if defined(DEBUG_DISAS)
54 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
55#if defined(TARGET_I386)
56 log_cpu_state(cpu, CPU_DUMP_CCOP);
57#elif defined(TARGET_M68K)
58 /* ??? Should not modify env state for dumping. */
59 cpu_m68k_flush_flags(env, env->cc_op);
60 env->cc_op = CC_OP_FLAGS;
61 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
62 log_cpu_state(cpu, 0);
63#else
64 log_cpu_state(cpu, 0);
65#endif
66 }
67#endif /* DEBUG_DISAS */
68
69 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
Peter Maydell77211372013-02-22 18:10:02 +000070 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
71 /* We didn't start executing this TB (eg because the instruction
72 * counter hit zero); we must restore the guest PC to the address
73 * of the start of the TB.
74 */
Andreas Färberbdf7ae52013-06-28 19:31:32 +020075 CPUClass *cc = CPU_GET_CLASS(cpu);
Peter Maydell77211372013-02-22 18:10:02 +000076 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
Andreas Färberbdf7ae52013-06-28 19:31:32 +020077 if (cc->synchronize_from_tb) {
78 cc->synchronize_from_tb(cpu, tb);
79 } else {
80 assert(cc->set_pc);
81 cc->set_pc(cpu, tb->pc);
82 }
Peter Maydell77211372013-02-22 18:10:02 +000083 }
Peter Maydell378df4b2013-02-22 18:10:03 +000084 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
85 /* We were asked to stop executing TBs (probably a pending
86 * interrupt. We've now stopped, so clear the flag.
87 */
88 cpu->tcg_exit_req = 0;
89 }
Peter Maydell77211372013-02-22 18:10:02 +000090 return next_tb;
91}
92
pbrook2e70f6e2008-06-29 01:03:05 +000093/* Execute the code without caching the generated code. An interpreter
94 could be used if available. */
Andreas Färber9349b4f2012-03-14 01:38:32 +010095static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000096 TranslationBlock *orig_tb)
pbrook2e70f6e2008-06-29 01:03:05 +000097{
Andreas Färberd77953b2013-01-16 19:29:31 +010098 CPUState *cpu = ENV_GET_CPU(env);
pbrook2e70f6e2008-06-29 01:03:05 +000099 TranslationBlock *tb;
100
101 /* Should never happen.
102 We only end up here when an existing TB is too long. */
103 if (max_cycles > CF_COUNT_MASK)
104 max_cycles = CF_COUNT_MASK;
105
106 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
107 max_cycles);
Andreas Färberd77953b2013-01-16 19:29:31 +0100108 cpu->current_tb = tb;
pbrook2e70f6e2008-06-29 01:03:05 +0000109 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000110 cpu_tb_exec(cpu, tb->tc_ptr);
Andreas Färberd77953b2013-01-16 19:29:31 +0100111 cpu->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000112 tb_phys_invalidate(tb, -1);
113 tb_free(tb);
114}
115
Andreas Färber9349b4f2012-03-14 01:38:32 +0100116static TranslationBlock *tb_find_slow(CPUArchState *env,
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000117 target_ulong pc,
bellard8a40a182005-11-20 10:35:40 +0000118 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +0000119 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +0000120{
Andreas Färber8cd70432013-08-26 06:03:38 +0200121 CPUState *cpu = ENV_GET_CPU(env);
bellard8a40a182005-11-20 10:35:40 +0000122 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +0000123 unsigned int h;
Blue Swirl337fc752011-09-04 11:06:22 +0000124 tb_page_addr_t phys_pc, phys_page1;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000125 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +0000126
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700127 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +0000128
bellard8a40a182005-11-20 10:35:40 +0000129 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000130 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +0000131 phys_page1 = phys_pc & TARGET_PAGE_MASK;
bellard8a40a182005-11-20 10:35:40 +0000132 h = tb_phys_hash_func(phys_pc);
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700133 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
bellard8a40a182005-11-20 10:35:40 +0000134 for(;;) {
135 tb = *ptb1;
136 if (!tb)
137 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000138 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000139 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000140 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000141 tb->flags == flags) {
142 /* check next page if needed */
143 if (tb->page_addr[1] != -1) {
Blue Swirl337fc752011-09-04 11:06:22 +0000144 tb_page_addr_t phys_page2;
145
ths5fafdf22007-09-16 21:08:06 +0000146 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000147 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000148 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000149 if (tb->page_addr[1] == phys_page2)
150 goto found;
151 } else {
152 goto found;
153 }
154 }
155 ptb1 = &tb->phys_hash_next;
156 }
157 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000158 /* if no translated code available, then translate it now */
159 tb = tb_gen_code(env, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000160
bellard8a40a182005-11-20 10:35:40 +0000161 found:
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300162 /* Move the last found TB to the head of the list */
163 if (likely(*ptb1)) {
164 *ptb1 = tb->phys_hash_next;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700165 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
166 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300167 }
bellard8a40a182005-11-20 10:35:40 +0000168 /* we add the TB in the virtual pc hash table */
Andreas Färber8cd70432013-08-26 06:03:38 +0200169 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000170 return tb;
171}
172
Andreas Färber9349b4f2012-03-14 01:38:32 +0100173static inline TranslationBlock *tb_find_fast(CPUArchState *env)
bellard8a40a182005-11-20 10:35:40 +0000174{
Andreas Färber8cd70432013-08-26 06:03:38 +0200175 CPUState *cpu = ENV_GET_CPU(env);
bellard8a40a182005-11-20 10:35:40 +0000176 TranslationBlock *tb;
177 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000178 int flags;
bellard8a40a182005-11-20 10:35:40 +0000179
180 /* we record a subset of the CPU state. It will
181 always be the same before a given translated block
182 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000183 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
Andreas Färber8cd70432013-08-26 06:03:38 +0200184 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000185 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
186 tb->flags != flags)) {
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000187 tb = tb_find_slow(env, pc, cs_base, flags);
bellard8a40a182005-11-20 10:35:40 +0000188 }
189 return tb;
190}
191
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100192static CPUDebugExcpHandler *debug_excp_handler;
193
Igor Mammedov84e3b602012-06-21 18:29:38 +0200194void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100195{
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100196 debug_excp_handler = handler;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100197}
198
Andreas Färber9349b4f2012-03-14 01:38:32 +0100199static void cpu_handle_debug_exception(CPUArchState *env)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100200{
201 CPUWatchpoint *wp;
202
203 if (!env->watchpoint_hit) {
204 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
205 wp->flags &= ~BP_WATCHPOINT_HIT;
206 }
207 }
208 if (debug_excp_handler) {
209 debug_excp_handler(env);
210 }
211}
212
bellard7d132992003-03-06 23:23:54 +0000213/* main execution loop */
214
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300215volatile sig_atomic_t exit_request;
216
Andreas Färber9349b4f2012-03-14 01:38:32 +0100217int cpu_exec(CPUArchState *env)
bellard7d132992003-03-06 23:23:54 +0000218{
Andreas Färberc356a1b2012-05-04 19:39:23 +0200219 CPUState *cpu = ENV_GET_CPU(env);
Andreas Färber97a8ea52013-02-02 10:57:51 +0100220#if !(defined(CONFIG_USER_ONLY) && \
221 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
222 CPUClass *cc = CPU_GET_CLASS(cpu);
223#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100224#ifdef TARGET_I386
225 X86CPU *x86_cpu = X86_CPU(cpu);
226#endif
bellard8a40a182005-11-20 10:35:40 +0000227 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000228 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000229 uint8_t *tc_ptr;
Richard Henderson3e9bd632013-08-20 14:40:25 -0700230 uintptr_t next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000231
Andreas Färber259186a2013-01-17 18:51:17 +0100232 if (cpu->halted) {
Andreas Färber3993c6b2012-05-03 06:43:49 +0200233 if (!cpu_has_work(cpu)) {
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100234 return EXCP_HALTED;
235 }
236
Andreas Färber259186a2013-01-17 18:51:17 +0100237 cpu->halted = 0;
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100238 }
bellard5a1e3cf2005-11-23 21:02:53 +0000239
Andreas Färber4917cf42013-05-27 05:17:50 +0200240 current_cpu = cpu;
bellarde4533c72003-06-15 19:51:39 +0000241
Andreas Färber4917cf42013-05-27 05:17:50 +0200242 /* As long as current_cpu is null, up to the assignment just above,
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200243 * requests by other threads to exit the execution loop are expected to
244 * be issued using the exit_request global. We must make sure that our
Andreas Färber4917cf42013-05-27 05:17:50 +0200245 * evaluation of the global value is performed past the current_cpu
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200246 * value transition point, which requires a memory barrier as well as
247 * an instruction scheduling constraint on modern architectures. */
248 smp_mb();
249
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200250 if (unlikely(exit_request)) {
Andreas Färberfcd7d002012-12-17 08:02:44 +0100251 cpu->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300252 }
253
thsecb644f2007-06-03 18:45:53 +0000254#if defined(TARGET_I386)
Jan Kiszka6792a572011-02-07 12:19:18 +0100255 /* put eflags in CPU temporary format */
256 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
liguang80cf2c82013-05-28 16:21:08 +0800257 env->df = 1 - (2 * ((env->eflags >> 10) & 1));
Jan Kiszka6792a572011-02-07 12:19:18 +0100258 CC_OP = CC_OP_EFLAGS;
259 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000260#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000261#elif defined(TARGET_M68K)
262 env->cc_op = CC_OP_FLAGS;
263 env->cc_dest = env->sr & 0xf;
264 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000265#elif defined(TARGET_ALPHA)
266#elif defined(TARGET_ARM)
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800267#elif defined(TARGET_UNICORE32)
thsecb644f2007-06-03 18:45:53 +0000268#elif defined(TARGET_PPC)
Elie Richa4e85f822011-07-22 05:58:39 +0000269 env->reserve_addr = -1;
Michael Walle81ea0e12011-02-17 23:45:02 +0100270#elif defined(TARGET_LM32)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200271#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000272#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400273#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800274#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000275#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000276#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100277#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400278#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000279 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000280#else
281#error unsupported target CPU
282#endif
bellard3fb2ded2003-06-24 13:22:59 +0000283 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000284
bellard7d132992003-03-06 23:23:54 +0000285 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000286 for(;;) {
Peter Maydell6ab7e542013-02-20 15:21:09 +0000287 if (sigsetjmp(env->jmp_env, 0) == 0) {
bellard3fb2ded2003-06-24 13:22:59 +0000288 /* if an exception is pending, we execute it here */
289 if (env->exception_index >= 0) {
290 if (env->exception_index >= EXCP_INTERRUPT) {
291 /* exit request from the cpu execution loop */
292 ret = env->exception_index;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100293 if (ret == EXCP_DEBUG) {
294 cpu_handle_debug_exception(env);
295 }
bellard3fb2ded2003-06-24 13:22:59 +0000296 break;
aurel3272d239e2009-01-14 19:40:27 +0000297 } else {
298#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000299 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000300 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000301 loop */
bellard83479e72003-06-25 16:12:37 +0000302#if defined(TARGET_I386)
Andreas Färber97a8ea52013-02-02 10:57:51 +0100303 cc->do_interrupt(cpu);
bellard83479e72003-06-25 16:12:37 +0000304#endif
bellard3fb2ded2003-06-24 13:22:59 +0000305 ret = env->exception_index;
306 break;
aurel3272d239e2009-01-14 19:40:27 +0000307#else
Andreas Färber97a8ea52013-02-02 10:57:51 +0100308 cc->do_interrupt(cpu);
Paolo Bonzini301d2902010-01-15 09:41:01 +0100309 env->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000310#endif
bellard3fb2ded2003-06-24 13:22:59 +0000311 }
ths5fafdf22007-09-16 21:08:06 +0000312 }
bellard9df217a2005-02-10 22:05:51 +0000313
blueswir1b5fc09a2008-05-04 06:38:18 +0000314 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000315 for(;;) {
Andreas Färber259186a2013-01-17 18:51:17 +0100316 interrupt_request = cpu->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000317 if (unlikely(interrupt_request)) {
Andreas Färbered2803d2013-06-21 20:20:45 +0200318 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
malce1638bd2008-11-06 18:54:46 +0000319 /* Mask out external interrupts for this step. */
Richard Henderson3125f762011-05-04 13:34:25 -0700320 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
malce1638bd2008-11-06 18:54:46 +0000321 }
pbrook6658ffb2007-03-16 23:58:11 +0000322 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
Andreas Färber259186a2013-01-17 18:51:17 +0100323 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
pbrook6658ffb2007-03-16 23:58:11 +0000324 env->exception_index = EXCP_DEBUG;
Blue Swirl1162c042011-05-14 12:52:35 +0000325 cpu_loop_exit(env);
pbrook6658ffb2007-03-16 23:58:11 +0000326 }
balroga90b7312007-05-01 01:28:01 +0000327#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200328 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800329 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
balroga90b7312007-05-01 01:28:01 +0000330 if (interrupt_request & CPU_INTERRUPT_HALT) {
Andreas Färber259186a2013-01-17 18:51:17 +0100331 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
332 cpu->halted = 1;
balroga90b7312007-05-01 01:28:01 +0000333 env->exception_index = EXCP_HLT;
Blue Swirl1162c042011-05-14 12:52:35 +0000334 cpu_loop_exit(env);
balroga90b7312007-05-01 01:28:01 +0000335 }
336#endif
bellard68a79312003-06-30 13:12:32 +0000337#if defined(TARGET_I386)
Jan Kiszka5d62c432012-07-09 16:42:32 +0200338#if !defined(CONFIG_USER_ONLY)
339 if (interrupt_request & CPU_INTERRUPT_POLL) {
Andreas Färber259186a2013-01-17 18:51:17 +0100340 cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
Andreas Färber693fa552013-12-24 03:18:12 +0100341 apic_poll_irq(x86_cpu->apic_state);
Jan Kiszka5d62c432012-07-09 16:42:32 +0200342 }
343#endif
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300344 if (interrupt_request & CPU_INTERRUPT_INIT) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000345 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
346 0);
Andreas Färber693fa552013-12-24 03:18:12 +0100347 do_cpu_init(x86_cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300348 env->exception_index = EXCP_HALTED;
Blue Swirl1162c042011-05-14 12:52:35 +0000349 cpu_loop_exit(env);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300350 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
Andreas Färber693fa552013-12-24 03:18:12 +0100351 do_cpu_sipi(x86_cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300352 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000353 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
354 !(env->hflags & HF_SMM_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000355 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
356 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100357 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
Andreas Färber693fa552013-12-24 03:18:12 +0100358 do_smm_enter(x86_cpu);
bellarddb620f42008-06-04 17:02:19 +0000359 next_tb = 0;
360 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
361 !(env->hflags2 & HF2_NMI_MASK)) {
Andreas Färber259186a2013-01-17 18:51:17 +0100362 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
bellarddb620f42008-06-04 17:02:19 +0000363 env->hflags2 |= HF2_NMI_MASK;
Blue Swirle694d4e2011-05-16 19:38:48 +0000364 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
bellarddb620f42008-06-04 17:02:19 +0000365 next_tb = 0;
陳韋任e965fc32012-02-06 14:02:55 +0800366 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
Andreas Färber259186a2013-01-17 18:51:17 +0100367 cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
Blue Swirle694d4e2011-05-16 19:38:48 +0000368 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
Huang Ying79c4f6b2009-06-23 10:05:14 +0800369 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000370 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
371 (((env->hflags2 & HF2_VINTR_MASK) &&
372 (env->hflags2 & HF2_HIF_MASK)) ||
373 (!(env->hflags2 & HF2_VINTR_MASK) &&
374 (env->eflags & IF_MASK &&
375 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
376 int intno;
Blue Swirl77b2bc22012-04-28 19:35:10 +0000377 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
378 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100379 cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
380 CPU_INTERRUPT_VIRQ);
bellarddb620f42008-06-04 17:02:19 +0000381 intno = cpu_get_pic_interrupt(env);
malc4f213872012-08-27 18:33:12 +0400382 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
383 do_interrupt_x86_hardirq(env, intno, 1);
384 /* ensure that no TB jump will be modified as
385 the program flow was changed */
386 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000387#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000388 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
389 (env->eflags & IF_MASK) &&
390 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
391 int intno;
392 /* FIXME: this should respect TPR */
Blue Swirl77b2bc22012-04-28 19:35:10 +0000393 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
394 0);
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100395 intno = ldl_phys(cpu->as,
396 env->vm_vmcb
397 + offsetof(struct vmcb,
398 control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000399 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000400 do_interrupt_x86_hardirq(env, intno, 1);
Andreas Färber259186a2013-01-17 18:51:17 +0100401 cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000402 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000403#endif
bellarddb620f42008-06-04 17:02:19 +0000404 }
bellard68a79312003-06-30 13:12:32 +0000405 }
bellardce097762004-01-04 23:53:18 +0000406#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000407 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Andreas Färberc356a1b2012-05-04 19:39:23 +0200408 cpu_reset(cpu);
bellard9fddaa02004-05-21 12:59:32 +0000409 }
j_mayer47103572007-03-30 09:38:04 +0000410 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000411 ppc_hw_interrupt(env);
Andreas Färber259186a2013-01-17 18:51:17 +0100412 if (env->pending_interrupts == 0) {
413 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
414 }
blueswir1b5fc09a2008-05-04 06:38:18 +0000415 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000416 }
Michael Walle81ea0e12011-02-17 23:45:02 +0100417#elif defined(TARGET_LM32)
418 if ((interrupt_request & CPU_INTERRUPT_HARD)
419 && (env->ie & IE_IE)) {
420 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100421 cc->do_interrupt(cpu);
Michael Walle81ea0e12011-02-17 23:45:02 +0100422 next_tb = 0;
423 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200424#elif defined(TARGET_MICROBLAZE)
425 if ((interrupt_request & CPU_INTERRUPT_HARD)
426 && (env->sregs[SR_MSR] & MSR_IE)
427 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
428 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
429 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100430 cc->do_interrupt(cpu);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200431 next_tb = 0;
432 }
bellard6af0bf92005-07-02 14:58:51 +0000433#elif defined(TARGET_MIPS)
434 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100435 cpu_mips_hw_interrupts_pending(env)) {
bellard6af0bf92005-07-02 14:58:51 +0000436 /* Raise it */
437 env->exception_index = EXCP_EXT_INTERRUPT;
438 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100439 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000440 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000441 }
Jia Liub6a71ef2012-07-20 15:50:41 +0800442#elif defined(TARGET_OPENRISC)
443 {
444 int idx = -1;
445 if ((interrupt_request & CPU_INTERRUPT_HARD)
446 && (env->sr & SR_IEE)) {
447 idx = EXCP_INT;
448 }
449 if ((interrupt_request & CPU_INTERRUPT_TIMER)
450 && (env->sr & SR_TEE)) {
451 idx = EXCP_TICK;
452 }
453 if (idx >= 0) {
454 env->exception_index = idx;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100455 cc->do_interrupt(cpu);
Jia Liub6a71ef2012-07-20 15:50:41 +0800456 next_tb = 0;
457 }
458 }
bellarde95c8d52004-09-30 22:22:08 +0000459#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300460 if (interrupt_request & CPU_INTERRUPT_HARD) {
461 if (cpu_interrupts_enabled(env) &&
462 env->interrupt_index > 0) {
463 int pil = env->interrupt_index & 0xf;
464 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000465
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300466 if (((type == TT_EXTINT) &&
467 cpu_pil_allowed(env, pil)) ||
468 type != TT_EXTINT) {
469 env->exception_index = env->interrupt_index;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100470 cc->do_interrupt(cpu);
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300471 next_tb = 0;
472 }
473 }
陳韋任e965fc32012-02-06 14:02:55 +0800474 }
bellardb5ff1b32005-11-26 10:38:39 +0000475#elif defined(TARGET_ARM)
476 if (interrupt_request & CPU_INTERRUPT_FIQ
Peter Maydell4cc35612014-02-26 17:20:06 +0000477 && !(env->daif & PSTATE_F)) {
bellardb5ff1b32005-11-26 10:38:39 +0000478 env->exception_index = EXCP_FIQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100479 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000480 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000481 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000482 /* ARMv7-M interrupt return works by loading a magic value
483 into the PC. On real hardware the load causes the
484 return to occur. The qemu implementation performs the
485 jump normally, then does the exception return when the
486 CPU tries to execute code at the magic address.
487 This will cause the magic PC value to be pushed to
Stefan Weila1c72732011-04-28 17:20:38 +0200488 the stack if an interrupt occurred at the wrong time.
pbrook9ee6e8b2007-11-11 00:04:49 +0000489 We avoid this by disabling interrupts when
490 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000491 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000492 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
Peter Maydell4cc35612014-02-26 17:20:06 +0000493 || !(env->daif & PSTATE_I))) {
bellardb5ff1b32005-11-26 10:38:39 +0000494 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100495 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000496 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000497 }
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800498#elif defined(TARGET_UNICORE32)
499 if (interrupt_request & CPU_INTERRUPT_HARD
500 && !(env->uncached_asr & ASR_I)) {
Guan Xuetaod48813d2012-08-10 14:42:23 +0800501 env->exception_index = UC32_EXCP_INTR;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100502 cc->do_interrupt(cpu);
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800503 next_tb = 0;
504 }
bellardfdf9b3e2006-04-27 21:07:38 +0000505#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000506 if (interrupt_request & CPU_INTERRUPT_HARD) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100507 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000508 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000509 }
j_mayereddf68a2007-04-05 07:22:49 +0000510#elif defined(TARGET_ALPHA)
Richard Henderson6a80e082011-04-18 15:09:09 -0700511 {
512 int idx = -1;
513 /* ??? This hard-codes the OSF/1 interrupt levels. */
陳韋任e965fc32012-02-06 14:02:55 +0800514 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
Richard Henderson6a80e082011-04-18 15:09:09 -0700515 case 0 ... 3:
516 if (interrupt_request & CPU_INTERRUPT_HARD) {
517 idx = EXCP_DEV_INTERRUPT;
518 }
519 /* FALLTHRU */
520 case 4:
521 if (interrupt_request & CPU_INTERRUPT_TIMER) {
522 idx = EXCP_CLK_INTERRUPT;
523 }
524 /* FALLTHRU */
525 case 5:
526 if (interrupt_request & CPU_INTERRUPT_SMP) {
527 idx = EXCP_SMP_INTERRUPT;
528 }
529 /* FALLTHRU */
530 case 6:
531 if (interrupt_request & CPU_INTERRUPT_MCHK) {
532 idx = EXCP_MCHK;
533 }
534 }
535 if (idx >= 0) {
536 env->exception_index = idx;
537 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100538 cc->do_interrupt(cpu);
Richard Henderson6a80e082011-04-18 15:09:09 -0700539 next_tb = 0;
540 }
j_mayereddf68a2007-04-05 07:22:49 +0000541 }
thsf1ccf902007-10-08 13:16:14 +0000542#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000543 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100544 && (env->pregs[PR_CCS] & I_FLAG)
545 && !env->locked_irq) {
edgar_igl1b1a38b2008-06-09 23:18:06 +0000546 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100547 cc->do_interrupt(cpu);
edgar_igl1b1a38b2008-06-09 23:18:06 +0000548 next_tb = 0;
549 }
Lars Persson82193142012-06-14 16:23:55 +0200550 if (interrupt_request & CPU_INTERRUPT_NMI) {
551 unsigned int m_flag_archval;
552 if (env->pregs[PR_VR] < 32) {
553 m_flag_archval = M_FLAG_V10;
554 } else {
555 m_flag_archval = M_FLAG_V32;
556 }
557 if ((env->pregs[PR_CCS] & m_flag_archval)) {
558 env->exception_index = EXCP_NMI;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100559 cc->do_interrupt(cpu);
Lars Persson82193142012-06-14 16:23:55 +0200560 next_tb = 0;
561 }
thsf1ccf902007-10-08 13:16:14 +0000562 }
pbrook06338792007-05-23 19:58:11 +0000563#elif defined(TARGET_M68K)
564 if (interrupt_request & CPU_INTERRUPT_HARD
565 && ((env->sr & SR_I) >> SR_I_SHIFT)
566 < env->pending_level) {
567 /* Real hardware gets the interrupt vector via an
568 IACK cycle at this point. Current emulated
569 hardware doesn't rely on this, so we
570 provide/save the vector when the interrupt is
571 first signalled. */
572 env->exception_index = env->pending_vector;
Blue Swirl3c688822011-05-21 07:55:24 +0000573 do_interrupt_m68k_hardirq(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000574 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000575 }
Alexander Graf3110e292011-04-15 17:32:48 +0200576#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
577 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
578 (env->psw.mask & PSW_MASK_EXT)) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100579 cc->do_interrupt(cpu);
Alexander Graf3110e292011-04-15 17:32:48 +0200580 next_tb = 0;
581 }
Max Filippov40643d72011-09-06 03:55:41 +0400582#elif defined(TARGET_XTENSA)
583 if (interrupt_request & CPU_INTERRUPT_HARD) {
584 env->exception_index = EXC_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100585 cc->do_interrupt(cpu);
Max Filippov40643d72011-09-06 03:55:41 +0400586 next_tb = 0;
587 }
bellard68a79312003-06-30 13:12:32 +0000588#endif
Stefan Weilff2712b2011-04-28 17:20:35 +0200589 /* Don't use the cached interrupt_request value,
bellard9d050952006-05-22 22:03:52 +0000590 do_interrupt may have updated the EXITTB flag. */
Andreas Färber259186a2013-01-17 18:51:17 +0100591 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
592 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bellardbf3e8bf2004-02-16 21:58:54 +0000593 /* ensure that no TB jump will be modified as
594 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000595 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000596 }
aurel32be214e62009-03-06 21:48:00 +0000597 }
Andreas Färberfcd7d002012-12-17 08:02:44 +0100598 if (unlikely(cpu->exit_request)) {
599 cpu->exit_request = 0;
aurel32be214e62009-03-06 21:48:00 +0000600 env->exception_index = EXCP_INTERRUPT;
Blue Swirl1162c042011-05-14 12:52:35 +0000601 cpu_loop_exit(env);
bellard3fb2ded2003-06-24 13:22:59 +0000602 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700603 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000604 tb = tb_find_fast(env);
pbrookd5975362008-06-07 20:50:51 +0000605 /* Note: we do it here to avoid a gcc bug on Mac OS X when
606 doing it in tb_find_slow */
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700607 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
pbrookd5975362008-06-07 20:50:51 +0000608 /* as some TB could have been invalidated because
609 of memory exceptions while generating the code, we
610 must recompute the hash index here */
611 next_tb = 0;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700612 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000613 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100614 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
615 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
616 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
617 }
bellard8a40a182005-11-20 10:35:40 +0000618 /* see if we can patch the calling TB. When the TB
619 spans two pages, we cannot safely do a direct
620 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100621 if (next_tb != 0 && tb->page_addr[1] == -1) {
Peter Maydell09800112013-02-22 18:10:00 +0000622 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
623 next_tb & TB_EXIT_MASK, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000624 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700625 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
malc55e8b852008-11-04 14:18:13 +0000626
627 /* cpu_interrupt might be called while translating the
628 TB, but before it is linked into a potentially
629 infinite loop and becomes env->current_tb. Avoid
630 starting execution if there is a pending interrupt. */
Andreas Färberd77953b2013-01-16 19:29:31 +0100631 cpu->current_tb = tb;
Jan Kiszkab0052d12010-06-25 16:56:50 +0200632 barrier();
Andreas Färberfcd7d002012-12-17 08:02:44 +0100633 if (likely(!cpu->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000634 tc_ptr = tb->tc_ptr;
陳韋任e965fc32012-02-06 14:02:55 +0800635 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000636 next_tb = cpu_tb_exec(cpu, tc_ptr);
Peter Maydell378df4b2013-02-22 18:10:03 +0000637 switch (next_tb & TB_EXIT_MASK) {
638 case TB_EXIT_REQUESTED:
639 /* Something asked us to stop executing
640 * chained TBs; just continue round the main
641 * loop. Whatever requested the exit will also
642 * have set something else (eg exit_request or
643 * interrupt_request) which we will handle
644 * next time around the loop.
645 */
646 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
647 next_tb = 0;
648 break;
649 case TB_EXIT_ICOUNT_EXPIRED:
650 {
thsbf20dc02008-06-30 17:22:19 +0000651 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000652 int insns_left;
Peter Maydell09800112013-02-22 18:10:00 +0000653 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
Andreas Färber28ecfd72013-08-26 05:51:49 +0200654 insns_left = cpu->icount_decr.u32;
Andreas Färberefee7342013-08-26 05:39:29 +0200655 if (cpu->icount_extra && insns_left >= 0) {
pbrook2e70f6e2008-06-29 01:03:05 +0000656 /* Refill decrementer and continue execution. */
Andreas Färberefee7342013-08-26 05:39:29 +0200657 cpu->icount_extra += insns_left;
658 if (cpu->icount_extra > 0xffff) {
pbrook2e70f6e2008-06-29 01:03:05 +0000659 insns_left = 0xffff;
660 } else {
Andreas Färberefee7342013-08-26 05:39:29 +0200661 insns_left = cpu->icount_extra;
pbrook2e70f6e2008-06-29 01:03:05 +0000662 }
Andreas Färberefee7342013-08-26 05:39:29 +0200663 cpu->icount_extra -= insns_left;
Andreas Färber28ecfd72013-08-26 05:51:49 +0200664 cpu->icount_decr.u16.low = insns_left;
pbrook2e70f6e2008-06-29 01:03:05 +0000665 } else {
666 if (insns_left > 0) {
667 /* Execute remaining instructions. */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000668 cpu_exec_nocache(env, insns_left, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000669 }
670 env->exception_index = EXCP_INTERRUPT;
671 next_tb = 0;
Blue Swirl1162c042011-05-14 12:52:35 +0000672 cpu_loop_exit(env);
pbrook2e70f6e2008-06-29 01:03:05 +0000673 }
Peter Maydell378df4b2013-02-22 18:10:03 +0000674 break;
675 }
676 default:
677 break;
pbrook2e70f6e2008-06-29 01:03:05 +0000678 }
679 }
Andreas Färberd77953b2013-01-16 19:29:31 +0100680 cpu->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000681 /* reset soft MMU for next block (it can currently
682 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000683 } /* for(;;) */
Jan Kiszka0d101932011-07-02 09:50:51 +0200684 } else {
685 /* Reload env after longjmp - the compiler may have smashed all
686 * local variables as longjmp is marked 'noreturn'. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200687 cpu = current_cpu;
688 env = cpu->env_ptr;
Juergen Lock6c78f292013-10-03 16:09:37 +0200689#if !(defined(CONFIG_USER_ONLY) && \
690 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
691 cc = CPU_GET_CLASS(cpu);
692#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100693#ifdef TARGET_I386
694 x86_cpu = X86_CPU(cpu);
695#endif
bellard7d132992003-03-06 23:23:54 +0000696 }
bellard3fb2ded2003-06-24 13:22:59 +0000697 } /* for(;;) */
698
bellard7d132992003-03-06 23:23:54 +0000699
bellarde4533c72003-06-15 19:51:39 +0000700#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000701 /* restore flags in standard format */
Blue Swirle694d4e2011-05-16 19:38:48 +0000702 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
liguang80cf2c82013-05-28 16:21:08 +0800703 | (env->df & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000704#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000705 /* XXX: Save/restore host fpu exception state?. */
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800706#elif defined(TARGET_UNICORE32)
bellard93ac68b2003-09-30 20:57:29 +0000707#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000708#elif defined(TARGET_PPC)
Michael Walle81ea0e12011-02-17 23:45:02 +0100709#elif defined(TARGET_LM32)
pbrooke6e59062006-10-22 00:18:54 +0000710#elif defined(TARGET_M68K)
711 cpu_m68k_flush_flags(env, env->cc_op);
712 env->cc_op = CC_OP_FLAGS;
713 env->sr = (env->sr & 0xffe0)
714 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200715#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000716#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400717#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800718#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000719#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000720#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000721#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100722#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400723#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000724 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000725#else
726#error unsupported target CPU
727#endif
pbrook1057eaa2007-02-04 13:37:44 +0000728
Andreas Färber4917cf42013-05-27 05:17:50 +0200729 /* fail safe : never use current_cpu outside cpu_exec() */
730 current_cpu = NULL;
bellard7d132992003-03-06 23:23:54 +0000731 return ret;
732}