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bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
bellard7d132992003-03-06 23:23:54 +000019 */
20#include "exec-i386.h"
bellard956034d2003-04-29 20:40:53 +000021#include "disas.h"
bellard7d132992003-03-06 23:23:54 +000022
bellarddc990652003-03-19 00:00:28 +000023//#define DEBUG_EXEC
bellard7d132992003-03-06 23:23:54 +000024#define DEBUG_FLUSH
bellard9de5e442003-03-23 16:49:39 +000025//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000026
27/* main execution loop */
28
29/* maximum total translate dcode allocated */
30#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
31//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
32#define CODE_GEN_MAX_SIZE 65536
33#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
34
35/* threshold to flush the translated code buffer */
36#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
37
38#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64)
39#define CODE_GEN_HASH_BITS 15
40#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
bellard6dbad632003-03-16 18:05:05 +000041
bellard7d132992003-03-06 23:23:54 +000042typedef struct TranslationBlock {
bellarddab2ed92003-03-22 15:23:14 +000043 unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
44 unsigned long cs_base; /* CS base for this block */
bellard6dbad632003-03-16 18:05:05 +000045 unsigned int flags; /* flags defining in which context the code was generated */
bellard7d132992003-03-06 23:23:54 +000046 uint8_t *tc_ptr; /* pointer to the translated code */
47 struct TranslationBlock *hash_next; /* next matching block */
48} TranslationBlock;
49
50TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
51TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
52int nb_tbs;
53
54uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
55uint8_t *code_gen_ptr;
56
bellard1b6b0292003-03-22 17:31:38 +000057/* thread support */
58
59#ifdef __powerpc__
60static inline int testandset (int *p)
61{
62 int ret;
63 __asm__ __volatile__ (
64 "0: lwarx %0,0,%1 ;"
65 " xor. %0,%3,%0;"
66 " bne 1f;"
67 " stwcx. %2,0,%1;"
68 " bne- 0b;"
69 "1: "
70 : "=&r" (ret)
71 : "r" (p), "r" (1), "r" (0)
72 : "cr0", "memory");
73 return ret;
74}
75#endif
76
77#ifdef __i386__
78static inline int testandset (int *p)
79{
80 char ret;
81 long int readval;
82
83 __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
84 : "=q" (ret), "=m" (*p), "=a" (readval)
85 : "r" (1), "m" (*p), "a" (0)
86 : "memory");
87 return ret;
88}
89#endif
90
bellardfb3e5842003-03-29 17:32:36 +000091#ifdef __s390__
92static inline int testandset (int *p)
93{
94 int ret;
95
96 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
97 " jl 0b"
98 : "=&d" (ret)
99 : "r" (1), "a" (p), "0" (*p)
100 : "cc", "memory" );
101 return ret;
102}
103#endif
104
bellarde026db52003-04-29 21:07:28 +0000105#ifdef __alpha__
106int testandset (int *p)
107{
108 int ret;
109 unsigned long one;
110
111 __asm__ __volatile__ ("0: mov 1,%2\n"
112 " ldl_l %0,%1\n"
113 " stl_c %2,%1\n"
114 " beq %2,1f\n"
115 ".subsection 2\n"
116 "1: br 0b\n"
117 ".previous"
118 : "=r" (ret), "=m" (*p), "=r" (one)
119 : "m" (*p));
120 return ret;
121}
122#endif
123
bellardd014c982003-04-29 21:26:53 +0000124#ifdef __sparc__
125static inline int testandset (int *p)
126{
127 int ret;
128
129 __asm__ __volatile__("ldstub [%1], %0"
130 : "=r" (ret)
131 : "r" (p)
132 : "memory");
133
134 return (ret ? 1 : 0);
135}
136#endif
137
bellard1b6b0292003-03-22 17:31:38 +0000138int global_cpu_lock = 0;
139
140void cpu_lock(void)
141{
142 while (testandset(&global_cpu_lock));
143}
144
145void cpu_unlock(void)
146{
147 global_cpu_lock = 0;
148}
149
bellard9de5e442003-03-23 16:49:39 +0000150/* exception support */
151/* NOTE: not static to force relocation generation by GCC */
bellardb56dad12003-05-08 15:38:04 +0000152void raise_exception_err(int exception_index, int error_code)
bellard9de5e442003-03-23 16:49:39 +0000153{
154 /* NOTE: the register at this point must be saved by hand because
155 longjmp restore them */
156#ifdef reg_EAX
157 env->regs[R_EAX] = EAX;
158#endif
159#ifdef reg_ECX
160 env->regs[R_ECX] = ECX;
161#endif
162#ifdef reg_EDX
163 env->regs[R_EDX] = EDX;
164#endif
165#ifdef reg_EBX
166 env->regs[R_EBX] = EBX;
167#endif
168#ifdef reg_ESP
169 env->regs[R_ESP] = ESP;
170#endif
171#ifdef reg_EBP
172 env->regs[R_EBP] = EBP;
173#endif
174#ifdef reg_ESI
175 env->regs[R_ESI] = ESI;
176#endif
177#ifdef reg_EDI
178 env->regs[R_EDI] = EDI;
179#endif
180 env->exception_index = exception_index;
bellardb56dad12003-05-08 15:38:04 +0000181 env->error_code = error_code;
bellard9de5e442003-03-23 16:49:39 +0000182 longjmp(env->jmp_env, 1);
183}
184
bellardb56dad12003-05-08 15:38:04 +0000185/* short cut if error_code is 0 or not present */
186void raise_exception(int exception_index)
187{
188 raise_exception_err(exception_index, 0);
189}
190
bellard7d132992003-03-06 23:23:54 +0000191void cpu_x86_tblocks_init(void)
192{
193 if (!code_gen_ptr) {
194 code_gen_ptr = code_gen_buffer;
195 }
196}
197
198/* flush all the translation blocks */
199static void tb_flush(void)
200{
201 int i;
202#ifdef DEBUG_FLUSH
203 printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
204 code_gen_ptr - code_gen_buffer,
205 nb_tbs,
206 (code_gen_ptr - code_gen_buffer) / nb_tbs);
207#endif
208 nb_tbs = 0;
209 for(i = 0;i < CODE_GEN_HASH_SIZE; i++)
210 tb_hash[i] = NULL;
211 code_gen_ptr = code_gen_buffer;
212 /* XXX: flush processor icache at this point */
213}
214
215/* find a translation block in the translation cache. If not found,
bellard9de5e442003-03-23 16:49:39 +0000216 return NULL and the pointer to the last element of the list in pptb */
217static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
218 unsigned long pc,
219 unsigned long cs_base,
220 unsigned int flags)
bellard7d132992003-03-06 23:23:54 +0000221{
222 TranslationBlock **ptb, *tb;
223 unsigned int h;
224
225 h = pc & (CODE_GEN_HASH_SIZE - 1);
226 ptb = &tb_hash[h];
bellardb56dad12003-05-08 15:38:04 +0000227#if 0
228 /* XXX: hack to handle 16 bit modyfing code */
229 if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
230#endif
231 for(;;) {
232 tb = *ptb;
233 if (!tb)
234 break;
235 if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
bellard7d132992003-03-06 23:23:54 +0000236 return tb;
bellardb56dad12003-05-08 15:38:04 +0000237 ptb = &tb->hash_next;
238 }
bellard9de5e442003-03-23 16:49:39 +0000239 *pptb = ptb;
240 return NULL;
241}
242
243/* allocate a new translation block. flush the translation buffer if
244 too many translation blocks or too much generated code */
245static inline TranslationBlock *tb_alloc(void)
246{
247 TranslationBlock *tb;
bellard7d132992003-03-06 23:23:54 +0000248 if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
249 (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
250 tb_flush();
251 tb = &tbs[nb_tbs++];
bellard7d132992003-03-06 23:23:54 +0000252 return tb;
253}
254
255int cpu_x86_exec(CPUX86State *env1)
256{
257 int saved_T0, saved_T1, saved_A0;
258 CPUX86State *saved_env;
bellard04369ff2003-03-20 22:33:23 +0000259#ifdef reg_EAX
260 int saved_EAX;
261#endif
262#ifdef reg_ECX
263 int saved_ECX;
264#endif
265#ifdef reg_EDX
266 int saved_EDX;
267#endif
268#ifdef reg_EBX
269 int saved_EBX;
270#endif
271#ifdef reg_ESP
272 int saved_ESP;
273#endif
274#ifdef reg_EBP
275 int saved_EBP;
276#endif
277#ifdef reg_ESI
278 int saved_ESI;
279#endif
280#ifdef reg_EDI
281 int saved_EDI;
282#endif
bellard7d132992003-03-06 23:23:54 +0000283 int code_gen_size, ret;
284 void (*gen_func)(void);
bellard9de5e442003-03-23 16:49:39 +0000285 TranslationBlock *tb, **ptb;
bellarddab2ed92003-03-22 15:23:14 +0000286 uint8_t *tc_ptr, *cs_base, *pc;
bellard6dbad632003-03-16 18:05:05 +0000287 unsigned int flags;
288
bellard7d132992003-03-06 23:23:54 +0000289 /* first we save global registers */
290 saved_T0 = T0;
291 saved_T1 = T1;
292 saved_A0 = A0;
293 saved_env = env;
294 env = env1;
bellard04369ff2003-03-20 22:33:23 +0000295#ifdef reg_EAX
296 saved_EAX = EAX;
297 EAX = env->regs[R_EAX];
298#endif
299#ifdef reg_ECX
300 saved_ECX = ECX;
301 ECX = env->regs[R_ECX];
302#endif
303#ifdef reg_EDX
304 saved_EDX = EDX;
305 EDX = env->regs[R_EDX];
306#endif
307#ifdef reg_EBX
308 saved_EBX = EBX;
309 EBX = env->regs[R_EBX];
310#endif
311#ifdef reg_ESP
312 saved_ESP = ESP;
313 ESP = env->regs[R_ESP];
314#endif
315#ifdef reg_EBP
316 saved_EBP = EBP;
317 EBP = env->regs[R_EBP];
318#endif
319#ifdef reg_ESI
320 saved_ESI = ESI;
321 ESI = env->regs[R_ESI];
322#endif
323#ifdef reg_EDI
324 saved_EDI = EDI;
325 EDI = env->regs[R_EDI];
326#endif
bellard7d132992003-03-06 23:23:54 +0000327
bellard9de5e442003-03-23 16:49:39 +0000328 /* put eflags in CPU temporary format */
bellardfc2b4c42003-03-29 16:52:44 +0000329 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
330 DF = 1 - (2 * ((env->eflags >> 10) & 1));
bellard9de5e442003-03-23 16:49:39 +0000331 CC_OP = CC_OP_EFLAGS;
bellardfc2b4c42003-03-29 16:52:44 +0000332 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard9de5e442003-03-23 16:49:39 +0000333 env->interrupt_request = 0;
bellard9d27abd2003-05-10 13:13:54 +0000334
bellard7d132992003-03-06 23:23:54 +0000335 /* prepare setjmp context for exception handling */
336 if (setjmp(env->jmp_env) == 0) {
337 for(;;) {
bellard9de5e442003-03-23 16:49:39 +0000338 if (env->interrupt_request) {
339 raise_exception(EXCP_INTERRUPT);
340 }
bellard7d132992003-03-06 23:23:54 +0000341#ifdef DEBUG_EXEC
342 if (loglevel) {
bellard9d27abd2003-05-10 13:13:54 +0000343 /* XXX: save all volatile state in cpu state */
344 /* restore flags in standard format */
345 env->regs[R_EAX] = EAX;
346 env->regs[R_EBX] = EBX;
347 env->regs[R_ECX] = ECX;
348 env->regs[R_EDX] = EDX;
349 env->regs[R_ESI] = ESI;
350 env->regs[R_EDI] = EDI;
351 env->regs[R_EBP] = EBP;
352 env->regs[R_ESP] = ESP;
353 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
354 cpu_x86_dump_state(env, logfile, 0);
355 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard7d132992003-03-06 23:23:54 +0000356 }
357#endif
bellard6dbad632003-03-16 18:05:05 +0000358 /* we compute the CPU state. We assume it will not
359 change during the whole generated block. */
360 flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
bellarddab2ed92003-03-22 15:23:14 +0000361 flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
bellard6dbad632003-03-16 18:05:05 +0000362 flags |= (((unsigned long)env->seg_cache[R_DS].base |
363 (unsigned long)env->seg_cache[R_ES].base |
364 (unsigned long)env->seg_cache[R_SS].base) != 0) <<
365 GEN_FLAG_ADDSEG_SHIFT;
bellard9d27abd2003-05-10 13:13:54 +0000366 if (!(env->eflags & VM_MASK)) {
367 flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
368 } else {
369 /* NOTE: a dummy CPL is kept */
370 flags |= (1 << GEN_FLAG_VM_SHIFT);
371 flags |= (3 << GEN_FLAG_CPL_SHIFT);
372 }
bellardb56dad12003-05-08 15:38:04 +0000373 flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
bellarddab2ed92003-03-22 15:23:14 +0000374 cs_base = env->seg_cache[R_CS].base;
375 pc = cs_base + env->eip;
bellard9de5e442003-03-23 16:49:39 +0000376 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
377 flags);
378 if (!tb) {
bellard7d132992003-03-06 23:23:54 +0000379 /* if no translated code available, then translate it now */
bellard1b6b0292003-03-22 17:31:38 +0000380 /* XXX: very inefficient: we lock all the cpus when
381 generating code */
382 cpu_lock();
bellard7d132992003-03-06 23:23:54 +0000383 tc_ptr = code_gen_ptr;
bellard9de5e442003-03-23 16:49:39 +0000384 ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
385 &code_gen_size, pc, cs_base, flags);
386 /* if invalid instruction, signal it */
387 if (ret != 0) {
388 cpu_unlock();
389 raise_exception(EXCP06_ILLOP);
390 }
391 tb = tb_alloc();
392 *ptb = tb;
393 tb->pc = (unsigned long)pc;
394 tb->cs_base = (unsigned long)cs_base;
395 tb->flags = flags;
bellard7d132992003-03-06 23:23:54 +0000396 tb->tc_ptr = tc_ptr;
bellard9de5e442003-03-23 16:49:39 +0000397 tb->hash_next = NULL;
bellard7d132992003-03-06 23:23:54 +0000398 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
bellard1b6b0292003-03-22 17:31:38 +0000399 cpu_unlock();
bellard7d132992003-03-06 23:23:54 +0000400 }
bellard9d27abd2003-05-10 13:13:54 +0000401#ifdef DEBUG_EXEC
bellard956034d2003-04-29 20:40:53 +0000402 if (loglevel) {
403 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
404 (long)tb->tc_ptr, (long)tb->pc,
405 lookup_symbol((void *)tb->pc));
bellard956034d2003-04-29 20:40:53 +0000406 }
bellard9d27abd2003-05-10 13:13:54 +0000407#endif
bellard7d132992003-03-06 23:23:54 +0000408 /* execute the generated code */
bellard9de5e442003-03-23 16:49:39 +0000409 tc_ptr = tb->tc_ptr;
bellard7d132992003-03-06 23:23:54 +0000410 gen_func = (void *)tc_ptr;
411 gen_func();
412 }
413 }
414 ret = env->exception_index;
415
bellard9de5e442003-03-23 16:49:39 +0000416 /* restore flags in standard format */
bellardfc2b4c42003-03-29 16:52:44 +0000417 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard9de5e442003-03-23 16:49:39 +0000418
bellard7d132992003-03-06 23:23:54 +0000419 /* restore global registers */
bellard04369ff2003-03-20 22:33:23 +0000420#ifdef reg_EAX
421 EAX = saved_EAX;
422#endif
423#ifdef reg_ECX
424 ECX = saved_ECX;
425#endif
426#ifdef reg_EDX
427 EDX = saved_EDX;
428#endif
429#ifdef reg_EBX
430 EBX = saved_EBX;
431#endif
432#ifdef reg_ESP
433 ESP = saved_ESP;
434#endif
435#ifdef reg_EBP
436 EBP = saved_EBP;
437#endif
438#ifdef reg_ESI
439 ESI = saved_ESI;
440#endif
441#ifdef reg_EDI
442 EDI = saved_EDI;
443#endif
bellard7d132992003-03-06 23:23:54 +0000444 T0 = saved_T0;
445 T1 = saved_T1;
446 A0 = saved_A0;
447 env = saved_env;
448 return ret;
449}
bellard6dbad632003-03-16 18:05:05 +0000450
bellard9de5e442003-03-23 16:49:39 +0000451void cpu_x86_interrupt(CPUX86State *s)
452{
453 s->interrupt_request = 1;
454}
455
456
bellard6dbad632003-03-16 18:05:05 +0000457void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
458{
459 CPUX86State *saved_env;
460
461 saved_env = env;
462 env = s;
463 load_seg(seg_reg, selector);
464 env = saved_env;
465}
bellard9de5e442003-03-23 16:49:39 +0000466
467#undef EAX
468#undef ECX
469#undef EDX
470#undef EBX
471#undef ESP
472#undef EBP
473#undef ESI
474#undef EDI
475#undef EIP
476#include <signal.h>
477#include <sys/ucontext.h>
478
bellardb56dad12003-05-08 15:38:04 +0000479/* 'pc' is the host PC at which the exception was raised. 'address' is
480 the effective address of the memory exception */
bellard9de5e442003-03-23 16:49:39 +0000481static inline int handle_cpu_signal(unsigned long pc,
bellardb56dad12003-05-08 15:38:04 +0000482 unsigned long address,
bellard9de5e442003-03-23 16:49:39 +0000483 sigset_t *old_set)
484{
485#ifdef DEBUG_SIGNAL
486 printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
487 pc, *(unsigned long *)old_set);
488#endif
489 if (pc >= (unsigned long)code_gen_buffer &&
490 pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
491 /* the PC is inside the translated code. It means that we have
492 a virtual CPU fault */
493 /* we restore the process signal mask as the sigreturn should
494 do it */
495 sigprocmask(SIG_SETMASK, old_set, NULL);
496 /* XXX: need to compute virtual pc position by retranslating
497 code. The rest of the CPU state should be correct. */
bellardb56dad12003-05-08 15:38:04 +0000498 env->cr2 = address;
499 /* XXX: more precise exception code */
500 raise_exception_err(EXCP0E_PAGE, 4);
bellard9de5e442003-03-23 16:49:39 +0000501 /* never comes here */
502 return 1;
503 } else {
504 return 0;
505 }
506}
507
508int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
509 void *puc)
510{
511#if defined(__i386__)
512 struct ucontext *uc = puc;
513 unsigned long pc;
514 sigset_t *pold_set;
515
bellardd691f662003-03-24 21:58:34 +0000516#ifndef REG_EIP
517/* for glibc 2.1 */
518#define REG_EIP EIP
519#endif
bellardfc2b4c42003-03-29 16:52:44 +0000520 pc = uc->uc_mcontext.gregs[REG_EIP];
bellard9de5e442003-03-23 16:49:39 +0000521 pold_set = &uc->uc_sigmask;
bellardb56dad12003-05-08 15:38:04 +0000522 return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set);
bellard9de5e442003-03-23 16:49:39 +0000523#else
524#warning No CPU specific signal handler: cannot handle target SIGSEGV events
525 return 0;
526#endif
527}