blob: 6559d5e9222f0f98bf6b528556445595ec6aa240 [file] [log] [blame]
bellard7d132992003-03-06 23:23:54 +00001/*
陳韋任e965fc32012-02-06 14:02:55 +08002 * emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
Blue Swirlcea5f9a2011-05-15 16:03:25 +000020#include "cpu.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +020021#include "disas/disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/atomic.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010024#include "sysemu/qtest.h"
bellard7d132992003-03-06 23:23:54 +000025
Andreas Färber9349b4f2012-03-14 01:38:32 +010026void cpu_loop_exit(CPUArchState *env)
bellarde4533c72003-06-15 19:51:39 +000027{
Andreas Färberd77953b2013-01-16 19:29:31 +010028 CPUState *cpu = ENV_GET_CPU(env);
29
30 cpu->current_tb = NULL;
Peter Maydell6ab7e542013-02-20 15:21:09 +000031 siglongjmp(env->jmp_env, 1);
bellarde4533c72003-06-15 19:51:39 +000032}
thsbfed01f2007-06-03 17:44:37 +000033
bellardfbf9eeb2004-04-25 21:21:33 +000034/* exit the current TB from a signal handler. The host registers are
35 restored in a state compatible with the CPU emulator
36 */
Blue Swirl9eff14f2011-05-21 08:42:35 +000037#if defined(CONFIG_SOFTMMU)
Andreas Färber9349b4f2012-03-14 01:38:32 +010038void cpu_resume_from_signal(CPUArchState *env, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000039{
Blue Swirl9eff14f2011-05-21 08:42:35 +000040 /* XXX: restore cpu registers saved in host registers */
41
42 env->exception_index = -1;
Peter Maydell6ab7e542013-02-20 15:21:09 +000043 siglongjmp(env->jmp_env, 1);
Blue Swirl9eff14f2011-05-21 08:42:35 +000044}
Blue Swirl9eff14f2011-05-21 08:42:35 +000045#endif
bellardfbf9eeb2004-04-25 21:21:33 +000046
Peter Maydell77211372013-02-22 18:10:02 +000047/* Execute a TB, and fix up the CPU state afterwards if necessary */
48static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
49{
50 CPUArchState *env = cpu->env_ptr;
Richard Henderson03afa5f2013-11-06 17:29:39 +100051 uintptr_t next_tb;
52
53#if defined(DEBUG_DISAS)
54 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
55#if defined(TARGET_I386)
56 log_cpu_state(cpu, CPU_DUMP_CCOP);
57#elif defined(TARGET_M68K)
58 /* ??? Should not modify env state for dumping. */
59 cpu_m68k_flush_flags(env, env->cc_op);
60 env->cc_op = CC_OP_FLAGS;
61 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
62 log_cpu_state(cpu, 0);
63#else
64 log_cpu_state(cpu, 0);
65#endif
66 }
67#endif /* DEBUG_DISAS */
68
69 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
Peter Maydell77211372013-02-22 18:10:02 +000070 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
71 /* We didn't start executing this TB (eg because the instruction
72 * counter hit zero); we must restore the guest PC to the address
73 * of the start of the TB.
74 */
Andreas Färberbdf7ae52013-06-28 19:31:32 +020075 CPUClass *cc = CPU_GET_CLASS(cpu);
Peter Maydell77211372013-02-22 18:10:02 +000076 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
Andreas Färberbdf7ae52013-06-28 19:31:32 +020077 if (cc->synchronize_from_tb) {
78 cc->synchronize_from_tb(cpu, tb);
79 } else {
80 assert(cc->set_pc);
81 cc->set_pc(cpu, tb->pc);
82 }
Peter Maydell77211372013-02-22 18:10:02 +000083 }
Peter Maydell378df4b2013-02-22 18:10:03 +000084 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
85 /* We were asked to stop executing TBs (probably a pending
86 * interrupt. We've now stopped, so clear the flag.
87 */
88 cpu->tcg_exit_req = 0;
89 }
Peter Maydell77211372013-02-22 18:10:02 +000090 return next_tb;
91}
92
pbrook2e70f6e2008-06-29 01:03:05 +000093/* Execute the code without caching the generated code. An interpreter
94 could be used if available. */
Andreas Färber9349b4f2012-03-14 01:38:32 +010095static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000096 TranslationBlock *orig_tb)
pbrook2e70f6e2008-06-29 01:03:05 +000097{
Andreas Färberd77953b2013-01-16 19:29:31 +010098 CPUState *cpu = ENV_GET_CPU(env);
pbrook2e70f6e2008-06-29 01:03:05 +000099 TranslationBlock *tb;
100
101 /* Should never happen.
102 We only end up here when an existing TB is too long. */
103 if (max_cycles > CF_COUNT_MASK)
104 max_cycles = CF_COUNT_MASK;
105
106 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
107 max_cycles);
Andreas Färberd77953b2013-01-16 19:29:31 +0100108 cpu->current_tb = tb;
pbrook2e70f6e2008-06-29 01:03:05 +0000109 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000110 cpu_tb_exec(cpu, tb->tc_ptr);
Andreas Färberd77953b2013-01-16 19:29:31 +0100111 cpu->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000112 tb_phys_invalidate(tb, -1);
113 tb_free(tb);
114}
115
Andreas Färber9349b4f2012-03-14 01:38:32 +0100116static TranslationBlock *tb_find_slow(CPUArchState *env,
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000117 target_ulong pc,
bellard8a40a182005-11-20 10:35:40 +0000118 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +0000119 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +0000120{
121 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +0000122 unsigned int h;
Blue Swirl337fc752011-09-04 11:06:22 +0000123 tb_page_addr_t phys_pc, phys_page1;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000124 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +0000125
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700126 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +0000127
bellard8a40a182005-11-20 10:35:40 +0000128 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000129 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +0000130 phys_page1 = phys_pc & TARGET_PAGE_MASK;
bellard8a40a182005-11-20 10:35:40 +0000131 h = tb_phys_hash_func(phys_pc);
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700132 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
bellard8a40a182005-11-20 10:35:40 +0000133 for(;;) {
134 tb = *ptb1;
135 if (!tb)
136 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000137 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000138 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000139 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000140 tb->flags == flags) {
141 /* check next page if needed */
142 if (tb->page_addr[1] != -1) {
Blue Swirl337fc752011-09-04 11:06:22 +0000143 tb_page_addr_t phys_page2;
144
ths5fafdf22007-09-16 21:08:06 +0000145 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000146 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000147 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000148 if (tb->page_addr[1] == phys_page2)
149 goto found;
150 } else {
151 goto found;
152 }
153 }
154 ptb1 = &tb->phys_hash_next;
155 }
156 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000157 /* if no translated code available, then translate it now */
158 tb = tb_gen_code(env, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000159
bellard8a40a182005-11-20 10:35:40 +0000160 found:
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300161 /* Move the last found TB to the head of the list */
162 if (likely(*ptb1)) {
163 *ptb1 = tb->phys_hash_next;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700164 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
165 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300166 }
bellard8a40a182005-11-20 10:35:40 +0000167 /* we add the TB in the virtual pc hash table */
168 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000169 return tb;
170}
171
Andreas Färber9349b4f2012-03-14 01:38:32 +0100172static inline TranslationBlock *tb_find_fast(CPUArchState *env)
bellard8a40a182005-11-20 10:35:40 +0000173{
174 TranslationBlock *tb;
175 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000176 int flags;
bellard8a40a182005-11-20 10:35:40 +0000177
178 /* we record a subset of the CPU state. It will
179 always be the same before a given translated block
180 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000181 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bellardbce61842008-02-01 22:18:51 +0000182 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000183 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
184 tb->flags != flags)) {
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000185 tb = tb_find_slow(env, pc, cs_base, flags);
bellard8a40a182005-11-20 10:35:40 +0000186 }
187 return tb;
188}
189
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100190static CPUDebugExcpHandler *debug_excp_handler;
191
Igor Mammedov84e3b602012-06-21 18:29:38 +0200192void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100193{
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100194 debug_excp_handler = handler;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100195}
196
Andreas Färber9349b4f2012-03-14 01:38:32 +0100197static void cpu_handle_debug_exception(CPUArchState *env)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100198{
199 CPUWatchpoint *wp;
200
201 if (!env->watchpoint_hit) {
202 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
203 wp->flags &= ~BP_WATCHPOINT_HIT;
204 }
205 }
206 if (debug_excp_handler) {
207 debug_excp_handler(env);
208 }
209}
210
bellard7d132992003-03-06 23:23:54 +0000211/* main execution loop */
212
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300213volatile sig_atomic_t exit_request;
214
Andreas Färber9349b4f2012-03-14 01:38:32 +0100215int cpu_exec(CPUArchState *env)
bellard7d132992003-03-06 23:23:54 +0000216{
Andreas Färberc356a1b2012-05-04 19:39:23 +0200217 CPUState *cpu = ENV_GET_CPU(env);
Andreas Färber97a8ea52013-02-02 10:57:51 +0100218#if !(defined(CONFIG_USER_ONLY) && \
219 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
220 CPUClass *cc = CPU_GET_CLASS(cpu);
221#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100222#ifdef TARGET_I386
223 X86CPU *x86_cpu = X86_CPU(cpu);
224#endif
bellard8a40a182005-11-20 10:35:40 +0000225 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000226 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000227 uint8_t *tc_ptr;
Richard Henderson3e9bd632013-08-20 14:40:25 -0700228 uintptr_t next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000229
Andreas Färber259186a2013-01-17 18:51:17 +0100230 if (cpu->halted) {
Andreas Färber3993c6b2012-05-03 06:43:49 +0200231 if (!cpu_has_work(cpu)) {
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100232 return EXCP_HALTED;
233 }
234
Andreas Färber259186a2013-01-17 18:51:17 +0100235 cpu->halted = 0;
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100236 }
bellard5a1e3cf2005-11-23 21:02:53 +0000237
Andreas Färber4917cf42013-05-27 05:17:50 +0200238 current_cpu = cpu;
bellarde4533c72003-06-15 19:51:39 +0000239
Andreas Färber4917cf42013-05-27 05:17:50 +0200240 /* As long as current_cpu is null, up to the assignment just above,
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200241 * requests by other threads to exit the execution loop are expected to
242 * be issued using the exit_request global. We must make sure that our
Andreas Färber4917cf42013-05-27 05:17:50 +0200243 * evaluation of the global value is performed past the current_cpu
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200244 * value transition point, which requires a memory barrier as well as
245 * an instruction scheduling constraint on modern architectures. */
246 smp_mb();
247
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200248 if (unlikely(exit_request)) {
Andreas Färberfcd7d002012-12-17 08:02:44 +0100249 cpu->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300250 }
251
thsecb644f2007-06-03 18:45:53 +0000252#if defined(TARGET_I386)
Jan Kiszka6792a572011-02-07 12:19:18 +0100253 /* put eflags in CPU temporary format */
254 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
liguang80cf2c82013-05-28 16:21:08 +0800255 env->df = 1 - (2 * ((env->eflags >> 10) & 1));
Jan Kiszka6792a572011-02-07 12:19:18 +0100256 CC_OP = CC_OP_EFLAGS;
257 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000258#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000259#elif defined(TARGET_M68K)
260 env->cc_op = CC_OP_FLAGS;
261 env->cc_dest = env->sr & 0xf;
262 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000263#elif defined(TARGET_ALPHA)
264#elif defined(TARGET_ARM)
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800265#elif defined(TARGET_UNICORE32)
thsecb644f2007-06-03 18:45:53 +0000266#elif defined(TARGET_PPC)
Elie Richa4e85f822011-07-22 05:58:39 +0000267 env->reserve_addr = -1;
Michael Walle81ea0e12011-02-17 23:45:02 +0100268#elif defined(TARGET_LM32)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200269#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000270#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400271#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800272#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000273#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000274#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100275#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400276#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000277 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000278#else
279#error unsupported target CPU
280#endif
bellard3fb2ded2003-06-24 13:22:59 +0000281 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000282
bellard7d132992003-03-06 23:23:54 +0000283 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000284 for(;;) {
Peter Maydell6ab7e542013-02-20 15:21:09 +0000285 if (sigsetjmp(env->jmp_env, 0) == 0) {
bellard3fb2ded2003-06-24 13:22:59 +0000286 /* if an exception is pending, we execute it here */
287 if (env->exception_index >= 0) {
288 if (env->exception_index >= EXCP_INTERRUPT) {
289 /* exit request from the cpu execution loop */
290 ret = env->exception_index;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100291 if (ret == EXCP_DEBUG) {
292 cpu_handle_debug_exception(env);
293 }
bellard3fb2ded2003-06-24 13:22:59 +0000294 break;
aurel3272d239e2009-01-14 19:40:27 +0000295 } else {
296#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000297 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000298 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000299 loop */
bellard83479e72003-06-25 16:12:37 +0000300#if defined(TARGET_I386)
Andreas Färber97a8ea52013-02-02 10:57:51 +0100301 cc->do_interrupt(cpu);
bellard83479e72003-06-25 16:12:37 +0000302#endif
bellard3fb2ded2003-06-24 13:22:59 +0000303 ret = env->exception_index;
304 break;
aurel3272d239e2009-01-14 19:40:27 +0000305#else
Andreas Färber97a8ea52013-02-02 10:57:51 +0100306 cc->do_interrupt(cpu);
Paolo Bonzini301d2902010-01-15 09:41:01 +0100307 env->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000308#endif
bellard3fb2ded2003-06-24 13:22:59 +0000309 }
ths5fafdf22007-09-16 21:08:06 +0000310 }
bellard9df217a2005-02-10 22:05:51 +0000311
blueswir1b5fc09a2008-05-04 06:38:18 +0000312 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000313 for(;;) {
Andreas Färber259186a2013-01-17 18:51:17 +0100314 interrupt_request = cpu->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000315 if (unlikely(interrupt_request)) {
Andreas Färbered2803d2013-06-21 20:20:45 +0200316 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
malce1638bd2008-11-06 18:54:46 +0000317 /* Mask out external interrupts for this step. */
Richard Henderson3125f762011-05-04 13:34:25 -0700318 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
malce1638bd2008-11-06 18:54:46 +0000319 }
pbrook6658ffb2007-03-16 23:58:11 +0000320 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
Andreas Färber259186a2013-01-17 18:51:17 +0100321 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
pbrook6658ffb2007-03-16 23:58:11 +0000322 env->exception_index = EXCP_DEBUG;
Blue Swirl1162c042011-05-14 12:52:35 +0000323 cpu_loop_exit(env);
pbrook6658ffb2007-03-16 23:58:11 +0000324 }
balroga90b7312007-05-01 01:28:01 +0000325#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200326 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800327 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
balroga90b7312007-05-01 01:28:01 +0000328 if (interrupt_request & CPU_INTERRUPT_HALT) {
Andreas Färber259186a2013-01-17 18:51:17 +0100329 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
330 cpu->halted = 1;
balroga90b7312007-05-01 01:28:01 +0000331 env->exception_index = EXCP_HLT;
Blue Swirl1162c042011-05-14 12:52:35 +0000332 cpu_loop_exit(env);
balroga90b7312007-05-01 01:28:01 +0000333 }
334#endif
bellard68a79312003-06-30 13:12:32 +0000335#if defined(TARGET_I386)
Jan Kiszka5d62c432012-07-09 16:42:32 +0200336#if !defined(CONFIG_USER_ONLY)
337 if (interrupt_request & CPU_INTERRUPT_POLL) {
Andreas Färber259186a2013-01-17 18:51:17 +0100338 cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
Andreas Färber693fa552013-12-24 03:18:12 +0100339 apic_poll_irq(x86_cpu->apic_state);
Jan Kiszka5d62c432012-07-09 16:42:32 +0200340 }
341#endif
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300342 if (interrupt_request & CPU_INTERRUPT_INIT) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000343 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
344 0);
Andreas Färber693fa552013-12-24 03:18:12 +0100345 do_cpu_init(x86_cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300346 env->exception_index = EXCP_HALTED;
Blue Swirl1162c042011-05-14 12:52:35 +0000347 cpu_loop_exit(env);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300348 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
Andreas Färber693fa552013-12-24 03:18:12 +0100349 do_cpu_sipi(x86_cpu);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300350 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000351 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
352 !(env->hflags & HF_SMM_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000353 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
354 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100355 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
Andreas Färber693fa552013-12-24 03:18:12 +0100356 do_smm_enter(x86_cpu);
bellarddb620f42008-06-04 17:02:19 +0000357 next_tb = 0;
358 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
359 !(env->hflags2 & HF2_NMI_MASK)) {
Andreas Färber259186a2013-01-17 18:51:17 +0100360 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
bellarddb620f42008-06-04 17:02:19 +0000361 env->hflags2 |= HF2_NMI_MASK;
Blue Swirle694d4e2011-05-16 19:38:48 +0000362 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
bellarddb620f42008-06-04 17:02:19 +0000363 next_tb = 0;
陳韋任e965fc32012-02-06 14:02:55 +0800364 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
Andreas Färber259186a2013-01-17 18:51:17 +0100365 cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
Blue Swirle694d4e2011-05-16 19:38:48 +0000366 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
Huang Ying79c4f6b2009-06-23 10:05:14 +0800367 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000368 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
369 (((env->hflags2 & HF2_VINTR_MASK) &&
370 (env->hflags2 & HF2_HIF_MASK)) ||
371 (!(env->hflags2 & HF2_VINTR_MASK) &&
372 (env->eflags & IF_MASK &&
373 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
374 int intno;
Blue Swirl77b2bc22012-04-28 19:35:10 +0000375 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
376 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100377 cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
378 CPU_INTERRUPT_VIRQ);
bellarddb620f42008-06-04 17:02:19 +0000379 intno = cpu_get_pic_interrupt(env);
malc4f213872012-08-27 18:33:12 +0400380 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
381 do_interrupt_x86_hardirq(env, intno, 1);
382 /* ensure that no TB jump will be modified as
383 the program flow was changed */
384 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000385#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000386 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
387 (env->eflags & IF_MASK) &&
388 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
389 int intno;
390 /* FIXME: this should respect TPR */
Blue Swirl77b2bc22012-04-28 19:35:10 +0000391 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
392 0);
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100393 intno = ldl_phys(cpu->as,
394 env->vm_vmcb
395 + offsetof(struct vmcb,
396 control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000397 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000398 do_interrupt_x86_hardirq(env, intno, 1);
Andreas Färber259186a2013-01-17 18:51:17 +0100399 cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000400 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000401#endif
bellarddb620f42008-06-04 17:02:19 +0000402 }
bellard68a79312003-06-30 13:12:32 +0000403 }
bellardce097762004-01-04 23:53:18 +0000404#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000405 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Andreas Färberc356a1b2012-05-04 19:39:23 +0200406 cpu_reset(cpu);
bellard9fddaa02004-05-21 12:59:32 +0000407 }
j_mayer47103572007-03-30 09:38:04 +0000408 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000409 ppc_hw_interrupt(env);
Andreas Färber259186a2013-01-17 18:51:17 +0100410 if (env->pending_interrupts == 0) {
411 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
412 }
blueswir1b5fc09a2008-05-04 06:38:18 +0000413 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000414 }
Michael Walle81ea0e12011-02-17 23:45:02 +0100415#elif defined(TARGET_LM32)
416 if ((interrupt_request & CPU_INTERRUPT_HARD)
417 && (env->ie & IE_IE)) {
418 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100419 cc->do_interrupt(cpu);
Michael Walle81ea0e12011-02-17 23:45:02 +0100420 next_tb = 0;
421 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200422#elif defined(TARGET_MICROBLAZE)
423 if ((interrupt_request & CPU_INTERRUPT_HARD)
424 && (env->sregs[SR_MSR] & MSR_IE)
425 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
426 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
427 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100428 cc->do_interrupt(cpu);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200429 next_tb = 0;
430 }
bellard6af0bf92005-07-02 14:58:51 +0000431#elif defined(TARGET_MIPS)
432 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100433 cpu_mips_hw_interrupts_pending(env)) {
bellard6af0bf92005-07-02 14:58:51 +0000434 /* Raise it */
435 env->exception_index = EXCP_EXT_INTERRUPT;
436 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100437 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000438 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000439 }
Jia Liub6a71ef2012-07-20 15:50:41 +0800440#elif defined(TARGET_OPENRISC)
441 {
442 int idx = -1;
443 if ((interrupt_request & CPU_INTERRUPT_HARD)
444 && (env->sr & SR_IEE)) {
445 idx = EXCP_INT;
446 }
447 if ((interrupt_request & CPU_INTERRUPT_TIMER)
448 && (env->sr & SR_TEE)) {
449 idx = EXCP_TICK;
450 }
451 if (idx >= 0) {
452 env->exception_index = idx;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100453 cc->do_interrupt(cpu);
Jia Liub6a71ef2012-07-20 15:50:41 +0800454 next_tb = 0;
455 }
456 }
bellarde95c8d52004-09-30 22:22:08 +0000457#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300458 if (interrupt_request & CPU_INTERRUPT_HARD) {
459 if (cpu_interrupts_enabled(env) &&
460 env->interrupt_index > 0) {
461 int pil = env->interrupt_index & 0xf;
462 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000463
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300464 if (((type == TT_EXTINT) &&
465 cpu_pil_allowed(env, pil)) ||
466 type != TT_EXTINT) {
467 env->exception_index = env->interrupt_index;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100468 cc->do_interrupt(cpu);
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300469 next_tb = 0;
470 }
471 }
陳韋任e965fc32012-02-06 14:02:55 +0800472 }
bellardb5ff1b32005-11-26 10:38:39 +0000473#elif defined(TARGET_ARM)
474 if (interrupt_request & CPU_INTERRUPT_FIQ
Peter Maydell4cc35612014-02-26 17:20:06 +0000475 && !(env->daif & PSTATE_F)) {
bellardb5ff1b32005-11-26 10:38:39 +0000476 env->exception_index = EXCP_FIQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100477 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000478 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000479 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000480 /* ARMv7-M interrupt return works by loading a magic value
481 into the PC. On real hardware the load causes the
482 return to occur. The qemu implementation performs the
483 jump normally, then does the exception return when the
484 CPU tries to execute code at the magic address.
485 This will cause the magic PC value to be pushed to
Stefan Weila1c72732011-04-28 17:20:38 +0200486 the stack if an interrupt occurred at the wrong time.
pbrook9ee6e8b2007-11-11 00:04:49 +0000487 We avoid this by disabling interrupts when
488 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000489 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000490 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
Peter Maydell4cc35612014-02-26 17:20:06 +0000491 || !(env->daif & PSTATE_I))) {
bellardb5ff1b32005-11-26 10:38:39 +0000492 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100493 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000494 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000495 }
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800496#elif defined(TARGET_UNICORE32)
497 if (interrupt_request & CPU_INTERRUPT_HARD
498 && !(env->uncached_asr & ASR_I)) {
Guan Xuetaod48813d2012-08-10 14:42:23 +0800499 env->exception_index = UC32_EXCP_INTR;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100500 cc->do_interrupt(cpu);
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800501 next_tb = 0;
502 }
bellardfdf9b3e2006-04-27 21:07:38 +0000503#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000504 if (interrupt_request & CPU_INTERRUPT_HARD) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100505 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000506 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000507 }
j_mayereddf68a2007-04-05 07:22:49 +0000508#elif defined(TARGET_ALPHA)
Richard Henderson6a80e082011-04-18 15:09:09 -0700509 {
510 int idx = -1;
511 /* ??? This hard-codes the OSF/1 interrupt levels. */
陳韋任e965fc32012-02-06 14:02:55 +0800512 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
Richard Henderson6a80e082011-04-18 15:09:09 -0700513 case 0 ... 3:
514 if (interrupt_request & CPU_INTERRUPT_HARD) {
515 idx = EXCP_DEV_INTERRUPT;
516 }
517 /* FALLTHRU */
518 case 4:
519 if (interrupt_request & CPU_INTERRUPT_TIMER) {
520 idx = EXCP_CLK_INTERRUPT;
521 }
522 /* FALLTHRU */
523 case 5:
524 if (interrupt_request & CPU_INTERRUPT_SMP) {
525 idx = EXCP_SMP_INTERRUPT;
526 }
527 /* FALLTHRU */
528 case 6:
529 if (interrupt_request & CPU_INTERRUPT_MCHK) {
530 idx = EXCP_MCHK;
531 }
532 }
533 if (idx >= 0) {
534 env->exception_index = idx;
535 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100536 cc->do_interrupt(cpu);
Richard Henderson6a80e082011-04-18 15:09:09 -0700537 next_tb = 0;
538 }
j_mayereddf68a2007-04-05 07:22:49 +0000539 }
thsf1ccf902007-10-08 13:16:14 +0000540#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000541 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100542 && (env->pregs[PR_CCS] & I_FLAG)
543 && !env->locked_irq) {
edgar_igl1b1a38b2008-06-09 23:18:06 +0000544 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100545 cc->do_interrupt(cpu);
edgar_igl1b1a38b2008-06-09 23:18:06 +0000546 next_tb = 0;
547 }
Lars Persson82193142012-06-14 16:23:55 +0200548 if (interrupt_request & CPU_INTERRUPT_NMI) {
549 unsigned int m_flag_archval;
550 if (env->pregs[PR_VR] < 32) {
551 m_flag_archval = M_FLAG_V10;
552 } else {
553 m_flag_archval = M_FLAG_V32;
554 }
555 if ((env->pregs[PR_CCS] & m_flag_archval)) {
556 env->exception_index = EXCP_NMI;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100557 cc->do_interrupt(cpu);
Lars Persson82193142012-06-14 16:23:55 +0200558 next_tb = 0;
559 }
thsf1ccf902007-10-08 13:16:14 +0000560 }
pbrook06338792007-05-23 19:58:11 +0000561#elif defined(TARGET_M68K)
562 if (interrupt_request & CPU_INTERRUPT_HARD
563 && ((env->sr & SR_I) >> SR_I_SHIFT)
564 < env->pending_level) {
565 /* Real hardware gets the interrupt vector via an
566 IACK cycle at this point. Current emulated
567 hardware doesn't rely on this, so we
568 provide/save the vector when the interrupt is
569 first signalled. */
570 env->exception_index = env->pending_vector;
Blue Swirl3c688822011-05-21 07:55:24 +0000571 do_interrupt_m68k_hardirq(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000572 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000573 }
Alexander Graf3110e292011-04-15 17:32:48 +0200574#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
575 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
576 (env->psw.mask & PSW_MASK_EXT)) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100577 cc->do_interrupt(cpu);
Alexander Graf3110e292011-04-15 17:32:48 +0200578 next_tb = 0;
579 }
Max Filippov40643d72011-09-06 03:55:41 +0400580#elif defined(TARGET_XTENSA)
581 if (interrupt_request & CPU_INTERRUPT_HARD) {
582 env->exception_index = EXC_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100583 cc->do_interrupt(cpu);
Max Filippov40643d72011-09-06 03:55:41 +0400584 next_tb = 0;
585 }
bellard68a79312003-06-30 13:12:32 +0000586#endif
Stefan Weilff2712b2011-04-28 17:20:35 +0200587 /* Don't use the cached interrupt_request value,
bellard9d050952006-05-22 22:03:52 +0000588 do_interrupt may have updated the EXITTB flag. */
Andreas Färber259186a2013-01-17 18:51:17 +0100589 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
590 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bellardbf3e8bf2004-02-16 21:58:54 +0000591 /* ensure that no TB jump will be modified as
592 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000593 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000594 }
aurel32be214e62009-03-06 21:48:00 +0000595 }
Andreas Färberfcd7d002012-12-17 08:02:44 +0100596 if (unlikely(cpu->exit_request)) {
597 cpu->exit_request = 0;
aurel32be214e62009-03-06 21:48:00 +0000598 env->exception_index = EXCP_INTERRUPT;
Blue Swirl1162c042011-05-14 12:52:35 +0000599 cpu_loop_exit(env);
bellard3fb2ded2003-06-24 13:22:59 +0000600 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700601 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000602 tb = tb_find_fast(env);
pbrookd5975362008-06-07 20:50:51 +0000603 /* Note: we do it here to avoid a gcc bug on Mac OS X when
604 doing it in tb_find_slow */
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700605 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
pbrookd5975362008-06-07 20:50:51 +0000606 /* as some TB could have been invalidated because
607 of memory exceptions while generating the code, we
608 must recompute the hash index here */
609 next_tb = 0;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700610 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000611 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100612 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
613 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
614 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
615 }
bellard8a40a182005-11-20 10:35:40 +0000616 /* see if we can patch the calling TB. When the TB
617 spans two pages, we cannot safely do a direct
618 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100619 if (next_tb != 0 && tb->page_addr[1] == -1) {
Peter Maydell09800112013-02-22 18:10:00 +0000620 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
621 next_tb & TB_EXIT_MASK, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000622 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700623 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
malc55e8b852008-11-04 14:18:13 +0000624
625 /* cpu_interrupt might be called while translating the
626 TB, but before it is linked into a potentially
627 infinite loop and becomes env->current_tb. Avoid
628 starting execution if there is a pending interrupt. */
Andreas Färberd77953b2013-01-16 19:29:31 +0100629 cpu->current_tb = tb;
Jan Kiszkab0052d12010-06-25 16:56:50 +0200630 barrier();
Andreas Färberfcd7d002012-12-17 08:02:44 +0100631 if (likely(!cpu->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000632 tc_ptr = tb->tc_ptr;
陳韋任e965fc32012-02-06 14:02:55 +0800633 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000634 next_tb = cpu_tb_exec(cpu, tc_ptr);
Peter Maydell378df4b2013-02-22 18:10:03 +0000635 switch (next_tb & TB_EXIT_MASK) {
636 case TB_EXIT_REQUESTED:
637 /* Something asked us to stop executing
638 * chained TBs; just continue round the main
639 * loop. Whatever requested the exit will also
640 * have set something else (eg exit_request or
641 * interrupt_request) which we will handle
642 * next time around the loop.
643 */
644 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
645 next_tb = 0;
646 break;
647 case TB_EXIT_ICOUNT_EXPIRED:
648 {
thsbf20dc02008-06-30 17:22:19 +0000649 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000650 int insns_left;
Peter Maydell09800112013-02-22 18:10:00 +0000651 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
pbrook2e70f6e2008-06-29 01:03:05 +0000652 insns_left = env->icount_decr.u32;
653 if (env->icount_extra && insns_left >= 0) {
654 /* Refill decrementer and continue execution. */
655 env->icount_extra += insns_left;
656 if (env->icount_extra > 0xffff) {
657 insns_left = 0xffff;
658 } else {
659 insns_left = env->icount_extra;
660 }
661 env->icount_extra -= insns_left;
662 env->icount_decr.u16.low = insns_left;
663 } else {
664 if (insns_left > 0) {
665 /* Execute remaining instructions. */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000666 cpu_exec_nocache(env, insns_left, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000667 }
668 env->exception_index = EXCP_INTERRUPT;
669 next_tb = 0;
Blue Swirl1162c042011-05-14 12:52:35 +0000670 cpu_loop_exit(env);
pbrook2e70f6e2008-06-29 01:03:05 +0000671 }
Peter Maydell378df4b2013-02-22 18:10:03 +0000672 break;
673 }
674 default:
675 break;
pbrook2e70f6e2008-06-29 01:03:05 +0000676 }
677 }
Andreas Färberd77953b2013-01-16 19:29:31 +0100678 cpu->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000679 /* reset soft MMU for next block (it can currently
680 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000681 } /* for(;;) */
Jan Kiszka0d101932011-07-02 09:50:51 +0200682 } else {
683 /* Reload env after longjmp - the compiler may have smashed all
684 * local variables as longjmp is marked 'noreturn'. */
Andreas Färber4917cf42013-05-27 05:17:50 +0200685 cpu = current_cpu;
686 env = cpu->env_ptr;
Juergen Lock6c78f292013-10-03 16:09:37 +0200687#if !(defined(CONFIG_USER_ONLY) && \
688 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
689 cc = CPU_GET_CLASS(cpu);
690#endif
Andreas Färber693fa552013-12-24 03:18:12 +0100691#ifdef TARGET_I386
692 x86_cpu = X86_CPU(cpu);
693#endif
bellard7d132992003-03-06 23:23:54 +0000694 }
bellard3fb2ded2003-06-24 13:22:59 +0000695 } /* for(;;) */
696
bellard7d132992003-03-06 23:23:54 +0000697
bellarde4533c72003-06-15 19:51:39 +0000698#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000699 /* restore flags in standard format */
Blue Swirle694d4e2011-05-16 19:38:48 +0000700 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
liguang80cf2c82013-05-28 16:21:08 +0800701 | (env->df & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000702#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000703 /* XXX: Save/restore host fpu exception state?. */
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800704#elif defined(TARGET_UNICORE32)
bellard93ac68b2003-09-30 20:57:29 +0000705#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000706#elif defined(TARGET_PPC)
Michael Walle81ea0e12011-02-17 23:45:02 +0100707#elif defined(TARGET_LM32)
pbrooke6e59062006-10-22 00:18:54 +0000708#elif defined(TARGET_M68K)
709 cpu_m68k_flush_flags(env, env->cc_op);
710 env->cc_op = CC_OP_FLAGS;
711 env->sr = (env->sr & 0xffe0)
712 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200713#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000714#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400715#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800716#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000717#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000718#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000719#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100720#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400721#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000722 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000723#else
724#error unsupported target CPU
725#endif
pbrook1057eaa2007-02-04 13:37:44 +0000726
Andreas Färber4917cf42013-05-27 05:17:50 +0200727 /* fail safe : never use current_cpu outside cpu_exec() */
728 current_cpu = NULL;
bellard7d132992003-03-06 23:23:54 +0000729 return ret;
730}