blob: 634f1ba875450eeb2b02da7a09f2b4d002bc67b1 [file] [log] [blame]
bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
3 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
bellard7d132992003-03-06 23:23:54 +000019 */
bellarde4533c72003-06-15 19:51:39 +000020#include "config.h"
bellard93ac68b2003-09-30 20:57:29 +000021#include "exec.h"
bellard956034d2003-04-29 20:40:53 +000022#include "disas.h"
bellard7d132992003-03-06 23:23:54 +000023
bellardfbf9eeb2004-04-25 21:21:33 +000024#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
bellard36bdbe52003-11-19 22:12:02 +000038int tb_invalidated_flag;
39
bellarddc990652003-03-19 00:00:28 +000040//#define DEBUG_EXEC
bellard9de5e442003-03-23 16:49:39 +000041//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000042
pbrooke6e59062006-10-22 00:18:54 +000043#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
bellarde4533c72003-06-15 19:51:39 +000044/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
pbrooke6e59062006-10-22 00:18:54 +000050#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
bellard34751872005-07-02 14:31:34 +000051#define reg_T2
52#endif
bellarde4533c72003-06-15 19:51:39 +000053
bellardfbf9eeb2004-04-25 21:21:33 +000054/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
bellard8a40a182005-11-20 10:35:40 +000076
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
bellard15388002005-12-19 01:42:32 +0000129 tb_invalidated_flag = 1;
bellard8a40a182005-11-20 10:35:40 +0000130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
bellard8a40a182005-11-20 10:35:40 +0000147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151}
152
153static inline TranslationBlock *tb_find_fast(void)
154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162#if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167#elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
bellardb5ff1b32005-11-26 10:38:39 +0000169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
pbrook40f137e2006-02-20 00:33:36 +0000172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
bellard8a40a182005-11-20 10:35:40 +0000174 cs_base = 0;
175 pc = env->regs[15];
176#elif defined(TARGET_SPARC)
177#ifdef TARGET_SPARC64
bellarda80dde02006-06-26 19:53:29 +0000178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
bellard8a40a182005-11-20 10:35:40 +0000181#else
bellarda80dde02006-06-26 19:53:29 +0000182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
bellard8a40a182005-11-20 10:35:40 +0000185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
pbrook56b19402006-03-11 16:23:39 +0000194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
bellardcc9442b2005-11-26 18:43:28 +0000195 cs_base = 0;
bellard8a40a182005-11-20 10:35:40 +0000196 pc = env->PC;
pbrooke6e59062006-10-22 00:18:54 +0000197#elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
bellardfdf9b3e2006-04-27 21:07:38 +0000201#elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
bellard8a40a182005-11-20 10:35:40 +0000205#else
206#error unsupported CPU
207#endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
bellard15388002005-12-19 01:42:32 +0000212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
bellard8a40a182005-11-20 10:35:40 +0000220 }
221 return tb;
222}
223
224
bellard7d132992003-03-06 23:23:54 +0000225/* main execution loop */
226
bellarde4533c72003-06-15 19:51:39 +0000227int cpu_exec(CPUState *env1)
bellard7d132992003-03-06 23:23:54 +0000228{
pbrook1057eaa2007-02-04 13:37:44 +0000229#define DECLARE_HOST_REGS 1
230#include "hostregs_helper.h"
231#if defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000232#if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
234#endif
235#endif
bellardfdbb4692006-06-14 17:32:25 +0000236#if defined(__sparc__) && !defined(HOST_SOLARIS)
thsb49d07b2007-02-02 03:57:09 +0000237 int saved_i7;
238 target_ulong tmp_T0;
bellard8c6939c2003-06-09 15:28:00 +0000239#endif
bellard8a40a182005-11-20 10:35:40 +0000240 int ret, interrupt_request;
bellard7d132992003-03-06 23:23:54 +0000241 void (*gen_func)(void);
bellard8a40a182005-11-20 10:35:40 +0000242 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000243 uint8_t *tc_ptr;
bellard8c6939c2003-06-09 15:28:00 +0000244
bellard5a1e3cf2005-11-23 21:02:53 +0000245#if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
252 } else {
253 return EXCP_HALTED;
254 }
255 }
bellarde80e1cc2005-11-23 22:05:28 +0000256#elif defined(TARGET_PPC)
bellard50443c92005-11-26 20:15:14 +0000257 if (env1->halted) {
bellarde80e1cc2005-11-23 22:05:28 +0000258 if (env1->msr[MSR_EE] &&
259 (env1->interrupt_request &
260 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
bellard50443c92005-11-26 20:15:14 +0000261 env1->halted = 0;
bellarde80e1cc2005-11-23 22:05:28 +0000262 } else {
263 return EXCP_HALTED;
264 }
265 }
bellardba3c64f2005-12-05 20:31:52 +0000266#elif defined(TARGET_SPARC)
267 if (env1->halted) {
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->psret != 0)) {
270 env1->halted = 0;
271 } else {
272 return EXCP_HALTED;
273 }
274 }
bellard9332f9d2005-11-26 10:46:39 +0000275#elif defined(TARGET_ARM)
276 if (env1->halted) {
277 /* An interrupt wakes the CPU even if the I and F CPSR bits are
278 set. */
279 if (env1->interrupt_request
280 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
281 env1->halted = 0;
282 } else {
283 return EXCP_HALTED;
284 }
285 }
bellard6810e152005-12-05 19:59:05 +0000286#elif defined(TARGET_MIPS)
287 if (env1->halted) {
288 if (env1->interrupt_request &
289 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
290 env1->halted = 0;
291 } else {
292 return EXCP_HALTED;
293 }
294 }
bellard5a1e3cf2005-11-23 21:02:53 +0000295#endif
296
bellard6a00d602005-11-21 23:25:50 +0000297 cpu_single_env = env1;
298
bellard7d132992003-03-06 23:23:54 +0000299 /* first we save global registers */
pbrook1057eaa2007-02-04 13:37:44 +0000300#define SAVE_HOST_REGS 1
301#include "hostregs_helper.h"
bellardc27004e2005-01-03 23:35:10 +0000302 env = env1;
bellardfdbb4692006-06-14 17:32:25 +0000303#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellarde4533c72003-06-15 19:51:39 +0000304 /* we also save i7 because longjmp may not restore it */
305 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
306#endif
307
308#if defined(TARGET_I386)
bellard0d1a29f2004-10-12 22:01:28 +0000309 env_to_regs();
bellard9de5e442003-03-23 16:49:39 +0000310 /* put eflags in CPU temporary format */
bellardfc2b4c42003-03-29 16:52:44 +0000311 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
312 DF = 1 - (2 * ((env->eflags >> 10) & 1));
bellard9de5e442003-03-23 16:49:39 +0000313 CC_OP = CC_OP_EFLAGS;
bellardfc2b4c42003-03-29 16:52:44 +0000314 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000315#elif defined(TARGET_ARM)
bellard93ac68b2003-09-30 20:57:29 +0000316#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000317#if defined(reg_REGWPTR)
318 saved_regwptr = REGWPTR;
319#endif
bellard67867302003-11-23 17:05:30 +0000320#elif defined(TARGET_PPC)
pbrooke6e59062006-10-22 00:18:54 +0000321#elif defined(TARGET_M68K)
322 env->cc_op = CC_OP_FLAGS;
323 env->cc_dest = env->sr & 0xf;
324 env->cc_x = (env->sr >> 4) & 1;
bellard6af0bf92005-07-02 14:58:51 +0000325#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000326#elif defined(TARGET_SH4)
327 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000328#else
329#error unsupported target CPU
330#endif
bellard3fb2ded2003-06-24 13:22:59 +0000331 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000332
bellard7d132992003-03-06 23:23:54 +0000333 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000334 for(;;) {
335 if (setjmp(env->jmp_env) == 0) {
bellardee8b7022004-02-03 23:35:10 +0000336 env->current_tb = NULL;
bellard3fb2ded2003-06-24 13:22:59 +0000337 /* if an exception is pending, we execute it here */
338 if (env->exception_index >= 0) {
339 if (env->exception_index >= EXCP_INTERRUPT) {
340 /* exit request from the cpu execution loop */
341 ret = env->exception_index;
342 break;
343 } else if (env->user_mode_only) {
344 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000345 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000346 loop */
bellard83479e72003-06-25 16:12:37 +0000347#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000348 do_interrupt_user(env->exception_index,
349 env->exception_is_int,
350 env->error_code,
351 env->exception_next_eip);
bellard83479e72003-06-25 16:12:37 +0000352#endif
bellard3fb2ded2003-06-24 13:22:59 +0000353 ret = env->exception_index;
354 break;
355 } else {
bellard83479e72003-06-25 16:12:37 +0000356#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000357 /* simulate a real cpu exception. On i386, it can
358 trigger new exceptions, but we do not handle
359 double or triple faults yet. */
360 do_interrupt(env->exception_index,
361 env->exception_is_int,
362 env->error_code,
bellardd05e66d2003-08-20 21:34:35 +0000363 env->exception_next_eip, 0);
bellardce097762004-01-04 23:53:18 +0000364#elif defined(TARGET_PPC)
365 do_interrupt(env);
bellard6af0bf92005-07-02 14:58:51 +0000366#elif defined(TARGET_MIPS)
367 do_interrupt(env);
bellarde95c8d52004-09-30 22:22:08 +0000368#elif defined(TARGET_SPARC)
bellard1a0c3292005-02-13 19:02:07 +0000369 do_interrupt(env->exception_index);
bellardb5ff1b32005-11-26 10:38:39 +0000370#elif defined(TARGET_ARM)
371 do_interrupt(env);
bellardfdf9b3e2006-04-27 21:07:38 +0000372#elif defined(TARGET_SH4)
373 do_interrupt(env);
bellard83479e72003-06-25 16:12:37 +0000374#endif
bellard3fb2ded2003-06-24 13:22:59 +0000375 }
376 env->exception_index = -1;
bellard9df217a2005-02-10 22:05:51 +0000377 }
378#ifdef USE_KQEMU
379 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
380 int ret;
381 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
382 ret = kqemu_cpu_exec(env);
383 /* put eflags in CPU temporary format */
384 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
385 DF = 1 - (2 * ((env->eflags >> 10) & 1));
386 CC_OP = CC_OP_EFLAGS;
387 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
388 if (ret == 1) {
389 /* exception */
390 longjmp(env->jmp_env, 1);
391 } else if (ret == 2) {
392 /* softmmu execution needed */
393 } else {
394 if (env->interrupt_request != 0) {
395 /* hardware interrupt will be executed just after */
396 } else {
397 /* otherwise, we restart */
398 longjmp(env->jmp_env, 1);
399 }
400 }
bellard9de5e442003-03-23 16:49:39 +0000401 }
bellard9df217a2005-02-10 22:05:51 +0000402#endif
403
bellard3fb2ded2003-06-24 13:22:59 +0000404 T0 = 0; /* force lookup of first TB */
405 for(;;) {
bellardfdbb4692006-06-14 17:32:25 +0000406#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard3fb2ded2003-06-24 13:22:59 +0000407 /* g1 can be modified by some libc? functions */
408 tmp_T0 = T0;
409#endif
bellard68a79312003-06-30 13:12:32 +0000410 interrupt_request = env->interrupt_request;
bellard2e255c62003-08-21 23:25:21 +0000411 if (__builtin_expect(interrupt_request, 0)) {
pbrook6658ffb2007-03-16 23:58:11 +0000412 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
413 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
414 env->exception_index = EXCP_DEBUG;
415 cpu_loop_exit();
416 }
bellard68a79312003-06-30 13:12:32 +0000417#if defined(TARGET_I386)
bellard3b21e032006-09-24 18:41:56 +0000418 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
419 !(env->hflags & HF_SMM_MASK)) {
420 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
421 do_smm_enter();
422#if defined(__sparc__) && !defined(HOST_SOLARIS)
423 tmp_T0 = 0;
424#else
425 T0 = 0;
426#endif
427 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
bellard3f337312003-08-20 23:02:09 +0000428 (env->eflags & IF_MASK) &&
429 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
bellard68a79312003-06-30 13:12:32 +0000430 int intno;
bellardfbf9eeb2004-04-25 21:21:33 +0000431 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellarda541f292004-04-12 20:39:29 +0000432 intno = cpu_get_pic_interrupt(env);
bellardf193c792004-03-21 17:06:25 +0000433 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard68a79312003-06-30 13:12:32 +0000434 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
435 }
bellardd05e66d2003-08-20 21:34:35 +0000436 do_interrupt(intno, 0, 0, 0, 1);
bellard907a5b22003-06-30 23:18:22 +0000437 /* ensure that no TB jump will be modified as
438 the program flow was changed */
bellardfdbb4692006-06-14 17:32:25 +0000439#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard907a5b22003-06-30 23:18:22 +0000440 tmp_T0 = 0;
441#else
442 T0 = 0;
443#endif
bellard68a79312003-06-30 13:12:32 +0000444 }
bellardce097762004-01-04 23:53:18 +0000445#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000446#if 0
447 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
448 cpu_ppc_reset(env);
449 }
450#endif
451 if (msr_ee != 0) {
bellard8a40a182005-11-20 10:35:40 +0000452 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
bellard9fddaa02004-05-21 12:59:32 +0000453 /* Raise it */
454 env->exception_index = EXCP_EXTERNAL;
455 env->error_code = 0;
bellardce097762004-01-04 23:53:18 +0000456 do_interrupt(env);
bellard8a40a182005-11-20 10:35:40 +0000457 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellardfdbb4692006-06-14 17:32:25 +0000458#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000459 tmp_T0 = 0;
460#else
461 T0 = 0;
462#endif
463 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
464 /* Raise it */
465 env->exception_index = EXCP_DECR;
466 env->error_code = 0;
467 do_interrupt(env);
bellard9fddaa02004-05-21 12:59:32 +0000468 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
bellardfdbb4692006-06-14 17:32:25 +0000469#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000470 tmp_T0 = 0;
471#else
472 T0 = 0;
473#endif
474 }
bellardce097762004-01-04 23:53:18 +0000475 }
bellard6af0bf92005-07-02 14:58:51 +0000476#elif defined(TARGET_MIPS)
477 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
478 (env->CP0_Status & (1 << CP0St_IE)) &&
bellard7ebab692005-08-21 09:43:38 +0000479 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
bellard6af0bf92005-07-02 14:58:51 +0000480 !(env->hflags & MIPS_HFLAG_EXL) &&
481 !(env->hflags & MIPS_HFLAG_ERL) &&
482 !(env->hflags & MIPS_HFLAG_DM)) {
483 /* Raise it */
484 env->exception_index = EXCP_EXT_INTERRUPT;
485 env->error_code = 0;
486 do_interrupt(env);
bellardfdbb4692006-06-14 17:32:25 +0000487#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000488 tmp_T0 = 0;
489#else
490 T0 = 0;
491#endif
bellard6af0bf92005-07-02 14:58:51 +0000492 }
bellarde95c8d52004-09-30 22:22:08 +0000493#elif defined(TARGET_SPARC)
bellard66321a12005-04-06 20:47:48 +0000494 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
495 (env->psret != 0)) {
496 int pil = env->interrupt_index & 15;
497 int type = env->interrupt_index & 0xf0;
498
499 if (((type == TT_EXTINT) &&
500 (pil == 15 || pil > env->psrpil)) ||
501 type != TT_EXTINT) {
502 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
503 do_interrupt(env->interrupt_index);
504 env->interrupt_index = 0;
bellardfdbb4692006-06-14 17:32:25 +0000505#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8a40a182005-11-20 10:35:40 +0000506 tmp_T0 = 0;
507#else
508 T0 = 0;
509#endif
bellard66321a12005-04-06 20:47:48 +0000510 }
bellarde95c8d52004-09-30 22:22:08 +0000511 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
512 //do_interrupt(0, 0, 0, 0, 0);
513 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
bellardba3c64f2005-12-05 20:31:52 +0000514 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
bellarddf52b002006-09-20 20:30:57 +0000515 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
516 env->halted = 1;
517 env->exception_index = EXCP_HLT;
518 cpu_loop_exit();
bellardba3c64f2005-12-05 20:31:52 +0000519 }
bellardb5ff1b32005-11-26 10:38:39 +0000520#elif defined(TARGET_ARM)
521 if (interrupt_request & CPU_INTERRUPT_FIQ
522 && !(env->uncached_cpsr & CPSR_F)) {
523 env->exception_index = EXCP_FIQ;
524 do_interrupt(env);
525 }
526 if (interrupt_request & CPU_INTERRUPT_HARD
527 && !(env->uncached_cpsr & CPSR_I)) {
528 env->exception_index = EXCP_IRQ;
529 do_interrupt(env);
530 }
bellardfdf9b3e2006-04-27 21:07:38 +0000531#elif defined(TARGET_SH4)
532 /* XXXXX */
bellard68a79312003-06-30 13:12:32 +0000533#endif
bellard9d050952006-05-22 22:03:52 +0000534 /* Don't use the cached interupt_request value,
535 do_interrupt may have updated the EXITTB flag. */
bellardb5ff1b32005-11-26 10:38:39 +0000536 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bellardbf3e8bf2004-02-16 21:58:54 +0000537 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
538 /* ensure that no TB jump will be modified as
539 the program flow was changed */
bellardfdbb4692006-06-14 17:32:25 +0000540#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellardbf3e8bf2004-02-16 21:58:54 +0000541 tmp_T0 = 0;
542#else
543 T0 = 0;
544#endif
545 }
bellard68a79312003-06-30 13:12:32 +0000546 if (interrupt_request & CPU_INTERRUPT_EXIT) {
547 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
548 env->exception_index = EXCP_INTERRUPT;
549 cpu_loop_exit();
550 }
bellard3fb2ded2003-06-24 13:22:59 +0000551 }
552#ifdef DEBUG_EXEC
bellardb5ff1b32005-11-26 10:38:39 +0000553 if ((loglevel & CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000554#if defined(TARGET_I386)
555 /* restore flags in standard format */
bellardfc9f7152005-04-26 19:33:35 +0000556#ifdef reg_EAX
bellard3fb2ded2003-06-24 13:22:59 +0000557 env->regs[R_EAX] = EAX;
bellardfc9f7152005-04-26 19:33:35 +0000558#endif
559#ifdef reg_EBX
bellard3fb2ded2003-06-24 13:22:59 +0000560 env->regs[R_EBX] = EBX;
bellardfc9f7152005-04-26 19:33:35 +0000561#endif
562#ifdef reg_ECX
bellard3fb2ded2003-06-24 13:22:59 +0000563 env->regs[R_ECX] = ECX;
bellardfc9f7152005-04-26 19:33:35 +0000564#endif
565#ifdef reg_EDX
bellard3fb2ded2003-06-24 13:22:59 +0000566 env->regs[R_EDX] = EDX;
bellardfc9f7152005-04-26 19:33:35 +0000567#endif
568#ifdef reg_ESI
bellard3fb2ded2003-06-24 13:22:59 +0000569 env->regs[R_ESI] = ESI;
bellardfc9f7152005-04-26 19:33:35 +0000570#endif
571#ifdef reg_EDI
bellard3fb2ded2003-06-24 13:22:59 +0000572 env->regs[R_EDI] = EDI;
bellardfc9f7152005-04-26 19:33:35 +0000573#endif
574#ifdef reg_EBP
bellard3fb2ded2003-06-24 13:22:59 +0000575 env->regs[R_EBP] = EBP;
bellardfc9f7152005-04-26 19:33:35 +0000576#endif
577#ifdef reg_ESP
bellard3fb2ded2003-06-24 13:22:59 +0000578 env->regs[R_ESP] = ESP;
bellardfc9f7152005-04-26 19:33:35 +0000579#endif
bellard3fb2ded2003-06-24 13:22:59 +0000580 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard7fe48482004-10-09 18:08:01 +0000581 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000582 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000583#elif defined(TARGET_ARM)
bellard7fe48482004-10-09 18:08:01 +0000584 cpu_dump_state(env, logfile, fprintf, 0);
bellard93ac68b2003-09-30 20:57:29 +0000585#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000586 REGWPTR = env->regbase + (env->cwp * 16);
587 env->regwptr = REGWPTR;
588 cpu_dump_state(env, logfile, fprintf, 0);
bellard67867302003-11-23 17:05:30 +0000589#elif defined(TARGET_PPC)
bellard7fe48482004-10-09 18:08:01 +0000590 cpu_dump_state(env, logfile, fprintf, 0);
pbrooke6e59062006-10-22 00:18:54 +0000591#elif defined(TARGET_M68K)
592 cpu_m68k_flush_flags(env, env->cc_op);
593 env->cc_op = CC_OP_FLAGS;
594 env->sr = (env->sr & 0xffe0)
595 | env->cc_dest | (env->cc_x << 4);
596 cpu_dump_state(env, logfile, fprintf, 0);
bellard6af0bf92005-07-02 14:58:51 +0000597#elif defined(TARGET_MIPS)
598 cpu_dump_state(env, logfile, fprintf, 0);
bellardfdf9b3e2006-04-27 21:07:38 +0000599#elif defined(TARGET_SH4)
600 cpu_dump_state(env, logfile, fprintf, 0);
bellarde4533c72003-06-15 19:51:39 +0000601#else
602#error unsupported target CPU
603#endif
bellard3fb2ded2003-06-24 13:22:59 +0000604 }
bellard7d132992003-03-06 23:23:54 +0000605#endif
bellard8a40a182005-11-20 10:35:40 +0000606 tb = tb_find_fast();
bellard9d27abd2003-05-10 13:13:54 +0000607#ifdef DEBUG_EXEC
bellardc1135f62005-01-30 22:41:54 +0000608 if ((loglevel & CPU_LOG_EXEC)) {
bellardc27004e2005-01-03 23:35:10 +0000609 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
610 (long)tb->tc_ptr, tb->pc,
611 lookup_symbol(tb->pc));
bellard3fb2ded2003-06-24 13:22:59 +0000612 }
bellard9d27abd2003-05-10 13:13:54 +0000613#endif
bellardfdbb4692006-06-14 17:32:25 +0000614#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard3fb2ded2003-06-24 13:22:59 +0000615 T0 = tmp_T0;
bellard8c6939c2003-06-09 15:28:00 +0000616#endif
bellard8a40a182005-11-20 10:35:40 +0000617 /* see if we can patch the calling TB. When the TB
618 spans two pages, we cannot safely do a direct
619 jump. */
bellardc27004e2005-01-03 23:35:10 +0000620 {
bellard8a40a182005-11-20 10:35:40 +0000621 if (T0 != 0 &&
bellardf32fc642006-02-08 22:43:39 +0000622#if USE_KQEMU
623 (env->kqemu_enabled != 2) &&
624#endif
bellard8a40a182005-11-20 10:35:40 +0000625 tb->page_addr[1] == -1
bellardbf3e8bf2004-02-16 21:58:54 +0000626#if defined(TARGET_I386) && defined(USE_CODE_COPY)
627 && (tb->cflags & CF_CODE_COPY) ==
628 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
629#endif
630 ) {
bellard3fb2ded2003-06-24 13:22:59 +0000631 spin_lock(&tb_lock);
bellardc27004e2005-01-03 23:35:10 +0000632 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
bellard97eb5b12004-02-25 23:19:55 +0000633#if defined(USE_CODE_COPY)
634 /* propagates the FP use info */
635 ((TranslationBlock *)(T0 & ~3))->cflags |=
636 (tb->cflags & CF_FP_USED);
637#endif
bellard3fb2ded2003-06-24 13:22:59 +0000638 spin_unlock(&tb_lock);
639 }
bellardc27004e2005-01-03 23:35:10 +0000640 }
bellard3fb2ded2003-06-24 13:22:59 +0000641 tc_ptr = tb->tc_ptr;
bellard83479e72003-06-25 16:12:37 +0000642 env->current_tb = tb;
bellard3fb2ded2003-06-24 13:22:59 +0000643 /* execute the generated code */
644 gen_func = (void *)tc_ptr;
645#if defined(__sparc__)
646 __asm__ __volatile__("call %0\n\t"
647 "mov %%o7,%%i0"
648 : /* no outputs */
649 : "r" (gen_func)
bellardfdbb4692006-06-14 17:32:25 +0000650 : "i0", "i1", "i2", "i3", "i4", "i5",
thsfaab7592007-03-19 20:39:49 +0000651 "o0", "o1", "o2", "o3", "o4", "o5",
bellardfdbb4692006-06-14 17:32:25 +0000652 "l0", "l1", "l2", "l3", "l4", "l5",
653 "l6", "l7");
bellard3fb2ded2003-06-24 13:22:59 +0000654#elif defined(__arm__)
655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
657 "exec_loop:\n\t"
658 : /* no outputs */
659 : "r" (gen_func)
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bellardbf3e8bf2004-02-16 21:58:54 +0000661#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
662{
663 if (!(tb->cflags & CF_CODE_COPY)) {
bellard97eb5b12004-02-25 23:19:55 +0000664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
666 }
bellardbf3e8bf2004-02-16 21:58:54 +0000667 gen_func();
668 } else {
bellard97eb5b12004-02-25 23:19:55 +0000669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
671 }
bellardbf3e8bf2004-02-16 21:58:54 +0000672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
676 "\n"
677 "debug1:\n"
678 " pushl %%ebp\n"
679 " fs movl %10, %9\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
683 " pushl %%eax\n"
684 " popf\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
694 " fs jmp *%9\n"
695 "exec_loop:\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
705 " pushf\n"
706 " popl %%eax\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
709 " shrl $9, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
712 " movl $1, %%eax\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
716 " popl %%ebp\n"
717 :
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
728 "a" (gen_func),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
731 : "%ecx", "%edx"
732 );
733 }
734}
bellardb8076a72005-04-07 22:20:31 +0000735#elif defined(__ia64)
736 struct fptr {
737 void *ip;
738 void *gp;
739 } fp;
740
741 fp.ip = tc_ptr;
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
bellard3fb2ded2003-06-24 13:22:59 +0000744#else
745 gen_func();
746#endif
bellard83479e72003-06-25 16:12:37 +0000747 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
bellard3f337312003-08-20 23:02:09 +0000751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
bellard4cbf74b2003-08-10 21:48:43 +0000753 /* do not allow linking to another block */
754 T0 = 0;
755 }
756#endif
bellardf32fc642006-02-08 22:43:39 +0000757#if defined(USE_KQEMU)
758#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
759 if (kqemu_is_ok(env) &&
760 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
761 cpu_loop_exit();
762 }
763#endif
bellard3fb2ded2003-06-24 13:22:59 +0000764 }
765 } else {
bellard0d1a29f2004-10-12 22:01:28 +0000766 env_to_regs();
bellard7d132992003-03-06 23:23:54 +0000767 }
bellard3fb2ded2003-06-24 13:22:59 +0000768 } /* for(;;) */
769
bellard7d132992003-03-06 23:23:54 +0000770
bellarde4533c72003-06-15 19:51:39 +0000771#if defined(TARGET_I386)
bellard97eb5b12004-02-25 23:19:55 +0000772#if defined(USE_CODE_COPY)
773 if (env->native_fp_regs) {
774 save_native_fp_state(env);
775 }
776#endif
bellard9de5e442003-03-23 16:49:39 +0000777 /* restore flags in standard format */
bellardfc2b4c42003-03-29 16:52:44 +0000778 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000779#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000780 /* XXX: Save/restore host fpu exception state?. */
bellard93ac68b2003-09-30 20:57:29 +0000781#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000782#if defined(reg_REGWPTR)
783 REGWPTR = saved_regwptr;
784#endif
bellard67867302003-11-23 17:05:30 +0000785#elif defined(TARGET_PPC)
pbrooke6e59062006-10-22 00:18:54 +0000786#elif defined(TARGET_M68K)
787 cpu_m68k_flush_flags(env, env->cc_op);
788 env->cc_op = CC_OP_FLAGS;
789 env->sr = (env->sr & 0xffe0)
790 | env->cc_dest | (env->cc_x << 4);
bellard6af0bf92005-07-02 14:58:51 +0000791#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000792#elif defined(TARGET_SH4)
793 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000794#else
795#error unsupported target CPU
796#endif
pbrook1057eaa2007-02-04 13:37:44 +0000797
798 /* restore global registers */
bellardfdbb4692006-06-14 17:32:25 +0000799#if defined(__sparc__) && !defined(HOST_SOLARIS)
bellard8c6939c2003-06-09 15:28:00 +0000800 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
801#endif
pbrook1057eaa2007-02-04 13:37:44 +0000802#include "hostregs_helper.h"
803
bellard6a00d602005-11-21 23:25:50 +0000804 /* fail safe : never use cpu_single_env outside cpu_exec() */
805 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000806 return ret;
807}
bellard6dbad632003-03-16 18:05:05 +0000808
bellardfbf9eeb2004-04-25 21:21:33 +0000809/* must only be called from the generated code as an exception can be
810 generated */
811void tb_invalidate_page_range(target_ulong start, target_ulong end)
812{
bellarddc5d0b32004-06-22 18:43:30 +0000813 /* XXX: cannot enable it yet because it yields to MMU exception
814 where NIP != read address on PowerPC */
815#if 0
bellardfbf9eeb2004-04-25 21:21:33 +0000816 target_ulong phys_addr;
817 phys_addr = get_phys_addr_code(env, start);
818 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
bellarddc5d0b32004-06-22 18:43:30 +0000819#endif
bellardfbf9eeb2004-04-25 21:21:33 +0000820}
821
bellard1a18c712003-10-30 01:07:51 +0000822#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
bellarde4533c72003-06-15 19:51:39 +0000823
bellard6dbad632003-03-16 18:05:05 +0000824void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
825{
826 CPUX86State *saved_env;
827
828 saved_env = env;
829 env = s;
bellarda412ac52003-07-26 18:01:40 +0000830 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
bellarda513fe12003-05-27 23:29:48 +0000831 selector &= 0xffff;
bellard2e255c62003-08-21 23:25:21 +0000832 cpu_x86_load_seg_cache(env, seg_reg, selector,
bellardc27004e2005-01-03 23:35:10 +0000833 (selector << 4), 0xffff, 0);
bellarda513fe12003-05-27 23:29:48 +0000834 } else {
bellardb453b702004-01-04 15:45:21 +0000835 load_seg(seg_reg, selector);
bellarda513fe12003-05-27 23:29:48 +0000836 }
bellard6dbad632003-03-16 18:05:05 +0000837 env = saved_env;
838}
bellard9de5e442003-03-23 16:49:39 +0000839
bellardd0a1ffc2003-05-29 20:04:28 +0000840void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
841{
842 CPUX86State *saved_env;
843
844 saved_env = env;
845 env = s;
846
bellardc27004e2005-01-03 23:35:10 +0000847 helper_fsave((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000848
849 env = saved_env;
850}
851
852void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
853{
854 CPUX86State *saved_env;
855
856 saved_env = env;
857 env = s;
858
bellardc27004e2005-01-03 23:35:10 +0000859 helper_frstor((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000860
861 env = saved_env;
862}
863
bellarde4533c72003-06-15 19:51:39 +0000864#endif /* TARGET_I386 */
865
bellard67b915a2004-03-31 23:37:16 +0000866#if !defined(CONFIG_SOFTMMU)
867
bellard3fb2ded2003-06-24 13:22:59 +0000868#if defined(TARGET_I386)
869
bellardb56dad12003-05-08 15:38:04 +0000870/* 'pc' is the host PC at which the exception was raised. 'address' is
bellardfd6ce8f2003-05-14 19:00:11 +0000871 the effective address of the memory exception. 'is_write' is 1 if a
872 write caused the exception and otherwise 0'. 'old_set' is the
873 signal set which should be restored */
bellard2b413142003-05-14 23:01:10 +0000874static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000875 int is_write, sigset_t *old_set,
876 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000877{
bellarda513fe12003-05-27 23:29:48 +0000878 TranslationBlock *tb;
879 int ret;
bellard68a79312003-06-30 13:12:32 +0000880
bellard83479e72003-06-25 16:12:37 +0000881 if (cpu_single_env)
882 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellardfd6ce8f2003-05-14 19:00:11 +0000883#if defined(DEBUG_SIGNAL)
bellardbf3e8bf2004-02-16 21:58:54 +0000884 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
885 pc, address, is_write, *(unsigned long *)old_set);
bellard9de5e442003-03-23 16:49:39 +0000886#endif
bellard25eb4482003-05-14 21:50:54 +0000887 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000888 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellardfd6ce8f2003-05-14 19:00:11 +0000889 return 1;
890 }
bellardfbf9eeb2004-04-25 21:21:33 +0000891
bellard3fb2ded2003-06-24 13:22:59 +0000892 /* see if it is an MMU fault */
bellard93a40ea2003-10-27 21:13:06 +0000893 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
894 ((env->hflags & HF_CPL_MASK) == 3), 0);
bellard3fb2ded2003-06-24 13:22:59 +0000895 if (ret < 0)
896 return 0; /* not an MMU fault */
897 if (ret == 0)
898 return 1; /* the MMU fault was handled without causing real CPU fault */
899 /* now we have a real cpu fault */
bellarda513fe12003-05-27 23:29:48 +0000900 tb = tb_find_pc(pc);
901 if (tb) {
bellard9de5e442003-03-23 16:49:39 +0000902 /* the PC is inside the translated code. It means that we have
903 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000904 cpu_restore_state(tb, env, pc, puc);
bellard3fb2ded2003-06-24 13:22:59 +0000905 }
bellard4cbf74b2003-08-10 21:48:43 +0000906 if (ret == 1) {
bellard3fb2ded2003-06-24 13:22:59 +0000907#if 0
bellard4cbf74b2003-08-10 21:48:43 +0000908 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
909 env->eip, env->cr[2], env->error_code);
bellard3fb2ded2003-06-24 13:22:59 +0000910#endif
bellard4cbf74b2003-08-10 21:48:43 +0000911 /* we restore the process signal mask as the sigreturn should
912 do it (XXX: use sigsetjmp) */
913 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard54ca9092005-12-04 18:46:06 +0000914 raise_exception_err(env->exception_index, env->error_code);
bellard4cbf74b2003-08-10 21:48:43 +0000915 } else {
916 /* activate soft MMU for this block */
bellard3f337312003-08-20 23:02:09 +0000917 env->hflags |= HF_SOFTMMU_MASK;
bellardfbf9eeb2004-04-25 21:21:33 +0000918 cpu_resume_from_signal(env, puc);
bellard4cbf74b2003-08-10 21:48:43 +0000919 }
bellard3fb2ded2003-06-24 13:22:59 +0000920 /* never comes here */
921 return 1;
922}
923
bellarde4533c72003-06-15 19:51:39 +0000924#elif defined(TARGET_ARM)
bellard3fb2ded2003-06-24 13:22:59 +0000925static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000926 int is_write, sigset_t *old_set,
927 void *puc)
bellard3fb2ded2003-06-24 13:22:59 +0000928{
bellard68016c62005-02-07 23:12:27 +0000929 TranslationBlock *tb;
930 int ret;
931
932 if (cpu_single_env)
933 env = cpu_single_env; /* XXX: find a correct solution for multithread */
934#if defined(DEBUG_SIGNAL)
935 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
936 pc, address, is_write, *(unsigned long *)old_set);
937#endif
bellard9f0777e2005-02-02 20:42:01 +0000938 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000939 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard9f0777e2005-02-02 20:42:01 +0000940 return 1;
941 }
bellard68016c62005-02-07 23:12:27 +0000942 /* see if it is an MMU fault */
943 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
944 if (ret < 0)
945 return 0; /* not an MMU fault */
946 if (ret == 0)
947 return 1; /* the MMU fault was handled without causing real CPU fault */
948 /* now we have a real cpu fault */
949 tb = tb_find_pc(pc);
950 if (tb) {
951 /* the PC is inside the translated code. It means that we have
952 a virtual CPU fault */
953 cpu_restore_state(tb, env, pc, puc);
954 }
955 /* we restore the process signal mask as the sigreturn should
956 do it (XXX: use sigsetjmp) */
957 sigprocmask(SIG_SETMASK, old_set, NULL);
958 cpu_loop_exit();
bellard3fb2ded2003-06-24 13:22:59 +0000959}
bellard93ac68b2003-09-30 20:57:29 +0000960#elif defined(TARGET_SPARC)
961static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000962 int is_write, sigset_t *old_set,
963 void *puc)
bellard93ac68b2003-09-30 20:57:29 +0000964{
bellard68016c62005-02-07 23:12:27 +0000965 TranslationBlock *tb;
966 int ret;
967
968 if (cpu_single_env)
969 env = cpu_single_env; /* XXX: find a correct solution for multithread */
970#if defined(DEBUG_SIGNAL)
971 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
972 pc, address, is_write, *(unsigned long *)old_set);
973#endif
bellardb453b702004-01-04 15:45:21 +0000974 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +0000975 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellardb453b702004-01-04 15:45:21 +0000976 return 1;
977 }
bellard68016c62005-02-07 23:12:27 +0000978 /* see if it is an MMU fault */
979 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
980 if (ret < 0)
981 return 0; /* not an MMU fault */
982 if (ret == 0)
983 return 1; /* the MMU fault was handled without causing real CPU fault */
984 /* now we have a real cpu fault */
985 tb = tb_find_pc(pc);
986 if (tb) {
987 /* the PC is inside the translated code. It means that we have
988 a virtual CPU fault */
989 cpu_restore_state(tb, env, pc, puc);
990 }
991 /* we restore the process signal mask as the sigreturn should
992 do it (XXX: use sigsetjmp) */
993 sigprocmask(SIG_SETMASK, old_set, NULL);
994 cpu_loop_exit();
bellard93ac68b2003-09-30 20:57:29 +0000995}
bellard67867302003-11-23 17:05:30 +0000996#elif defined (TARGET_PPC)
997static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000998 int is_write, sigset_t *old_set,
999 void *puc)
bellard67867302003-11-23 17:05:30 +00001000{
1001 TranslationBlock *tb;
bellardce097762004-01-04 23:53:18 +00001002 int ret;
bellard67867302003-11-23 17:05:30 +00001003
bellard67867302003-11-23 17:05:30 +00001004 if (cpu_single_env)
1005 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellard67867302003-11-23 17:05:30 +00001006#if defined(DEBUG_SIGNAL)
1007 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1008 pc, address, is_write, *(unsigned long *)old_set);
1009#endif
1010 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +00001011 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard67867302003-11-23 17:05:30 +00001012 return 1;
1013 }
1014
bellardce097762004-01-04 23:53:18 +00001015 /* see if it is an MMU fault */
bellard7f957d22004-01-18 23:19:48 +00001016 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
bellardce097762004-01-04 23:53:18 +00001017 if (ret < 0)
1018 return 0; /* not an MMU fault */
1019 if (ret == 0)
1020 return 1; /* the MMU fault was handled without causing real CPU fault */
1021
bellard67867302003-11-23 17:05:30 +00001022 /* now we have a real cpu fault */
1023 tb = tb_find_pc(pc);
1024 if (tb) {
1025 /* the PC is inside the translated code. It means that we have
1026 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +00001027 cpu_restore_state(tb, env, pc, puc);
bellard67867302003-11-23 17:05:30 +00001028 }
bellardce097762004-01-04 23:53:18 +00001029 if (ret == 1) {
bellard67867302003-11-23 17:05:30 +00001030#if 0
bellardce097762004-01-04 23:53:18 +00001031 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1032 env->nip, env->error_code, tb);
bellard67867302003-11-23 17:05:30 +00001033#endif
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
bellardbf3e8bf2004-02-16 21:58:54 +00001036 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard9fddaa02004-05-21 12:59:32 +00001037 do_raise_exception_err(env->exception_index, env->error_code);
bellardce097762004-01-04 23:53:18 +00001038 } else {
1039 /* activate soft MMU for this block */
bellardfbf9eeb2004-04-25 21:21:33 +00001040 cpu_resume_from_signal(env, puc);
bellardce097762004-01-04 23:53:18 +00001041 }
bellard67867302003-11-23 17:05:30 +00001042 /* never comes here */
1043 return 1;
1044}
bellard6af0bf92005-07-02 14:58:51 +00001045
pbrooke6e59062006-10-22 00:18:54 +00001046#elif defined(TARGET_M68K)
1047static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1048 int is_write, sigset_t *old_set,
1049 void *puc)
1050{
1051 TranslationBlock *tb;
1052 int ret;
1053
1054 if (cpu_single_env)
1055 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1056#if defined(DEBUG_SIGNAL)
1057 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1058 pc, address, is_write, *(unsigned long *)old_set);
1059#endif
1060 /* XXX: locking issue */
1061 if (is_write && page_unprotect(address, pc, puc)) {
1062 return 1;
1063 }
1064 /* see if it is an MMU fault */
1065 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1066 if (ret < 0)
1067 return 0; /* not an MMU fault */
1068 if (ret == 0)
1069 return 1; /* the MMU fault was handled without causing real CPU fault */
1070 /* now we have a real cpu fault */
1071 tb = tb_find_pc(pc);
1072 if (tb) {
1073 /* the PC is inside the translated code. It means that we have
1074 a virtual CPU fault */
1075 cpu_restore_state(tb, env, pc, puc);
1076 }
1077 /* we restore the process signal mask as the sigreturn should
1078 do it (XXX: use sigsetjmp) */
1079 sigprocmask(SIG_SETMASK, old_set, NULL);
1080 cpu_loop_exit();
1081 /* never comes here */
1082 return 1;
1083}
1084
bellard6af0bf92005-07-02 14:58:51 +00001085#elif defined (TARGET_MIPS)
1086static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1087 int is_write, sigset_t *old_set,
1088 void *puc)
1089{
1090 TranslationBlock *tb;
1091 int ret;
1092
1093 if (cpu_single_env)
1094 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1095#if defined(DEBUG_SIGNAL)
1096 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1097 pc, address, is_write, *(unsigned long *)old_set);
1098#endif
1099 /* XXX: locking issue */
pbrook53a59602006-03-25 19:31:22 +00001100 if (is_write && page_unprotect(h2g(address), pc, puc)) {
bellard6af0bf92005-07-02 14:58:51 +00001101 return 1;
1102 }
1103
1104 /* see if it is an MMU fault */
bellardcc9442b2005-11-26 18:43:28 +00001105 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
bellard6af0bf92005-07-02 14:58:51 +00001106 if (ret < 0)
1107 return 0; /* not an MMU fault */
1108 if (ret == 0)
1109 return 1; /* the MMU fault was handled without causing real CPU fault */
1110
1111 /* now we have a real cpu fault */
1112 tb = tb_find_pc(pc);
1113 if (tb) {
1114 /* the PC is inside the translated code. It means that we have
1115 a virtual CPU fault */
1116 cpu_restore_state(tb, env, pc, puc);
1117 }
1118 if (ret == 1) {
1119#if 0
1120 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1121 env->nip, env->error_code, tb);
1122#endif
1123 /* we restore the process signal mask as the sigreturn should
1124 do it (XXX: use sigsetjmp) */
1125 sigprocmask(SIG_SETMASK, old_set, NULL);
1126 do_raise_exception_err(env->exception_index, env->error_code);
1127 } else {
1128 /* activate soft MMU for this block */
1129 cpu_resume_from_signal(env, puc);
1130 }
1131 /* never comes here */
1132 return 1;
1133}
1134
bellardfdf9b3e2006-04-27 21:07:38 +00001135#elif defined (TARGET_SH4)
1136static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1137 int is_write, sigset_t *old_set,
1138 void *puc)
1139{
1140 TranslationBlock *tb;
1141 int ret;
1142
1143 if (cpu_single_env)
1144 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1145#if defined(DEBUG_SIGNAL)
1146 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1147 pc, address, is_write, *(unsigned long *)old_set);
1148#endif
1149 /* XXX: locking issue */
1150 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1151 return 1;
1152 }
1153
1154 /* see if it is an MMU fault */
1155 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1156 if (ret < 0)
1157 return 0; /* not an MMU fault */
1158 if (ret == 0)
1159 return 1; /* the MMU fault was handled without causing real CPU fault */
1160
1161 /* now we have a real cpu fault */
1162 tb = tb_find_pc(pc);
1163 if (tb) {
1164 /* the PC is inside the translated code. It means that we have
1165 a virtual CPU fault */
1166 cpu_restore_state(tb, env, pc, puc);
1167 }
bellardfdf9b3e2006-04-27 21:07:38 +00001168#if 0
1169 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1170 env->nip, env->error_code, tb);
1171#endif
1172 /* we restore the process signal mask as the sigreturn should
1173 do it (XXX: use sigsetjmp) */
pbrook355fb232006-06-17 19:58:25 +00001174 sigprocmask(SIG_SETMASK, old_set, NULL);
1175 cpu_loop_exit();
bellardfdf9b3e2006-04-27 21:07:38 +00001176 /* never comes here */
1177 return 1;
1178}
bellarde4533c72003-06-15 19:51:39 +00001179#else
1180#error unsupported target CPU
1181#endif
bellard9de5e442003-03-23 16:49:39 +00001182
bellard2b413142003-05-14 23:01:10 +00001183#if defined(__i386__)
1184
bellardd8ecc0b2007-02-05 21:41:46 +00001185#if defined(__APPLE__)
1186# include <sys/ucontext.h>
1187
1188# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1189# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1190# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1191#else
1192# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1193# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1194# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1195#endif
1196
bellardbf3e8bf2004-02-16 21:58:54 +00001197#if defined(USE_CODE_COPY)
1198static void cpu_send_trap(unsigned long pc, int trap,
1199 struct ucontext *uc)
1200{
1201 TranslationBlock *tb;
1202
1203 if (cpu_single_env)
1204 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1205 /* now we have a real cpu fault */
1206 tb = tb_find_pc(pc);
1207 if (tb) {
1208 /* the PC is inside the translated code. It means that we have
1209 a virtual CPU fault */
1210 cpu_restore_state(tb, env, pc, uc);
1211 }
1212 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1213 raise_exception_err(trap, env->error_code);
1214}
1215#endif
1216
ths5a7b5422007-01-31 12:16:51 +00001217int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001218 void *puc)
bellard9de5e442003-03-23 16:49:39 +00001219{
ths5a7b5422007-01-31 12:16:51 +00001220 siginfo_t *info = pinfo;
bellard9de5e442003-03-23 16:49:39 +00001221 struct ucontext *uc = puc;
1222 unsigned long pc;
bellardbf3e8bf2004-02-16 21:58:54 +00001223 int trapno;
bellard97eb5b12004-02-25 23:19:55 +00001224
bellardd691f662003-03-24 21:58:34 +00001225#ifndef REG_EIP
1226/* for glibc 2.1 */
bellardfd6ce8f2003-05-14 19:00:11 +00001227#define REG_EIP EIP
1228#define REG_ERR ERR
1229#define REG_TRAPNO TRAPNO
bellardd691f662003-03-24 21:58:34 +00001230#endif
bellardd8ecc0b2007-02-05 21:41:46 +00001231 pc = EIP_sig(uc);
1232 trapno = TRAP_sig(uc);
bellardbf3e8bf2004-02-16 21:58:54 +00001233#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1234 if (trapno == 0x00 || trapno == 0x05) {
1235 /* send division by zero or bound exception */
1236 cpu_send_trap(pc, trapno, uc);
1237 return 1;
1238 } else
1239#endif
1240 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1241 trapno == 0xe ?
bellardd8ecc0b2007-02-05 21:41:46 +00001242 (ERROR_sig(uc) >> 1) & 1 : 0,
bellardbf3e8bf2004-02-16 21:58:54 +00001243 &uc->uc_sigmask, puc);
bellard2b413142003-05-14 23:01:10 +00001244}
1245
bellardbc51c5c2004-03-17 23:46:04 +00001246#elif defined(__x86_64__)
1247
ths5a7b5422007-01-31 12:16:51 +00001248int cpu_signal_handler(int host_signum, void *pinfo,
bellardbc51c5c2004-03-17 23:46:04 +00001249 void *puc)
1250{
ths5a7b5422007-01-31 12:16:51 +00001251 siginfo_t *info = pinfo;
bellardbc51c5c2004-03-17 23:46:04 +00001252 struct ucontext *uc = puc;
1253 unsigned long pc;
1254
1255 pc = uc->uc_mcontext.gregs[REG_RIP];
1256 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1257 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1258 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1259 &uc->uc_sigmask, puc);
1260}
1261
bellard83fb7ad2004-07-05 21:25:26 +00001262#elif defined(__powerpc__)
bellard2b413142003-05-14 23:01:10 +00001263
bellard83fb7ad2004-07-05 21:25:26 +00001264/***********************************************************************
1265 * signal context platform-specific definitions
1266 * From Wine
1267 */
1268#ifdef linux
1269/* All Registers access - only for local access */
1270# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1271/* Gpr Registers access */
1272# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1273# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1274# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1275# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1276# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1277# define LR_sig(context) REG_sig(link, context) /* Link register */
1278# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1279/* Float Registers access */
1280# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1281# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1282/* Exception Registers access */
1283# define DAR_sig(context) REG_sig(dar, context)
1284# define DSISR_sig(context) REG_sig(dsisr, context)
1285# define TRAP_sig(context) REG_sig(trap, context)
1286#endif /* linux */
1287
1288#ifdef __APPLE__
1289# include <sys/ucontext.h>
1290typedef struct ucontext SIGCONTEXT;
1291/* All Registers access - only for local access */
1292# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1293# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1294# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1295# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1296/* Gpr Registers access */
1297# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1298# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1299# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1300# define CTR_sig(context) REG_sig(ctr, context)
1301# define XER_sig(context) REG_sig(xer, context) /* Link register */
1302# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1303# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1304/* Float Registers access */
1305# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1306# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1307/* Exception Registers access */
1308# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1309# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1310# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1311#endif /* __APPLE__ */
1312
ths5a7b5422007-01-31 12:16:51 +00001313int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001314 void *puc)
bellard2b413142003-05-14 23:01:10 +00001315{
ths5a7b5422007-01-31 12:16:51 +00001316 siginfo_t *info = pinfo;
bellard25eb4482003-05-14 21:50:54 +00001317 struct ucontext *uc = puc;
bellard25eb4482003-05-14 21:50:54 +00001318 unsigned long pc;
bellard25eb4482003-05-14 21:50:54 +00001319 int is_write;
1320
bellard83fb7ad2004-07-05 21:25:26 +00001321 pc = IAR_sig(uc);
bellard25eb4482003-05-14 21:50:54 +00001322 is_write = 0;
1323#if 0
1324 /* ppc 4xx case */
bellard83fb7ad2004-07-05 21:25:26 +00001325 if (DSISR_sig(uc) & 0x00800000)
bellard25eb4482003-05-14 21:50:54 +00001326 is_write = 1;
bellard9de5e442003-03-23 16:49:39 +00001327#else
bellard83fb7ad2004-07-05 21:25:26 +00001328 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
bellard25eb4482003-05-14 21:50:54 +00001329 is_write = 1;
1330#endif
1331 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001332 is_write, &uc->uc_sigmask, puc);
bellard9de5e442003-03-23 16:49:39 +00001333}
bellard2b413142003-05-14 23:01:10 +00001334
bellard2f87c602003-06-02 20:38:09 +00001335#elif defined(__alpha__)
1336
ths5a7b5422007-01-31 12:16:51 +00001337int cpu_signal_handler(int host_signum, void *pinfo,
bellard2f87c602003-06-02 20:38:09 +00001338 void *puc)
1339{
ths5a7b5422007-01-31 12:16:51 +00001340 siginfo_t *info = pinfo;
bellard2f87c602003-06-02 20:38:09 +00001341 struct ucontext *uc = puc;
1342 uint32_t *pc = uc->uc_mcontext.sc_pc;
1343 uint32_t insn = *pc;
1344 int is_write = 0;
1345
bellard8c6939c2003-06-09 15:28:00 +00001346 /* XXX: need kernel patch to get write flag faster */
bellard2f87c602003-06-02 20:38:09 +00001347 switch (insn >> 26) {
1348 case 0x0d: // stw
1349 case 0x0e: // stb
1350 case 0x0f: // stq_u
1351 case 0x24: // stf
1352 case 0x25: // stg
1353 case 0x26: // sts
1354 case 0x27: // stt
1355 case 0x2c: // stl
1356 case 0x2d: // stq
1357 case 0x2e: // stl_c
1358 case 0x2f: // stq_c
1359 is_write = 1;
1360 }
1361
1362 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001363 is_write, &uc->uc_sigmask, puc);
bellard2f87c602003-06-02 20:38:09 +00001364}
bellard8c6939c2003-06-09 15:28:00 +00001365#elif defined(__sparc__)
1366
ths5a7b5422007-01-31 12:16:51 +00001367int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001368 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001369{
ths5a7b5422007-01-31 12:16:51 +00001370 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001371 uint32_t *regs = (uint32_t *)(info + 1);
1372 void *sigmask = (regs + 20);
1373 unsigned long pc;
1374 int is_write;
1375 uint32_t insn;
1376
1377 /* XXX: is there a standard glibc define ? */
1378 pc = regs[1];
1379 /* XXX: need kernel patch to get write flag faster */
1380 is_write = 0;
1381 insn = *(uint32_t *)pc;
1382 if ((insn >> 30) == 3) {
1383 switch((insn >> 19) & 0x3f) {
1384 case 0x05: // stb
1385 case 0x06: // sth
1386 case 0x04: // st
1387 case 0x07: // std
1388 case 0x24: // stf
1389 case 0x27: // stdf
1390 case 0x25: // stfsr
1391 is_write = 1;
1392 break;
1393 }
1394 }
1395 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001396 is_write, sigmask, NULL);
bellard8c6939c2003-06-09 15:28:00 +00001397}
1398
1399#elif defined(__arm__)
1400
ths5a7b5422007-01-31 12:16:51 +00001401int cpu_signal_handler(int host_signum, void *pinfo,
bellarde4533c72003-06-15 19:51:39 +00001402 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001403{
ths5a7b5422007-01-31 12:16:51 +00001404 siginfo_t *info = pinfo;
bellard8c6939c2003-06-09 15:28:00 +00001405 struct ucontext *uc = puc;
1406 unsigned long pc;
1407 int is_write;
1408
1409 pc = uc->uc_mcontext.gregs[R15];
1410 /* XXX: compute is_write */
1411 is_write = 0;
1412 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1413 is_write,
pbrookf3a96762006-07-29 19:09:31 +00001414 &uc->uc_sigmask, puc);
bellard8c6939c2003-06-09 15:28:00 +00001415}
1416
bellard38e584a2003-08-10 22:14:22 +00001417#elif defined(__mc68000)
1418
ths5a7b5422007-01-31 12:16:51 +00001419int cpu_signal_handler(int host_signum, void *pinfo,
bellard38e584a2003-08-10 22:14:22 +00001420 void *puc)
1421{
ths5a7b5422007-01-31 12:16:51 +00001422 siginfo_t *info = pinfo;
bellard38e584a2003-08-10 22:14:22 +00001423 struct ucontext *uc = puc;
1424 unsigned long pc;
1425 int is_write;
1426
1427 pc = uc->uc_mcontext.gregs[16];
1428 /* XXX: compute is_write */
1429 is_write = 0;
1430 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1431 is_write,
bellardbf3e8bf2004-02-16 21:58:54 +00001432 &uc->uc_sigmask, puc);
bellard38e584a2003-08-10 22:14:22 +00001433}
1434
bellardb8076a72005-04-07 22:20:31 +00001435#elif defined(__ia64)
1436
1437#ifndef __ISR_VALID
1438 /* This ought to be in <bits/siginfo.h>... */
1439# define __ISR_VALID 1
bellardb8076a72005-04-07 22:20:31 +00001440#endif
1441
ths5a7b5422007-01-31 12:16:51 +00001442int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
bellardb8076a72005-04-07 22:20:31 +00001443{
ths5a7b5422007-01-31 12:16:51 +00001444 siginfo_t *info = pinfo;
bellardb8076a72005-04-07 22:20:31 +00001445 struct ucontext *uc = puc;
1446 unsigned long ip;
1447 int is_write = 0;
1448
1449 ip = uc->uc_mcontext.sc_ip;
1450 switch (host_signum) {
1451 case SIGILL:
1452 case SIGFPE:
1453 case SIGSEGV:
1454 case SIGBUS:
1455 case SIGTRAP:
bellardfd4a43e2006-04-24 20:32:17 +00001456 if (info->si_code && (info->si_segvflags & __ISR_VALID))
bellardb8076a72005-04-07 22:20:31 +00001457 /* ISR.W (write-access) is bit 33: */
1458 is_write = (info->si_isr >> 33) & 1;
1459 break;
1460
1461 default:
1462 break;
1463 }
1464 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1465 is_write,
1466 &uc->uc_sigmask, puc);
1467}
1468
bellard90cb9492005-07-24 15:11:38 +00001469#elif defined(__s390__)
1470
ths5a7b5422007-01-31 12:16:51 +00001471int cpu_signal_handler(int host_signum, void *pinfo,
bellard90cb9492005-07-24 15:11:38 +00001472 void *puc)
1473{
ths5a7b5422007-01-31 12:16:51 +00001474 siginfo_t *info = pinfo;
bellard90cb9492005-07-24 15:11:38 +00001475 struct ucontext *uc = puc;
1476 unsigned long pc;
1477 int is_write;
1478
1479 pc = uc->uc_mcontext.psw.addr;
1480 /* XXX: compute is_write */
1481 is_write = 0;
1482 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1483 is_write,
1484 &uc->uc_sigmask, puc);
1485}
1486
bellard2b413142003-05-14 23:01:10 +00001487#else
1488
bellard3fb2ded2003-06-24 13:22:59 +00001489#error host CPU specific signal handler needed
bellard2b413142003-05-14 23:01:10 +00001490
1491#endif
bellard67b915a2004-03-31 23:37:16 +00001492
1493#endif /* !defined(CONFIG_SOFTMMU) */