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bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
3 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
bellard7d132992003-03-06 23:23:54 +000019 */
bellarde4533c72003-06-15 19:51:39 +000020#include "config.h"
bellard93ac68b2003-09-30 20:57:29 +000021#include "exec.h"
bellard956034d2003-04-29 20:40:53 +000022#include "disas.h"
bellard7d132992003-03-06 23:23:54 +000023
bellardfbf9eeb2004-04-25 21:21:33 +000024#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
bellard36bdbe52003-11-19 22:12:02 +000038int tb_invalidated_flag;
39
bellarddc990652003-03-19 00:00:28 +000040//#define DEBUG_EXEC
bellard9de5e442003-03-23 16:49:39 +000041//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000042
bellard93ac68b2003-09-30 20:57:29 +000043#if defined(TARGET_ARM) || defined(TARGET_SPARC)
bellarde4533c72003-06-15 19:51:39 +000044/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
bellard34751872005-07-02 14:31:34 +000050#ifndef TARGET_SPARC
51#define reg_T2
52#endif
bellarde4533c72003-06-15 19:51:39 +000053
bellardfbf9eeb2004-04-25 21:21:33 +000054/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
bellard8a40a182005-11-20 10:35:40 +000076
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 T0 = 0;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
151 T0 = 0;
152 }
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
156 return tb;
157}
158
159static inline TranslationBlock *tb_find_fast(void)
160{
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
163 unsigned int flags;
164
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
167 is executed. */
168#if defined(TARGET_I386)
169 flags = env->hflags;
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173#elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
bellardb5ff1b32005-11-26 10:38:39 +0000175 | (env->vfp.vec_stride << 4);
176 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
177 flags |= (1 << 6);
bellard8a40a182005-11-20 10:35:40 +0000178 cs_base = 0;
179 pc = env->regs[15];
180#elif defined(TARGET_SPARC)
181#ifdef TARGET_SPARC64
182 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183#else
184 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
194 flags = env->hflags & MIPS_HFLAGS_TMASK;
bellardcc9442b2005-11-26 18:43:28 +0000195 cs_base = 0;
bellard8a40a182005-11-20 10:35:40 +0000196 pc = env->PC;
197#else
198#error unsupported CPU
199#endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 }
205 return tb;
206}
207
208
bellard7d132992003-03-06 23:23:54 +0000209/* main execution loop */
210
bellarde4533c72003-06-15 19:51:39 +0000211int cpu_exec(CPUState *env1)
bellard7d132992003-03-06 23:23:54 +0000212{
bellard34751872005-07-02 14:31:34 +0000213 int saved_T0, saved_T1;
214#if defined(reg_T2)
215 int saved_T2;
216#endif
bellarde4533c72003-06-15 19:51:39 +0000217 CPUState *saved_env;
bellard34751872005-07-02 14:31:34 +0000218#if defined(TARGET_I386)
bellard04369ff2003-03-20 22:33:23 +0000219#ifdef reg_EAX
220 int saved_EAX;
221#endif
222#ifdef reg_ECX
223 int saved_ECX;
224#endif
225#ifdef reg_EDX
226 int saved_EDX;
227#endif
228#ifdef reg_EBX
229 int saved_EBX;
230#endif
231#ifdef reg_ESP
232 int saved_ESP;
233#endif
234#ifdef reg_EBP
235 int saved_EBP;
236#endif
237#ifdef reg_ESI
238 int saved_ESI;
239#endif
240#ifdef reg_EDI
241 int saved_EDI;
242#endif
bellard34751872005-07-02 14:31:34 +0000243#elif defined(TARGET_SPARC)
244#if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246#endif
247#endif
bellard8c6939c2003-06-09 15:28:00 +0000248#ifdef __sparc__
249 int saved_i7, tmp_T0;
250#endif
bellard8a40a182005-11-20 10:35:40 +0000251 int ret, interrupt_request;
bellard7d132992003-03-06 23:23:54 +0000252 void (*gen_func)(void);
bellard8a40a182005-11-20 10:35:40 +0000253 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000254 uint8_t *tc_ptr;
bellard8c6939c2003-06-09 15:28:00 +0000255
bellard5a1e3cf2005-11-23 21:02:53 +0000256#if defined(TARGET_I386)
257 /* handle exit of HALTED state */
258 if (env1->hflags & HF_HALTED_MASK) {
259 /* disable halt condition */
260 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
261 (env1->eflags & IF_MASK)) {
262 env1->hflags &= ~HF_HALTED_MASK;
263 } else {
264 return EXCP_HALTED;
265 }
266 }
bellarde80e1cc2005-11-23 22:05:28 +0000267#elif defined(TARGET_PPC)
bellard50443c92005-11-26 20:15:14 +0000268 if (env1->halted) {
bellarde80e1cc2005-11-23 22:05:28 +0000269 if (env1->msr[MSR_EE] &&
270 (env1->interrupt_request &
271 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
bellard50443c92005-11-26 20:15:14 +0000272 env1->halted = 0;
bellarde80e1cc2005-11-23 22:05:28 +0000273 } else {
274 return EXCP_HALTED;
275 }
276 }
bellard9332f9d2005-11-26 10:46:39 +0000277#elif defined(TARGET_ARM)
278 if (env1->halted) {
279 /* An interrupt wakes the CPU even if the I and F CPSR bits are
280 set. */
281 if (env1->interrupt_request
282 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
283 env1->halted = 0;
284 } else {
285 return EXCP_HALTED;
286 }
287 }
bellard5a1e3cf2005-11-23 21:02:53 +0000288#endif
289
bellard6a00d602005-11-21 23:25:50 +0000290 cpu_single_env = env1;
291
bellard7d132992003-03-06 23:23:54 +0000292 /* first we save global registers */
bellardc27004e2005-01-03 23:35:10 +0000293 saved_env = env;
294 env = env1;
bellard7d132992003-03-06 23:23:54 +0000295 saved_T0 = T0;
296 saved_T1 = T1;
bellard34751872005-07-02 14:31:34 +0000297#if defined(reg_T2)
bellarde4533c72003-06-15 19:51:39 +0000298 saved_T2 = T2;
bellard34751872005-07-02 14:31:34 +0000299#endif
bellarde4533c72003-06-15 19:51:39 +0000300#ifdef __sparc__
301 /* we also save i7 because longjmp may not restore it */
302 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
303#endif
304
305#if defined(TARGET_I386)
bellard04369ff2003-03-20 22:33:23 +0000306#ifdef reg_EAX
307 saved_EAX = EAX;
bellard04369ff2003-03-20 22:33:23 +0000308#endif
309#ifdef reg_ECX
310 saved_ECX = ECX;
bellard04369ff2003-03-20 22:33:23 +0000311#endif
312#ifdef reg_EDX
313 saved_EDX = EDX;
bellard04369ff2003-03-20 22:33:23 +0000314#endif
315#ifdef reg_EBX
316 saved_EBX = EBX;
bellard04369ff2003-03-20 22:33:23 +0000317#endif
318#ifdef reg_ESP
319 saved_ESP = ESP;
bellard04369ff2003-03-20 22:33:23 +0000320#endif
321#ifdef reg_EBP
322 saved_EBP = EBP;
bellard04369ff2003-03-20 22:33:23 +0000323#endif
324#ifdef reg_ESI
325 saved_ESI = ESI;
bellard04369ff2003-03-20 22:33:23 +0000326#endif
327#ifdef reg_EDI
328 saved_EDI = EDI;
bellard04369ff2003-03-20 22:33:23 +0000329#endif
bellard0d1a29f2004-10-12 22:01:28 +0000330
331 env_to_regs();
bellard9de5e442003-03-23 16:49:39 +0000332 /* put eflags in CPU temporary format */
bellardfc2b4c42003-03-29 16:52:44 +0000333 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
334 DF = 1 - (2 * ((env->eflags >> 10) & 1));
bellard9de5e442003-03-23 16:49:39 +0000335 CC_OP = CC_OP_EFLAGS;
bellardfc2b4c42003-03-29 16:52:44 +0000336 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000337#elif defined(TARGET_ARM)
bellard93ac68b2003-09-30 20:57:29 +0000338#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000339#if defined(reg_REGWPTR)
340 saved_regwptr = REGWPTR;
341#endif
bellard67867302003-11-23 17:05:30 +0000342#elif defined(TARGET_PPC)
bellard6af0bf92005-07-02 14:58:51 +0000343#elif defined(TARGET_MIPS)
bellarde4533c72003-06-15 19:51:39 +0000344#else
345#error unsupported target CPU
346#endif
bellard3fb2ded2003-06-24 13:22:59 +0000347 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000348
bellard7d132992003-03-06 23:23:54 +0000349 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000350 for(;;) {
351 if (setjmp(env->jmp_env) == 0) {
bellardee8b7022004-02-03 23:35:10 +0000352 env->current_tb = NULL;
bellard3fb2ded2003-06-24 13:22:59 +0000353 /* if an exception is pending, we execute it here */
354 if (env->exception_index >= 0) {
355 if (env->exception_index >= EXCP_INTERRUPT) {
356 /* exit request from the cpu execution loop */
357 ret = env->exception_index;
358 break;
359 } else if (env->user_mode_only) {
360 /* if user mode only, we simulate a fake exception
361 which will be hanlded outside the cpu execution
362 loop */
bellard83479e72003-06-25 16:12:37 +0000363#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000364 do_interrupt_user(env->exception_index,
365 env->exception_is_int,
366 env->error_code,
367 env->exception_next_eip);
bellard83479e72003-06-25 16:12:37 +0000368#endif
bellard3fb2ded2003-06-24 13:22:59 +0000369 ret = env->exception_index;
370 break;
371 } else {
bellard83479e72003-06-25 16:12:37 +0000372#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000373 /* simulate a real cpu exception. On i386, it can
374 trigger new exceptions, but we do not handle
375 double or triple faults yet. */
376 do_interrupt(env->exception_index,
377 env->exception_is_int,
378 env->error_code,
bellardd05e66d2003-08-20 21:34:35 +0000379 env->exception_next_eip, 0);
bellardce097762004-01-04 23:53:18 +0000380#elif defined(TARGET_PPC)
381 do_interrupt(env);
bellard6af0bf92005-07-02 14:58:51 +0000382#elif defined(TARGET_MIPS)
383 do_interrupt(env);
bellarde95c8d52004-09-30 22:22:08 +0000384#elif defined(TARGET_SPARC)
bellard1a0c3292005-02-13 19:02:07 +0000385 do_interrupt(env->exception_index);
bellardb5ff1b32005-11-26 10:38:39 +0000386#elif defined(TARGET_ARM)
387 do_interrupt(env);
bellard83479e72003-06-25 16:12:37 +0000388#endif
bellard3fb2ded2003-06-24 13:22:59 +0000389 }
390 env->exception_index = -1;
bellard9df217a2005-02-10 22:05:51 +0000391 }
392#ifdef USE_KQEMU
393 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
394 int ret;
395 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
396 ret = kqemu_cpu_exec(env);
397 /* put eflags in CPU temporary format */
398 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
399 DF = 1 - (2 * ((env->eflags >> 10) & 1));
400 CC_OP = CC_OP_EFLAGS;
401 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
402 if (ret == 1) {
403 /* exception */
404 longjmp(env->jmp_env, 1);
405 } else if (ret == 2) {
406 /* softmmu execution needed */
407 } else {
408 if (env->interrupt_request != 0) {
409 /* hardware interrupt will be executed just after */
410 } else {
411 /* otherwise, we restart */
412 longjmp(env->jmp_env, 1);
413 }
414 }
bellard9de5e442003-03-23 16:49:39 +0000415 }
bellard9df217a2005-02-10 22:05:51 +0000416#endif
417
bellard3fb2ded2003-06-24 13:22:59 +0000418 T0 = 0; /* force lookup of first TB */
419 for(;;) {
420#ifdef __sparc__
421 /* g1 can be modified by some libc? functions */
422 tmp_T0 = T0;
423#endif
bellard68a79312003-06-30 13:12:32 +0000424 interrupt_request = env->interrupt_request;
bellard2e255c62003-08-21 23:25:21 +0000425 if (__builtin_expect(interrupt_request, 0)) {
bellard68a79312003-06-30 13:12:32 +0000426#if defined(TARGET_I386)
427 /* if hardware interrupt pending, we execute it */
428 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
bellard3f337312003-08-20 23:02:09 +0000429 (env->eflags & IF_MASK) &&
430 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
bellard68a79312003-06-30 13:12:32 +0000431 int intno;
bellardfbf9eeb2004-04-25 21:21:33 +0000432 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellarda541f292004-04-12 20:39:29 +0000433 intno = cpu_get_pic_interrupt(env);
bellardf193c792004-03-21 17:06:25 +0000434 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard68a79312003-06-30 13:12:32 +0000435 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
436 }
bellardd05e66d2003-08-20 21:34:35 +0000437 do_interrupt(intno, 0, 0, 0, 1);
bellard907a5b22003-06-30 23:18:22 +0000438 /* ensure that no TB jump will be modified as
439 the program flow was changed */
440#ifdef __sparc__
441 tmp_T0 = 0;
442#else
443 T0 = 0;
444#endif
bellard68a79312003-06-30 13:12:32 +0000445 }
bellardce097762004-01-04 23:53:18 +0000446#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000447#if 0
448 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
449 cpu_ppc_reset(env);
450 }
451#endif
452 if (msr_ee != 0) {
bellard8a40a182005-11-20 10:35:40 +0000453 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
bellard9fddaa02004-05-21 12:59:32 +0000454 /* Raise it */
455 env->exception_index = EXCP_EXTERNAL;
456 env->error_code = 0;
bellardce097762004-01-04 23:53:18 +0000457 do_interrupt(env);
bellard8a40a182005-11-20 10:35:40 +0000458 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
459#ifdef __sparc__
460 tmp_T0 = 0;
461#else
462 T0 = 0;
463#endif
464 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
465 /* Raise it */
466 env->exception_index = EXCP_DECR;
467 env->error_code = 0;
468 do_interrupt(env);
bellard9fddaa02004-05-21 12:59:32 +0000469 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
bellard8a40a182005-11-20 10:35:40 +0000470#ifdef __sparc__
471 tmp_T0 = 0;
472#else
473 T0 = 0;
474#endif
475 }
bellardce097762004-01-04 23:53:18 +0000476 }
bellard6af0bf92005-07-02 14:58:51 +0000477#elif defined(TARGET_MIPS)
478 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
479 (env->CP0_Status & (1 << CP0St_IE)) &&
bellard7ebab692005-08-21 09:43:38 +0000480 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
bellard6af0bf92005-07-02 14:58:51 +0000481 !(env->hflags & MIPS_HFLAG_EXL) &&
482 !(env->hflags & MIPS_HFLAG_ERL) &&
483 !(env->hflags & MIPS_HFLAG_DM)) {
484 /* Raise it */
485 env->exception_index = EXCP_EXT_INTERRUPT;
486 env->error_code = 0;
487 do_interrupt(env);
488 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellard8a40a182005-11-20 10:35:40 +0000489#ifdef __sparc__
490 tmp_T0 = 0;
491#else
492 T0 = 0;
493#endif
bellard6af0bf92005-07-02 14:58:51 +0000494 }
bellarde95c8d52004-09-30 22:22:08 +0000495#elif defined(TARGET_SPARC)
bellard66321a12005-04-06 20:47:48 +0000496 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
497 (env->psret != 0)) {
498 int pil = env->interrupt_index & 15;
499 int type = env->interrupt_index & 0xf0;
500
501 if (((type == TT_EXTINT) &&
502 (pil == 15 || pil > env->psrpil)) ||
503 type != TT_EXTINT) {
504 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
505 do_interrupt(env->interrupt_index);
506 env->interrupt_index = 0;
bellard8a40a182005-11-20 10:35:40 +0000507#ifdef __sparc__
508 tmp_T0 = 0;
509#else
510 T0 = 0;
511#endif
bellard66321a12005-04-06 20:47:48 +0000512 }
bellarde95c8d52004-09-30 22:22:08 +0000513 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
514 //do_interrupt(0, 0, 0, 0, 0);
515 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
516 }
bellardb5ff1b32005-11-26 10:38:39 +0000517#elif defined(TARGET_ARM)
518 if (interrupt_request & CPU_INTERRUPT_FIQ
519 && !(env->uncached_cpsr & CPSR_F)) {
520 env->exception_index = EXCP_FIQ;
521 do_interrupt(env);
522 }
523 if (interrupt_request & CPU_INTERRUPT_HARD
524 && !(env->uncached_cpsr & CPSR_I)) {
525 env->exception_index = EXCP_IRQ;
526 do_interrupt(env);
527 }
bellard68a79312003-06-30 13:12:32 +0000528#endif
bellardb5ff1b32005-11-26 10:38:39 +0000529 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bellardbf3e8bf2004-02-16 21:58:54 +0000530 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
531 /* ensure that no TB jump will be modified as
532 the program flow was changed */
533#ifdef __sparc__
534 tmp_T0 = 0;
535#else
536 T0 = 0;
537#endif
538 }
bellard68a79312003-06-30 13:12:32 +0000539 if (interrupt_request & CPU_INTERRUPT_EXIT) {
540 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
541 env->exception_index = EXCP_INTERRUPT;
542 cpu_loop_exit();
543 }
bellard3fb2ded2003-06-24 13:22:59 +0000544 }
545#ifdef DEBUG_EXEC
bellardb5ff1b32005-11-26 10:38:39 +0000546 if ((loglevel & CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000547#if defined(TARGET_I386)
548 /* restore flags in standard format */
bellardfc9f7152005-04-26 19:33:35 +0000549#ifdef reg_EAX
bellard3fb2ded2003-06-24 13:22:59 +0000550 env->regs[R_EAX] = EAX;
bellardfc9f7152005-04-26 19:33:35 +0000551#endif
552#ifdef reg_EBX
bellard3fb2ded2003-06-24 13:22:59 +0000553 env->regs[R_EBX] = EBX;
bellardfc9f7152005-04-26 19:33:35 +0000554#endif
555#ifdef reg_ECX
bellard3fb2ded2003-06-24 13:22:59 +0000556 env->regs[R_ECX] = ECX;
bellardfc9f7152005-04-26 19:33:35 +0000557#endif
558#ifdef reg_EDX
bellard3fb2ded2003-06-24 13:22:59 +0000559 env->regs[R_EDX] = EDX;
bellardfc9f7152005-04-26 19:33:35 +0000560#endif
561#ifdef reg_ESI
bellard3fb2ded2003-06-24 13:22:59 +0000562 env->regs[R_ESI] = ESI;
bellardfc9f7152005-04-26 19:33:35 +0000563#endif
564#ifdef reg_EDI
bellard3fb2ded2003-06-24 13:22:59 +0000565 env->regs[R_EDI] = EDI;
bellardfc9f7152005-04-26 19:33:35 +0000566#endif
567#ifdef reg_EBP
bellard3fb2ded2003-06-24 13:22:59 +0000568 env->regs[R_EBP] = EBP;
bellardfc9f7152005-04-26 19:33:35 +0000569#endif
570#ifdef reg_ESP
bellard3fb2ded2003-06-24 13:22:59 +0000571 env->regs[R_ESP] = ESP;
bellardfc9f7152005-04-26 19:33:35 +0000572#endif
bellard3fb2ded2003-06-24 13:22:59 +0000573 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard7fe48482004-10-09 18:08:01 +0000574 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000575 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000576#elif defined(TARGET_ARM)
bellard7fe48482004-10-09 18:08:01 +0000577 cpu_dump_state(env, logfile, fprintf, 0);
bellard93ac68b2003-09-30 20:57:29 +0000578#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000579 REGWPTR = env->regbase + (env->cwp * 16);
580 env->regwptr = REGWPTR;
581 cpu_dump_state(env, logfile, fprintf, 0);
bellard67867302003-11-23 17:05:30 +0000582#elif defined(TARGET_PPC)
bellard7fe48482004-10-09 18:08:01 +0000583 cpu_dump_state(env, logfile, fprintf, 0);
bellard6af0bf92005-07-02 14:58:51 +0000584#elif defined(TARGET_MIPS)
585 cpu_dump_state(env, logfile, fprintf, 0);
bellarde4533c72003-06-15 19:51:39 +0000586#else
587#error unsupported target CPU
588#endif
bellard3fb2ded2003-06-24 13:22:59 +0000589 }
bellard7d132992003-03-06 23:23:54 +0000590#endif
bellard8a40a182005-11-20 10:35:40 +0000591 tb = tb_find_fast();
bellard9d27abd2003-05-10 13:13:54 +0000592#ifdef DEBUG_EXEC
bellardc1135f62005-01-30 22:41:54 +0000593 if ((loglevel & CPU_LOG_EXEC)) {
bellardc27004e2005-01-03 23:35:10 +0000594 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
595 (long)tb->tc_ptr, tb->pc,
596 lookup_symbol(tb->pc));
bellard3fb2ded2003-06-24 13:22:59 +0000597 }
bellard9d27abd2003-05-10 13:13:54 +0000598#endif
bellard8c6939c2003-06-09 15:28:00 +0000599#ifdef __sparc__
bellard3fb2ded2003-06-24 13:22:59 +0000600 T0 = tmp_T0;
bellard8c6939c2003-06-09 15:28:00 +0000601#endif
bellard8a40a182005-11-20 10:35:40 +0000602 /* see if we can patch the calling TB. When the TB
603 spans two pages, we cannot safely do a direct
604 jump. */
bellardc27004e2005-01-03 23:35:10 +0000605 {
bellard8a40a182005-11-20 10:35:40 +0000606 if (T0 != 0 &&
607 tb->page_addr[1] == -1
bellardbf3e8bf2004-02-16 21:58:54 +0000608#if defined(TARGET_I386) && defined(USE_CODE_COPY)
609 && (tb->cflags & CF_CODE_COPY) ==
610 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
611#endif
612 ) {
bellard3fb2ded2003-06-24 13:22:59 +0000613 spin_lock(&tb_lock);
bellardc27004e2005-01-03 23:35:10 +0000614 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
bellard97eb5b12004-02-25 23:19:55 +0000615#if defined(USE_CODE_COPY)
616 /* propagates the FP use info */
617 ((TranslationBlock *)(T0 & ~3))->cflags |=
618 (tb->cflags & CF_FP_USED);
619#endif
bellard3fb2ded2003-06-24 13:22:59 +0000620 spin_unlock(&tb_lock);
621 }
bellardc27004e2005-01-03 23:35:10 +0000622 }
bellard3fb2ded2003-06-24 13:22:59 +0000623 tc_ptr = tb->tc_ptr;
bellard83479e72003-06-25 16:12:37 +0000624 env->current_tb = tb;
bellard3fb2ded2003-06-24 13:22:59 +0000625 /* execute the generated code */
626 gen_func = (void *)tc_ptr;
627#if defined(__sparc__)
628 __asm__ __volatile__("call %0\n\t"
629 "mov %%o7,%%i0"
630 : /* no outputs */
631 : "r" (gen_func)
632 : "i0", "i1", "i2", "i3", "i4", "i5");
633#elif defined(__arm__)
634 asm volatile ("mov pc, %0\n\t"
635 ".global exec_loop\n\t"
636 "exec_loop:\n\t"
637 : /* no outputs */
638 : "r" (gen_func)
639 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bellardbf3e8bf2004-02-16 21:58:54 +0000640#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
641{
642 if (!(tb->cflags & CF_CODE_COPY)) {
bellard97eb5b12004-02-25 23:19:55 +0000643 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
644 save_native_fp_state(env);
645 }
bellardbf3e8bf2004-02-16 21:58:54 +0000646 gen_func();
647 } else {
bellard97eb5b12004-02-25 23:19:55 +0000648 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
649 restore_native_fp_state(env);
650 }
bellardbf3e8bf2004-02-16 21:58:54 +0000651 /* we work with native eflags */
652 CC_SRC = cc_table[CC_OP].compute_all();
653 CC_OP = CC_OP_EFLAGS;
654 asm(".globl exec_loop\n"
655 "\n"
656 "debug1:\n"
657 " pushl %%ebp\n"
658 " fs movl %10, %9\n"
659 " fs movl %11, %%eax\n"
660 " andl $0x400, %%eax\n"
661 " fs orl %8, %%eax\n"
662 " pushl %%eax\n"
663 " popf\n"
664 " fs movl %%esp, %12\n"
665 " fs movl %0, %%eax\n"
666 " fs movl %1, %%ecx\n"
667 " fs movl %2, %%edx\n"
668 " fs movl %3, %%ebx\n"
669 " fs movl %4, %%esp\n"
670 " fs movl %5, %%ebp\n"
671 " fs movl %6, %%esi\n"
672 " fs movl %7, %%edi\n"
673 " fs jmp *%9\n"
674 "exec_loop:\n"
675 " fs movl %%esp, %4\n"
676 " fs movl %12, %%esp\n"
677 " fs movl %%eax, %0\n"
678 " fs movl %%ecx, %1\n"
679 " fs movl %%edx, %2\n"
680 " fs movl %%ebx, %3\n"
681 " fs movl %%ebp, %5\n"
682 " fs movl %%esi, %6\n"
683 " fs movl %%edi, %7\n"
684 " pushf\n"
685 " popl %%eax\n"
686 " movl %%eax, %%ecx\n"
687 " andl $0x400, %%ecx\n"
688 " shrl $9, %%ecx\n"
689 " andl $0x8d5, %%eax\n"
690 " fs movl %%eax, %8\n"
691 " movl $1, %%eax\n"
692 " subl %%ecx, %%eax\n"
693 " fs movl %%eax, %11\n"
694 " fs movl %9, %%ebx\n" /* get T0 value */
695 " popl %%ebp\n"
696 :
697 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
698 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
699 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
700 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
701 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
702 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
703 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
704 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
705 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
706 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
707 "a" (gen_func),
708 "m" (*(uint8_t *)offsetof(CPUState, df)),
709 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
710 : "%ecx", "%edx"
711 );
712 }
713}
bellardb8076a72005-04-07 22:20:31 +0000714#elif defined(__ia64)
715 struct fptr {
716 void *ip;
717 void *gp;
718 } fp;
719
720 fp.ip = tc_ptr;
721 fp.gp = code_gen_buffer + 2 * (1 << 20);
722 (*(void (*)(void)) &fp)();
bellard3fb2ded2003-06-24 13:22:59 +0000723#else
724 gen_func();
725#endif
bellard83479e72003-06-25 16:12:37 +0000726 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000727 /* reset soft MMU for next block (it can currently
728 only be set by a memory fault) */
729#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
bellard3f337312003-08-20 23:02:09 +0000730 if (env->hflags & HF_SOFTMMU_MASK) {
731 env->hflags &= ~HF_SOFTMMU_MASK;
bellard4cbf74b2003-08-10 21:48:43 +0000732 /* do not allow linking to another block */
733 T0 = 0;
734 }
735#endif
bellard3fb2ded2003-06-24 13:22:59 +0000736 }
737 } else {
bellard0d1a29f2004-10-12 22:01:28 +0000738 env_to_regs();
bellard7d132992003-03-06 23:23:54 +0000739 }
bellard3fb2ded2003-06-24 13:22:59 +0000740 } /* for(;;) */
741
bellard7d132992003-03-06 23:23:54 +0000742
bellarde4533c72003-06-15 19:51:39 +0000743#if defined(TARGET_I386)
bellard97eb5b12004-02-25 23:19:55 +0000744#if defined(USE_CODE_COPY)
745 if (env->native_fp_regs) {
746 save_native_fp_state(env);
747 }
748#endif
bellard9de5e442003-03-23 16:49:39 +0000749 /* restore flags in standard format */
bellardfc2b4c42003-03-29 16:52:44 +0000750 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard9de5e442003-03-23 16:49:39 +0000751
bellard7d132992003-03-06 23:23:54 +0000752 /* restore global registers */
bellard04369ff2003-03-20 22:33:23 +0000753#ifdef reg_EAX
754 EAX = saved_EAX;
755#endif
756#ifdef reg_ECX
757 ECX = saved_ECX;
758#endif
759#ifdef reg_EDX
760 EDX = saved_EDX;
761#endif
762#ifdef reg_EBX
763 EBX = saved_EBX;
764#endif
765#ifdef reg_ESP
766 ESP = saved_ESP;
767#endif
768#ifdef reg_EBP
769 EBP = saved_EBP;
770#endif
771#ifdef reg_ESI
772 ESI = saved_ESI;
773#endif
774#ifdef reg_EDI
775 EDI = saved_EDI;
776#endif
bellarde4533c72003-06-15 19:51:39 +0000777#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000778 /* XXX: Save/restore host fpu exception state?. */
bellard93ac68b2003-09-30 20:57:29 +0000779#elif defined(TARGET_SPARC)
bellard34751872005-07-02 14:31:34 +0000780#if defined(reg_REGWPTR)
781 REGWPTR = saved_regwptr;
782#endif
bellard67867302003-11-23 17:05:30 +0000783#elif defined(TARGET_PPC)
bellard6af0bf92005-07-02 14:58:51 +0000784#elif defined(TARGET_MIPS)
bellarde4533c72003-06-15 19:51:39 +0000785#else
786#error unsupported target CPU
787#endif
bellard8c6939c2003-06-09 15:28:00 +0000788#ifdef __sparc__
789 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
790#endif
bellard7d132992003-03-06 23:23:54 +0000791 T0 = saved_T0;
792 T1 = saved_T1;
bellard34751872005-07-02 14:31:34 +0000793#if defined(reg_T2)
bellarde4533c72003-06-15 19:51:39 +0000794 T2 = saved_T2;
bellard34751872005-07-02 14:31:34 +0000795#endif
bellard7d132992003-03-06 23:23:54 +0000796 env = saved_env;
bellard6a00d602005-11-21 23:25:50 +0000797 /* fail safe : never use cpu_single_env outside cpu_exec() */
798 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000799 return ret;
800}
bellard6dbad632003-03-16 18:05:05 +0000801
bellardfbf9eeb2004-04-25 21:21:33 +0000802/* must only be called from the generated code as an exception can be
803 generated */
804void tb_invalidate_page_range(target_ulong start, target_ulong end)
805{
bellarddc5d0b32004-06-22 18:43:30 +0000806 /* XXX: cannot enable it yet because it yields to MMU exception
807 where NIP != read address on PowerPC */
808#if 0
bellardfbf9eeb2004-04-25 21:21:33 +0000809 target_ulong phys_addr;
810 phys_addr = get_phys_addr_code(env, start);
811 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
bellarddc5d0b32004-06-22 18:43:30 +0000812#endif
bellardfbf9eeb2004-04-25 21:21:33 +0000813}
814
bellard1a18c712003-10-30 01:07:51 +0000815#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
bellarde4533c72003-06-15 19:51:39 +0000816
bellard6dbad632003-03-16 18:05:05 +0000817void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
818{
819 CPUX86State *saved_env;
820
821 saved_env = env;
822 env = s;
bellarda412ac52003-07-26 18:01:40 +0000823 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
bellarda513fe12003-05-27 23:29:48 +0000824 selector &= 0xffff;
bellard2e255c62003-08-21 23:25:21 +0000825 cpu_x86_load_seg_cache(env, seg_reg, selector,
bellardc27004e2005-01-03 23:35:10 +0000826 (selector << 4), 0xffff, 0);
bellarda513fe12003-05-27 23:29:48 +0000827 } else {
bellardb453b702004-01-04 15:45:21 +0000828 load_seg(seg_reg, selector);
bellarda513fe12003-05-27 23:29:48 +0000829 }
bellard6dbad632003-03-16 18:05:05 +0000830 env = saved_env;
831}
bellard9de5e442003-03-23 16:49:39 +0000832
bellardd0a1ffc2003-05-29 20:04:28 +0000833void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
834{
835 CPUX86State *saved_env;
836
837 saved_env = env;
838 env = s;
839
bellardc27004e2005-01-03 23:35:10 +0000840 helper_fsave((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000841
842 env = saved_env;
843}
844
845void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
846{
847 CPUX86State *saved_env;
848
849 saved_env = env;
850 env = s;
851
bellardc27004e2005-01-03 23:35:10 +0000852 helper_frstor((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000853
854 env = saved_env;
855}
856
bellarde4533c72003-06-15 19:51:39 +0000857#endif /* TARGET_I386 */
858
bellard67b915a2004-03-31 23:37:16 +0000859#if !defined(CONFIG_SOFTMMU)
860
bellard3fb2ded2003-06-24 13:22:59 +0000861#if defined(TARGET_I386)
862
bellardb56dad12003-05-08 15:38:04 +0000863/* 'pc' is the host PC at which the exception was raised. 'address' is
bellardfd6ce8f2003-05-14 19:00:11 +0000864 the effective address of the memory exception. 'is_write' is 1 if a
865 write caused the exception and otherwise 0'. 'old_set' is the
866 signal set which should be restored */
bellard2b413142003-05-14 23:01:10 +0000867static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000868 int is_write, sigset_t *old_set,
869 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000870{
bellarda513fe12003-05-27 23:29:48 +0000871 TranslationBlock *tb;
872 int ret;
bellard68a79312003-06-30 13:12:32 +0000873
bellard83479e72003-06-25 16:12:37 +0000874 if (cpu_single_env)
875 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellardfd6ce8f2003-05-14 19:00:11 +0000876#if defined(DEBUG_SIGNAL)
bellardbf3e8bf2004-02-16 21:58:54 +0000877 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
878 pc, address, is_write, *(unsigned long *)old_set);
bellard9de5e442003-03-23 16:49:39 +0000879#endif
bellard25eb4482003-05-14 21:50:54 +0000880 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +0000881 if (is_write && page_unprotect(address, pc, puc)) {
bellardfd6ce8f2003-05-14 19:00:11 +0000882 return 1;
883 }
bellardfbf9eeb2004-04-25 21:21:33 +0000884
bellard3fb2ded2003-06-24 13:22:59 +0000885 /* see if it is an MMU fault */
bellard93a40ea2003-10-27 21:13:06 +0000886 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
887 ((env->hflags & HF_CPL_MASK) == 3), 0);
bellard3fb2ded2003-06-24 13:22:59 +0000888 if (ret < 0)
889 return 0; /* not an MMU fault */
890 if (ret == 0)
891 return 1; /* the MMU fault was handled without causing real CPU fault */
892 /* now we have a real cpu fault */
bellarda513fe12003-05-27 23:29:48 +0000893 tb = tb_find_pc(pc);
894 if (tb) {
bellard9de5e442003-03-23 16:49:39 +0000895 /* the PC is inside the translated code. It means that we have
896 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000897 cpu_restore_state(tb, env, pc, puc);
bellard3fb2ded2003-06-24 13:22:59 +0000898 }
bellard4cbf74b2003-08-10 21:48:43 +0000899 if (ret == 1) {
bellard3fb2ded2003-06-24 13:22:59 +0000900#if 0
bellard4cbf74b2003-08-10 21:48:43 +0000901 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
902 env->eip, env->cr[2], env->error_code);
bellard3fb2ded2003-06-24 13:22:59 +0000903#endif
bellard4cbf74b2003-08-10 21:48:43 +0000904 /* we restore the process signal mask as the sigreturn should
905 do it (XXX: use sigsetjmp) */
906 sigprocmask(SIG_SETMASK, old_set, NULL);
907 raise_exception_err(EXCP0E_PAGE, env->error_code);
908 } else {
909 /* activate soft MMU for this block */
bellard3f337312003-08-20 23:02:09 +0000910 env->hflags |= HF_SOFTMMU_MASK;
bellardfbf9eeb2004-04-25 21:21:33 +0000911 cpu_resume_from_signal(env, puc);
bellard4cbf74b2003-08-10 21:48:43 +0000912 }
bellard3fb2ded2003-06-24 13:22:59 +0000913 /* never comes here */
914 return 1;
915}
916
bellarde4533c72003-06-15 19:51:39 +0000917#elif defined(TARGET_ARM)
bellard3fb2ded2003-06-24 13:22:59 +0000918static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000919 int is_write, sigset_t *old_set,
920 void *puc)
bellard3fb2ded2003-06-24 13:22:59 +0000921{
bellard68016c62005-02-07 23:12:27 +0000922 TranslationBlock *tb;
923 int ret;
924
925 if (cpu_single_env)
926 env = cpu_single_env; /* XXX: find a correct solution for multithread */
927#if defined(DEBUG_SIGNAL)
928 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
929 pc, address, is_write, *(unsigned long *)old_set);
930#endif
bellard9f0777e2005-02-02 20:42:01 +0000931 /* XXX: locking issue */
932 if (is_write && page_unprotect(address, pc, puc)) {
933 return 1;
934 }
bellard68016c62005-02-07 23:12:27 +0000935 /* see if it is an MMU fault */
936 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
937 if (ret < 0)
938 return 0; /* not an MMU fault */
939 if (ret == 0)
940 return 1; /* the MMU fault was handled without causing real CPU fault */
941 /* now we have a real cpu fault */
942 tb = tb_find_pc(pc);
943 if (tb) {
944 /* the PC is inside the translated code. It means that we have
945 a virtual CPU fault */
946 cpu_restore_state(tb, env, pc, puc);
947 }
948 /* we restore the process signal mask as the sigreturn should
949 do it (XXX: use sigsetjmp) */
950 sigprocmask(SIG_SETMASK, old_set, NULL);
951 cpu_loop_exit();
bellard3fb2ded2003-06-24 13:22:59 +0000952}
bellard93ac68b2003-09-30 20:57:29 +0000953#elif defined(TARGET_SPARC)
954static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000955 int is_write, sigset_t *old_set,
956 void *puc)
bellard93ac68b2003-09-30 20:57:29 +0000957{
bellard68016c62005-02-07 23:12:27 +0000958 TranslationBlock *tb;
959 int ret;
960
961 if (cpu_single_env)
962 env = cpu_single_env; /* XXX: find a correct solution for multithread */
963#if defined(DEBUG_SIGNAL)
964 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
965 pc, address, is_write, *(unsigned long *)old_set);
966#endif
bellardb453b702004-01-04 15:45:21 +0000967 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +0000968 if (is_write && page_unprotect(address, pc, puc)) {
bellardb453b702004-01-04 15:45:21 +0000969 return 1;
970 }
bellard68016c62005-02-07 23:12:27 +0000971 /* see if it is an MMU fault */
972 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
973 if (ret < 0)
974 return 0; /* not an MMU fault */
975 if (ret == 0)
976 return 1; /* the MMU fault was handled without causing real CPU fault */
977 /* now we have a real cpu fault */
978 tb = tb_find_pc(pc);
979 if (tb) {
980 /* the PC is inside the translated code. It means that we have
981 a virtual CPU fault */
982 cpu_restore_state(tb, env, pc, puc);
983 }
984 /* we restore the process signal mask as the sigreturn should
985 do it (XXX: use sigsetjmp) */
986 sigprocmask(SIG_SETMASK, old_set, NULL);
987 cpu_loop_exit();
bellard93ac68b2003-09-30 20:57:29 +0000988}
bellard67867302003-11-23 17:05:30 +0000989#elif defined (TARGET_PPC)
990static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000991 int is_write, sigset_t *old_set,
992 void *puc)
bellard67867302003-11-23 17:05:30 +0000993{
994 TranslationBlock *tb;
bellardce097762004-01-04 23:53:18 +0000995 int ret;
bellard67867302003-11-23 17:05:30 +0000996
bellard67867302003-11-23 17:05:30 +0000997 if (cpu_single_env)
998 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellard67867302003-11-23 17:05:30 +0000999#if defined(DEBUG_SIGNAL)
1000 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1001 pc, address, is_write, *(unsigned long *)old_set);
1002#endif
1003 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +00001004 if (is_write && page_unprotect(address, pc, puc)) {
bellard67867302003-11-23 17:05:30 +00001005 return 1;
1006 }
1007
bellardce097762004-01-04 23:53:18 +00001008 /* see if it is an MMU fault */
bellard7f957d22004-01-18 23:19:48 +00001009 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
bellardce097762004-01-04 23:53:18 +00001010 if (ret < 0)
1011 return 0; /* not an MMU fault */
1012 if (ret == 0)
1013 return 1; /* the MMU fault was handled without causing real CPU fault */
1014
bellard67867302003-11-23 17:05:30 +00001015 /* now we have a real cpu fault */
1016 tb = tb_find_pc(pc);
1017 if (tb) {
1018 /* the PC is inside the translated code. It means that we have
1019 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +00001020 cpu_restore_state(tb, env, pc, puc);
bellard67867302003-11-23 17:05:30 +00001021 }
bellardce097762004-01-04 23:53:18 +00001022 if (ret == 1) {
bellard67867302003-11-23 17:05:30 +00001023#if 0
bellardce097762004-01-04 23:53:18 +00001024 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1025 env->nip, env->error_code, tb);
bellard67867302003-11-23 17:05:30 +00001026#endif
1027 /* we restore the process signal mask as the sigreturn should
1028 do it (XXX: use sigsetjmp) */
bellardbf3e8bf2004-02-16 21:58:54 +00001029 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard9fddaa02004-05-21 12:59:32 +00001030 do_raise_exception_err(env->exception_index, env->error_code);
bellardce097762004-01-04 23:53:18 +00001031 } else {
1032 /* activate soft MMU for this block */
bellardfbf9eeb2004-04-25 21:21:33 +00001033 cpu_resume_from_signal(env, puc);
bellardce097762004-01-04 23:53:18 +00001034 }
bellard67867302003-11-23 17:05:30 +00001035 /* never comes here */
1036 return 1;
1037}
bellard6af0bf92005-07-02 14:58:51 +00001038
1039#elif defined (TARGET_MIPS)
1040static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1041 int is_write, sigset_t *old_set,
1042 void *puc)
1043{
1044 TranslationBlock *tb;
1045 int ret;
1046
1047 if (cpu_single_env)
1048 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1049#if defined(DEBUG_SIGNAL)
1050 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1051 pc, address, is_write, *(unsigned long *)old_set);
1052#endif
1053 /* XXX: locking issue */
1054 if (is_write && page_unprotect(address, pc, puc)) {
1055 return 1;
1056 }
1057
1058 /* see if it is an MMU fault */
bellardcc9442b2005-11-26 18:43:28 +00001059 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
bellard6af0bf92005-07-02 14:58:51 +00001060 if (ret < 0)
1061 return 0; /* not an MMU fault */
1062 if (ret == 0)
1063 return 1; /* the MMU fault was handled without causing real CPU fault */
1064
1065 /* now we have a real cpu fault */
1066 tb = tb_find_pc(pc);
1067 if (tb) {
1068 /* the PC is inside the translated code. It means that we have
1069 a virtual CPU fault */
1070 cpu_restore_state(tb, env, pc, puc);
1071 }
1072 if (ret == 1) {
1073#if 0
1074 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1075 env->nip, env->error_code, tb);
1076#endif
1077 /* we restore the process signal mask as the sigreturn should
1078 do it (XXX: use sigsetjmp) */
1079 sigprocmask(SIG_SETMASK, old_set, NULL);
1080 do_raise_exception_err(env->exception_index, env->error_code);
1081 } else {
1082 /* activate soft MMU for this block */
1083 cpu_resume_from_signal(env, puc);
1084 }
1085 /* never comes here */
1086 return 1;
1087}
1088
bellarde4533c72003-06-15 19:51:39 +00001089#else
1090#error unsupported target CPU
1091#endif
bellard9de5e442003-03-23 16:49:39 +00001092
bellard2b413142003-05-14 23:01:10 +00001093#if defined(__i386__)
1094
bellardbf3e8bf2004-02-16 21:58:54 +00001095#if defined(USE_CODE_COPY)
1096static void cpu_send_trap(unsigned long pc, int trap,
1097 struct ucontext *uc)
1098{
1099 TranslationBlock *tb;
1100
1101 if (cpu_single_env)
1102 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1103 /* now we have a real cpu fault */
1104 tb = tb_find_pc(pc);
1105 if (tb) {
1106 /* the PC is inside the translated code. It means that we have
1107 a virtual CPU fault */
1108 cpu_restore_state(tb, env, pc, uc);
1109 }
1110 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1111 raise_exception_err(trap, env->error_code);
1112}
1113#endif
1114
bellarde4533c72003-06-15 19:51:39 +00001115int cpu_signal_handler(int host_signum, struct siginfo *info,
1116 void *puc)
bellard9de5e442003-03-23 16:49:39 +00001117{
bellard9de5e442003-03-23 16:49:39 +00001118 struct ucontext *uc = puc;
1119 unsigned long pc;
bellardbf3e8bf2004-02-16 21:58:54 +00001120 int trapno;
bellard97eb5b12004-02-25 23:19:55 +00001121
bellardd691f662003-03-24 21:58:34 +00001122#ifndef REG_EIP
1123/* for glibc 2.1 */
bellardfd6ce8f2003-05-14 19:00:11 +00001124#define REG_EIP EIP
1125#define REG_ERR ERR
1126#define REG_TRAPNO TRAPNO
bellardd691f662003-03-24 21:58:34 +00001127#endif
bellardfc2b4c42003-03-29 16:52:44 +00001128 pc = uc->uc_mcontext.gregs[REG_EIP];
bellardbf3e8bf2004-02-16 21:58:54 +00001129 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1130#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1131 if (trapno == 0x00 || trapno == 0x05) {
1132 /* send division by zero or bound exception */
1133 cpu_send_trap(pc, trapno, uc);
1134 return 1;
1135 } else
1136#endif
1137 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1138 trapno == 0xe ?
1139 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1140 &uc->uc_sigmask, puc);
bellard2b413142003-05-14 23:01:10 +00001141}
1142
bellardbc51c5c2004-03-17 23:46:04 +00001143#elif defined(__x86_64__)
1144
1145int cpu_signal_handler(int host_signum, struct siginfo *info,
1146 void *puc)
1147{
1148 struct ucontext *uc = puc;
1149 unsigned long pc;
1150
1151 pc = uc->uc_mcontext.gregs[REG_RIP];
1152 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1153 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1154 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1155 &uc->uc_sigmask, puc);
1156}
1157
bellard83fb7ad2004-07-05 21:25:26 +00001158#elif defined(__powerpc__)
bellard2b413142003-05-14 23:01:10 +00001159
bellard83fb7ad2004-07-05 21:25:26 +00001160/***********************************************************************
1161 * signal context platform-specific definitions
1162 * From Wine
1163 */
1164#ifdef linux
1165/* All Registers access - only for local access */
1166# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1167/* Gpr Registers access */
1168# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1169# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1170# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1171# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1172# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1173# define LR_sig(context) REG_sig(link, context) /* Link register */
1174# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1175/* Float Registers access */
1176# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1177# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1178/* Exception Registers access */
1179# define DAR_sig(context) REG_sig(dar, context)
1180# define DSISR_sig(context) REG_sig(dsisr, context)
1181# define TRAP_sig(context) REG_sig(trap, context)
1182#endif /* linux */
1183
1184#ifdef __APPLE__
1185# include <sys/ucontext.h>
1186typedef struct ucontext SIGCONTEXT;
1187/* All Registers access - only for local access */
1188# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1189# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1190# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1191# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1192/* Gpr Registers access */
1193# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1194# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1195# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1196# define CTR_sig(context) REG_sig(ctr, context)
1197# define XER_sig(context) REG_sig(xer, context) /* Link register */
1198# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1199# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1200/* Float Registers access */
1201# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1202# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1203/* Exception Registers access */
1204# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1205# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1206# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1207#endif /* __APPLE__ */
1208
bellardd1d9f422004-07-14 17:20:55 +00001209int cpu_signal_handler(int host_signum, struct siginfo *info,
bellarde4533c72003-06-15 19:51:39 +00001210 void *puc)
bellard2b413142003-05-14 23:01:10 +00001211{
bellard25eb4482003-05-14 21:50:54 +00001212 struct ucontext *uc = puc;
bellard25eb4482003-05-14 21:50:54 +00001213 unsigned long pc;
bellard25eb4482003-05-14 21:50:54 +00001214 int is_write;
1215
bellard83fb7ad2004-07-05 21:25:26 +00001216 pc = IAR_sig(uc);
bellard25eb4482003-05-14 21:50:54 +00001217 is_write = 0;
1218#if 0
1219 /* ppc 4xx case */
bellard83fb7ad2004-07-05 21:25:26 +00001220 if (DSISR_sig(uc) & 0x00800000)
bellard25eb4482003-05-14 21:50:54 +00001221 is_write = 1;
bellard9de5e442003-03-23 16:49:39 +00001222#else
bellard83fb7ad2004-07-05 21:25:26 +00001223 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
bellard25eb4482003-05-14 21:50:54 +00001224 is_write = 1;
1225#endif
1226 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001227 is_write, &uc->uc_sigmask, puc);
bellard9de5e442003-03-23 16:49:39 +00001228}
bellard2b413142003-05-14 23:01:10 +00001229
bellard2f87c602003-06-02 20:38:09 +00001230#elif defined(__alpha__)
1231
bellarde4533c72003-06-15 19:51:39 +00001232int cpu_signal_handler(int host_signum, struct siginfo *info,
bellard2f87c602003-06-02 20:38:09 +00001233 void *puc)
1234{
1235 struct ucontext *uc = puc;
1236 uint32_t *pc = uc->uc_mcontext.sc_pc;
1237 uint32_t insn = *pc;
1238 int is_write = 0;
1239
bellard8c6939c2003-06-09 15:28:00 +00001240 /* XXX: need kernel patch to get write flag faster */
bellard2f87c602003-06-02 20:38:09 +00001241 switch (insn >> 26) {
1242 case 0x0d: // stw
1243 case 0x0e: // stb
1244 case 0x0f: // stq_u
1245 case 0x24: // stf
1246 case 0x25: // stg
1247 case 0x26: // sts
1248 case 0x27: // stt
1249 case 0x2c: // stl
1250 case 0x2d: // stq
1251 case 0x2e: // stl_c
1252 case 0x2f: // stq_c
1253 is_write = 1;
1254 }
1255
1256 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001257 is_write, &uc->uc_sigmask, puc);
bellard2f87c602003-06-02 20:38:09 +00001258}
bellard8c6939c2003-06-09 15:28:00 +00001259#elif defined(__sparc__)
1260
bellarde4533c72003-06-15 19:51:39 +00001261int cpu_signal_handler(int host_signum, struct siginfo *info,
1262 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001263{
1264 uint32_t *regs = (uint32_t *)(info + 1);
1265 void *sigmask = (regs + 20);
1266 unsigned long pc;
1267 int is_write;
1268 uint32_t insn;
1269
1270 /* XXX: is there a standard glibc define ? */
1271 pc = regs[1];
1272 /* XXX: need kernel patch to get write flag faster */
1273 is_write = 0;
1274 insn = *(uint32_t *)pc;
1275 if ((insn >> 30) == 3) {
1276 switch((insn >> 19) & 0x3f) {
1277 case 0x05: // stb
1278 case 0x06: // sth
1279 case 0x04: // st
1280 case 0x07: // std
1281 case 0x24: // stf
1282 case 0x27: // stdf
1283 case 0x25: // stfsr
1284 is_write = 1;
1285 break;
1286 }
1287 }
1288 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001289 is_write, sigmask, NULL);
bellard8c6939c2003-06-09 15:28:00 +00001290}
1291
1292#elif defined(__arm__)
1293
bellarde4533c72003-06-15 19:51:39 +00001294int cpu_signal_handler(int host_signum, struct siginfo *info,
1295 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001296{
1297 struct ucontext *uc = puc;
1298 unsigned long pc;
1299 int is_write;
1300
1301 pc = uc->uc_mcontext.gregs[R15];
1302 /* XXX: compute is_write */
1303 is_write = 0;
1304 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1305 is_write,
1306 &uc->uc_sigmask);
1307}
1308
bellard38e584a2003-08-10 22:14:22 +00001309#elif defined(__mc68000)
1310
1311int cpu_signal_handler(int host_signum, struct siginfo *info,
1312 void *puc)
1313{
1314 struct ucontext *uc = puc;
1315 unsigned long pc;
1316 int is_write;
1317
1318 pc = uc->uc_mcontext.gregs[16];
1319 /* XXX: compute is_write */
1320 is_write = 0;
1321 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1322 is_write,
bellardbf3e8bf2004-02-16 21:58:54 +00001323 &uc->uc_sigmask, puc);
bellard38e584a2003-08-10 22:14:22 +00001324}
1325
bellardb8076a72005-04-07 22:20:31 +00001326#elif defined(__ia64)
1327
1328#ifndef __ISR_VALID
1329 /* This ought to be in <bits/siginfo.h>... */
1330# define __ISR_VALID 1
1331# define si_flags _sifields._sigfault._si_pad0
1332#endif
1333
1334int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1335{
1336 struct ucontext *uc = puc;
1337 unsigned long ip;
1338 int is_write = 0;
1339
1340 ip = uc->uc_mcontext.sc_ip;
1341 switch (host_signum) {
1342 case SIGILL:
1343 case SIGFPE:
1344 case SIGSEGV:
1345 case SIGBUS:
1346 case SIGTRAP:
1347 if (info->si_code && (info->si_flags & __ISR_VALID))
1348 /* ISR.W (write-access) is bit 33: */
1349 is_write = (info->si_isr >> 33) & 1;
1350 break;
1351
1352 default:
1353 break;
1354 }
1355 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1356 is_write,
1357 &uc->uc_sigmask, puc);
1358}
1359
bellard90cb9492005-07-24 15:11:38 +00001360#elif defined(__s390__)
1361
1362int cpu_signal_handler(int host_signum, struct siginfo *info,
1363 void *puc)
1364{
1365 struct ucontext *uc = puc;
1366 unsigned long pc;
1367 int is_write;
1368
1369 pc = uc->uc_mcontext.psw.addr;
1370 /* XXX: compute is_write */
1371 is_write = 0;
1372 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1373 is_write,
1374 &uc->uc_sigmask, puc);
1375}
1376
bellard2b413142003-05-14 23:01:10 +00001377#else
1378
bellard3fb2ded2003-06-24 13:22:59 +00001379#error host CPU specific signal handler needed
bellard2b413142003-05-14 23:01:10 +00001380
1381#endif
bellard67b915a2004-03-31 23:37:16 +00001382
1383#endif /* !defined(CONFIG_SOFTMMU) */