bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
| 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 19 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 20 | #include "config.h" |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 21 | #include "exec.h" |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 22 | #include "disas.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 23 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 24 | #if !defined(CONFIG_SOFTMMU) |
| 25 | #undef EAX |
| 26 | #undef ECX |
| 27 | #undef EDX |
| 28 | #undef EBX |
| 29 | #undef ESP |
| 30 | #undef EBP |
| 31 | #undef ESI |
| 32 | #undef EDI |
| 33 | #undef EIP |
| 34 | #include <signal.h> |
| 35 | #include <sys/ucontext.h> |
| 36 | #endif |
| 37 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 38 | int tb_invalidated_flag; |
| 39 | |
bellard | dc99065 | 2003-03-19 00:00:28 +0000 | [diff] [blame] | 40 | //#define DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 41 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 42 | |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \ |
| 44 | defined(TARGET_ALPHA) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 45 | /* XXX: unify with i386 target */ |
| 46 | void cpu_loop_exit(void) |
| 47 | { |
| 48 | longjmp(env->jmp_env, 1); |
| 49 | } |
| 50 | #endif |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 51 | #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K)) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 52 | #define reg_T2 |
| 53 | #endif |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 54 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 55 | /* exit the current TB from a signal handler. The host registers are |
| 56 | restored in a state compatible with the CPU emulator |
| 57 | */ |
| 58 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
| 59 | { |
| 60 | #if !defined(CONFIG_SOFTMMU) |
| 61 | struct ucontext *uc = puc; |
| 62 | #endif |
| 63 | |
| 64 | env = env1; |
| 65 | |
| 66 | /* XXX: restore cpu registers saved in host registers */ |
| 67 | |
| 68 | #if !defined(CONFIG_SOFTMMU) |
| 69 | if (puc) { |
| 70 | /* XXX: use siglongjmp ? */ |
| 71 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 72 | } |
| 73 | #endif |
| 74 | longjmp(env->jmp_env, 1); |
| 75 | } |
| 76 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 77 | |
| 78 | static TranslationBlock *tb_find_slow(target_ulong pc, |
| 79 | target_ulong cs_base, |
| 80 | unsigned int flags) |
| 81 | { |
| 82 | TranslationBlock *tb, **ptb1; |
| 83 | int code_gen_size; |
| 84 | unsigned int h; |
| 85 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
| 86 | uint8_t *tc_ptr; |
| 87 | |
| 88 | spin_lock(&tb_lock); |
| 89 | |
| 90 | tb_invalidated_flag = 0; |
| 91 | |
| 92 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ |
| 93 | |
| 94 | /* find translated block using physical mappings */ |
| 95 | phys_pc = get_phys_addr_code(env, pc); |
| 96 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
| 97 | phys_page2 = -1; |
| 98 | h = tb_phys_hash_func(phys_pc); |
| 99 | ptb1 = &tb_phys_hash[h]; |
| 100 | for(;;) { |
| 101 | tb = *ptb1; |
| 102 | if (!tb) |
| 103 | goto not_found; |
| 104 | if (tb->pc == pc && |
| 105 | tb->page_addr[0] == phys_page1 && |
| 106 | tb->cs_base == cs_base && |
| 107 | tb->flags == flags) { |
| 108 | /* check next page if needed */ |
| 109 | if (tb->page_addr[1] != -1) { |
| 110 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
| 111 | TARGET_PAGE_SIZE; |
| 112 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 113 | if (tb->page_addr[1] == phys_page2) |
| 114 | goto found; |
| 115 | } else { |
| 116 | goto found; |
| 117 | } |
| 118 | } |
| 119 | ptb1 = &tb->phys_hash_next; |
| 120 | } |
| 121 | not_found: |
| 122 | /* if no translated code available, then translate it now */ |
| 123 | tb = tb_alloc(pc); |
| 124 | if (!tb) { |
| 125 | /* flush must be done */ |
| 126 | tb_flush(env); |
| 127 | /* cannot fail at this point */ |
| 128 | tb = tb_alloc(pc); |
| 129 | /* don't forget to invalidate previous TB info */ |
bellard | 1538800 | 2005-12-19 01:42:32 +0000 | [diff] [blame] | 130 | tb_invalidated_flag = 1; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 131 | } |
| 132 | tc_ptr = code_gen_ptr; |
| 133 | tb->tc_ptr = tc_ptr; |
| 134 | tb->cs_base = cs_base; |
| 135 | tb->flags = flags; |
| 136 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
| 137 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
| 138 | |
| 139 | /* check next page if needed */ |
| 140 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
| 141 | phys_page2 = -1; |
| 142 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
| 143 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 144 | } |
| 145 | tb_link_phys(tb, phys_pc, phys_page2); |
| 146 | |
| 147 | found: |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 148 | /* we add the TB in the virtual pc hash table */ |
| 149 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
| 150 | spin_unlock(&tb_lock); |
| 151 | return tb; |
| 152 | } |
| 153 | |
| 154 | static inline TranslationBlock *tb_find_fast(void) |
| 155 | { |
| 156 | TranslationBlock *tb; |
| 157 | target_ulong cs_base, pc; |
| 158 | unsigned int flags; |
| 159 | |
| 160 | /* we record a subset of the CPU state. It will |
| 161 | always be the same before a given translated block |
| 162 | is executed. */ |
| 163 | #if defined(TARGET_I386) |
| 164 | flags = env->hflags; |
| 165 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
| 166 | cs_base = env->segs[R_CS].base; |
| 167 | pc = cs_base + env->eip; |
| 168 | #elif defined(TARGET_ARM) |
| 169 | flags = env->thumb | (env->vfp.vec_len << 1) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 170 | | (env->vfp.vec_stride << 4); |
| 171 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) |
| 172 | flags |= (1 << 6); |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 173 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
| 174 | flags |= (1 << 7); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 175 | cs_base = 0; |
| 176 | pc = env->regs[15]; |
| 177 | #elif defined(TARGET_SPARC) |
| 178 | #ifdef TARGET_SPARC64 |
bellard | a80dde0 | 2006-06-26 19:53:29 +0000 | [diff] [blame] | 179 | // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled |
| 180 | flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
| 181 | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 182 | #else |
bellard | a80dde0 | 2006-06-26 19:53:29 +0000 | [diff] [blame] | 183 | // FPU enable . MMU enabled . MMU no-fault . Supervisor |
| 184 | flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) |
| 185 | | env->psrs; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 186 | #endif |
| 187 | cs_base = env->npc; |
| 188 | pc = env->pc; |
| 189 | #elif defined(TARGET_PPC) |
| 190 | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
| 191 | (msr_se << MSR_SE) | (msr_le << MSR_LE); |
| 192 | cs_base = 0; |
| 193 | pc = env->nip; |
| 194 | #elif defined(TARGET_MIPS) |
pbrook | 56b1940 | 2006-03-11 16:23:39 +0000 | [diff] [blame] | 195 | flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
bellard | cc9442b | 2005-11-26 18:43:28 +0000 | [diff] [blame] | 196 | cs_base = 0; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 197 | pc = env->PC; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 198 | #elif defined(TARGET_M68K) |
| 199 | flags = env->fpcr & M68K_FPCR_PREC; |
| 200 | cs_base = 0; |
| 201 | pc = env->pc; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 202 | #elif defined(TARGET_SH4) |
| 203 | flags = env->sr & (SR_MD | SR_RB); |
| 204 | cs_base = 0; /* XXXXX */ |
| 205 | pc = env->pc; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 206 | #elif defined(TARGET_ALPHA) |
| 207 | flags = env->ps; |
| 208 | cs_base = 0; |
| 209 | pc = env->pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 210 | #else |
| 211 | #error unsupported CPU |
| 212 | #endif |
| 213 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
| 214 | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || |
| 215 | tb->flags != flags, 0)) { |
| 216 | tb = tb_find_slow(pc, cs_base, flags); |
bellard | 1538800 | 2005-12-19 01:42:32 +0000 | [diff] [blame] | 217 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
| 218 | doing it in tb_find_slow */ |
| 219 | if (tb_invalidated_flag) { |
| 220 | /* as some TB could have been invalidated because |
| 221 | of memory exceptions while generating the code, we |
| 222 | must recompute the hash index here */ |
| 223 | T0 = 0; |
| 224 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 225 | } |
| 226 | return tb; |
| 227 | } |
| 228 | |
| 229 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 230 | /* main execution loop */ |
| 231 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 232 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 233 | { |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 234 | #define DECLARE_HOST_REGS 1 |
| 235 | #include "hostregs_helper.h" |
| 236 | #if defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 237 | #if defined(reg_REGWPTR) |
| 238 | uint32_t *saved_regwptr; |
| 239 | #endif |
| 240 | #endif |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 241 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
ths | b49d07b | 2007-02-02 03:57:09 +0000 | [diff] [blame] | 242 | int saved_i7; |
| 243 | target_ulong tmp_T0; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 244 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 245 | int ret, interrupt_request; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 246 | void (*gen_func)(void); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 247 | TranslationBlock *tb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 248 | uint8_t *tc_ptr; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 249 | |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 250 | #if defined(TARGET_I386) |
| 251 | /* handle exit of HALTED state */ |
| 252 | if (env1->hflags & HF_HALTED_MASK) { |
| 253 | /* disable halt condition */ |
| 254 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && |
| 255 | (env1->eflags & IF_MASK)) { |
| 256 | env1->hflags &= ~HF_HALTED_MASK; |
| 257 | } else { |
| 258 | return EXCP_HALTED; |
| 259 | } |
| 260 | } |
bellard | e80e1cc | 2005-11-23 22:05:28 +0000 | [diff] [blame] | 261 | #elif defined(TARGET_PPC) |
bellard | 50443c9 | 2005-11-26 20:15:14 +0000 | [diff] [blame] | 262 | if (env1->halted) { |
bellard | e80e1cc | 2005-11-23 22:05:28 +0000 | [diff] [blame] | 263 | if (env1->msr[MSR_EE] && |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 264 | (env1->interrupt_request & CPU_INTERRUPT_HARD)) { |
bellard | 50443c9 | 2005-11-26 20:15:14 +0000 | [diff] [blame] | 265 | env1->halted = 0; |
bellard | e80e1cc | 2005-11-23 22:05:28 +0000 | [diff] [blame] | 266 | } else { |
| 267 | return EXCP_HALTED; |
| 268 | } |
| 269 | } |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 270 | #elif defined(TARGET_SPARC) |
| 271 | if (env1->halted) { |
| 272 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && |
| 273 | (env1->psret != 0)) { |
| 274 | env1->halted = 0; |
| 275 | } else { |
| 276 | return EXCP_HALTED; |
| 277 | } |
| 278 | } |
bellard | 9332f9d | 2005-11-26 10:46:39 +0000 | [diff] [blame] | 279 | #elif defined(TARGET_ARM) |
| 280 | if (env1->halted) { |
| 281 | /* An interrupt wakes the CPU even if the I and F CPSR bits are |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 282 | set. We use EXITTB to silently wake CPU without causing an |
| 283 | actual interrupt. */ |
| 284 | if (env1->interrupt_request & |
| 285 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) { |
bellard | 9332f9d | 2005-11-26 10:46:39 +0000 | [diff] [blame] | 286 | env1->halted = 0; |
| 287 | } else { |
| 288 | return EXCP_HALTED; |
| 289 | } |
| 290 | } |
bellard | 6810e15 | 2005-12-05 19:59:05 +0000 | [diff] [blame] | 291 | #elif defined(TARGET_MIPS) |
| 292 | if (env1->halted) { |
| 293 | if (env1->interrupt_request & |
| 294 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
| 295 | env1->halted = 0; |
| 296 | } else { |
| 297 | return EXCP_HALTED; |
| 298 | } |
| 299 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 300 | #elif defined(TARGET_ALPHA) |
| 301 | if (env1->halted) { |
| 302 | if (env1->interrupt_request & CPU_INTERRUPT_HARD) { |
| 303 | env1->halted = 0; |
| 304 | } else { |
| 305 | return EXCP_HALTED; |
| 306 | } |
| 307 | } |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 308 | #endif |
| 309 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 310 | cpu_single_env = env1; |
| 311 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 312 | /* first we save global registers */ |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 313 | #define SAVE_HOST_REGS 1 |
| 314 | #include "hostregs_helper.h" |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 315 | env = env1; |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 316 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 317 | /* we also save i7 because longjmp may not restore it */ |
| 318 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 319 | #endif |
| 320 | |
| 321 | #if defined(TARGET_I386) |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 322 | env_to_regs(); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 323 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 324 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 325 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 326 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 327 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 328 | #elif defined(TARGET_ARM) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 329 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 330 | #if defined(reg_REGWPTR) |
| 331 | saved_regwptr = REGWPTR; |
| 332 | #endif |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 333 | #elif defined(TARGET_PPC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 334 | #elif defined(TARGET_M68K) |
| 335 | env->cc_op = CC_OP_FLAGS; |
| 336 | env->cc_dest = env->sr & 0xf; |
| 337 | env->cc_x = (env->sr >> 4) & 1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 338 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 339 | #elif defined(TARGET_SH4) |
| 340 | /* XXXXX */ |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 341 | #elif defined(TARGET_ALPHA) |
| 342 | env_to_regs(); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 343 | #else |
| 344 | #error unsupported target CPU |
| 345 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 346 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 347 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 348 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 349 | for(;;) { |
| 350 | if (setjmp(env->jmp_env) == 0) { |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 351 | env->current_tb = NULL; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 352 | /* if an exception is pending, we execute it here */ |
| 353 | if (env->exception_index >= 0) { |
| 354 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 355 | /* exit request from the cpu execution loop */ |
| 356 | ret = env->exception_index; |
| 357 | break; |
| 358 | } else if (env->user_mode_only) { |
| 359 | /* if user mode only, we simulate a fake exception |
ths | 9f08349 | 2006-12-07 18:28:42 +0000 | [diff] [blame] | 360 | which will be handled outside the cpu execution |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 361 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 362 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 363 | do_interrupt_user(env->exception_index, |
| 364 | env->exception_is_int, |
| 365 | env->error_code, |
| 366 | env->exception_next_eip); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 367 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 368 | ret = env->exception_index; |
| 369 | break; |
| 370 | } else { |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 371 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 372 | /* simulate a real cpu exception. On i386, it can |
| 373 | trigger new exceptions, but we do not handle |
| 374 | double or triple faults yet. */ |
| 375 | do_interrupt(env->exception_index, |
| 376 | env->exception_is_int, |
| 377 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 378 | env->exception_next_eip, 0); |
ths | 678dde1 | 2007-03-31 20:28:52 +0000 | [diff] [blame] | 379 | /* successfully delivered */ |
| 380 | env->old_exception = -1; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 381 | #elif defined(TARGET_PPC) |
| 382 | do_interrupt(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 383 | #elif defined(TARGET_MIPS) |
| 384 | do_interrupt(env); |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 385 | #elif defined(TARGET_SPARC) |
bellard | 1a0c329 | 2005-02-13 19:02:07 +0000 | [diff] [blame] | 386 | do_interrupt(env->exception_index); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 387 | #elif defined(TARGET_ARM) |
| 388 | do_interrupt(env); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 389 | #elif defined(TARGET_SH4) |
| 390 | do_interrupt(env); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 391 | #elif defined(TARGET_ALPHA) |
| 392 | do_interrupt(env); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 393 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 394 | } |
| 395 | env->exception_index = -1; |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 396 | } |
| 397 | #ifdef USE_KQEMU |
| 398 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
| 399 | int ret; |
| 400 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
| 401 | ret = kqemu_cpu_exec(env); |
| 402 | /* put eflags in CPU temporary format */ |
| 403 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 404 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 405 | CC_OP = CC_OP_EFLAGS; |
| 406 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 407 | if (ret == 1) { |
| 408 | /* exception */ |
| 409 | longjmp(env->jmp_env, 1); |
| 410 | } else if (ret == 2) { |
| 411 | /* softmmu execution needed */ |
| 412 | } else { |
| 413 | if (env->interrupt_request != 0) { |
| 414 | /* hardware interrupt will be executed just after */ |
| 415 | } else { |
| 416 | /* otherwise, we restart */ |
| 417 | longjmp(env->jmp_env, 1); |
| 418 | } |
| 419 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 420 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 421 | #endif |
| 422 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 423 | T0 = 0; /* force lookup of first TB */ |
| 424 | for(;;) { |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 425 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 426 | /* g1 can be modified by some libc? functions */ |
| 427 | tmp_T0 = T0; |
| 428 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 429 | interrupt_request = env->interrupt_request; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 430 | if (__builtin_expect(interrupt_request, 0)) { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 431 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
| 432 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
| 433 | env->exception_index = EXCP_DEBUG; |
| 434 | cpu_loop_exit(); |
| 435 | } |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 436 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
| 437 | defined(TARGET_PPC) || defined(TARGET_ALPHA) |
| 438 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
| 439 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 440 | env->halted = 1; |
| 441 | env->exception_index = EXCP_HLT; |
| 442 | cpu_loop_exit(); |
| 443 | } |
| 444 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 445 | #if defined(TARGET_I386) |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 446 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
| 447 | !(env->hflags & HF_SMM_MASK)) { |
| 448 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
| 449 | do_smm_enter(); |
| 450 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
| 451 | tmp_T0 = 0; |
| 452 | #else |
| 453 | T0 = 0; |
| 454 | #endif |
| 455 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 456 | (env->eflags & IF_MASK) && |
| 457 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 458 | int intno; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 459 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 460 | intno = cpu_get_pic_interrupt(env); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 461 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 462 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
| 463 | } |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 464 | do_interrupt(intno, 0, 0, 0, 1); |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 465 | /* ensure that no TB jump will be modified as |
| 466 | the program flow was changed */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 467 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 468 | tmp_T0 = 0; |
| 469 | #else |
| 470 | T0 = 0; |
| 471 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 472 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 473 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 474 | #if 0 |
| 475 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
| 476 | cpu_ppc_reset(env); |
| 477 | } |
| 478 | #endif |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 479 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 480 | ppc_hw_interrupt(env); |
| 481 | if (env->pending_interrupts == 0) |
| 482 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 483 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 484 | tmp_T0 = 0; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 485 | #else |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 486 | T0 = 0; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 487 | #endif |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 488 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 489 | #elif defined(TARGET_MIPS) |
| 490 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 491 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 492 | (env->CP0_Status & (1 << CP0St_IE)) && |
ths | 24c7b0e | 2007-03-30 16:44:54 +0000 | [diff] [blame] | 493 | !(env->CP0_Status & (1 << CP0St_EXL)) && |
| 494 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 495 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 496 | /* Raise it */ |
| 497 | env->exception_index = EXCP_EXT_INTERRUPT; |
| 498 | env->error_code = 0; |
| 499 | do_interrupt(env); |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 500 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 501 | tmp_T0 = 0; |
| 502 | #else |
| 503 | T0 = 0; |
| 504 | #endif |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 505 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 506 | #elif defined(TARGET_SPARC) |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 507 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 508 | (env->psret != 0)) { |
| 509 | int pil = env->interrupt_index & 15; |
| 510 | int type = env->interrupt_index & 0xf0; |
| 511 | |
| 512 | if (((type == TT_EXTINT) && |
| 513 | (pil == 15 || pil > env->psrpil)) || |
| 514 | type != TT_EXTINT) { |
| 515 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 516 | do_interrupt(env->interrupt_index); |
| 517 | env->interrupt_index = 0; |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 518 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 519 | tmp_T0 = 0; |
| 520 | #else |
| 521 | T0 = 0; |
| 522 | #endif |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 523 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 524 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 525 | //do_interrupt(0, 0, 0, 0, 0); |
| 526 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 527 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 528 | #elif defined(TARGET_ARM) |
| 529 | if (interrupt_request & CPU_INTERRUPT_FIQ |
| 530 | && !(env->uncached_cpsr & CPSR_F)) { |
| 531 | env->exception_index = EXCP_FIQ; |
| 532 | do_interrupt(env); |
| 533 | } |
| 534 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 535 | && !(env->uncached_cpsr & CPSR_I)) { |
| 536 | env->exception_index = EXCP_IRQ; |
| 537 | do_interrupt(env); |
| 538 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 539 | #elif defined(TARGET_SH4) |
| 540 | /* XXXXX */ |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 541 | #elif defined(TARGET_ALPHA) |
| 542 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 543 | do_interrupt(env); |
| 544 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 545 | #endif |
bellard | 9d05095 | 2006-05-22 22:03:52 +0000 | [diff] [blame] | 546 | /* Don't use the cached interupt_request value, |
| 547 | do_interrupt may have updated the EXITTB flag. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 548 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 549 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
| 550 | /* ensure that no TB jump will be modified as |
| 551 | the program flow was changed */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 552 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 553 | tmp_T0 = 0; |
| 554 | #else |
| 555 | T0 = 0; |
| 556 | #endif |
| 557 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 558 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
| 559 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
| 560 | env->exception_index = EXCP_INTERRUPT; |
| 561 | cpu_loop_exit(); |
| 562 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 563 | } |
| 564 | #ifdef DEBUG_EXEC |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 565 | if ((loglevel & CPU_LOG_TB_CPU)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 566 | #if defined(TARGET_I386) |
| 567 | /* restore flags in standard format */ |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 568 | #ifdef reg_EAX |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 569 | env->regs[R_EAX] = EAX; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 570 | #endif |
| 571 | #ifdef reg_EBX |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 572 | env->regs[R_EBX] = EBX; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 573 | #endif |
| 574 | #ifdef reg_ECX |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 575 | env->regs[R_ECX] = ECX; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 576 | #endif |
| 577 | #ifdef reg_EDX |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 578 | env->regs[R_EDX] = EDX; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 579 | #endif |
| 580 | #ifdef reg_ESI |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 581 | env->regs[R_ESI] = ESI; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 582 | #endif |
| 583 | #ifdef reg_EDI |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 584 | env->regs[R_EDI] = EDI; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 585 | #endif |
| 586 | #ifdef reg_EBP |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 587 | env->regs[R_EBP] = EBP; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 588 | #endif |
| 589 | #ifdef reg_ESP |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 590 | env->regs[R_ESP] = ESP; |
bellard | fc9f715 | 2005-04-26 19:33:35 +0000 | [diff] [blame] | 591 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 592 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 593 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 594 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 595 | #elif defined(TARGET_ARM) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 596 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 597 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 598 | REGWPTR = env->regbase + (env->cwp * 16); |
| 599 | env->regwptr = REGWPTR; |
| 600 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 601 | #elif defined(TARGET_PPC) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 602 | cpu_dump_state(env, logfile, fprintf, 0); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 603 | #elif defined(TARGET_M68K) |
| 604 | cpu_m68k_flush_flags(env, env->cc_op); |
| 605 | env->cc_op = CC_OP_FLAGS; |
| 606 | env->sr = (env->sr & 0xffe0) |
| 607 | | env->cc_dest | (env->cc_x << 4); |
| 608 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 609 | #elif defined(TARGET_MIPS) |
| 610 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 611 | #elif defined(TARGET_SH4) |
| 612 | cpu_dump_state(env, logfile, fprintf, 0); |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 613 | #elif defined(TARGET_ALPHA) |
| 614 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 615 | #else |
| 616 | #error unsupported target CPU |
| 617 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 618 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 619 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 620 | tb = tb_find_fast(); |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 621 | #ifdef DEBUG_EXEC |
bellard | c1135f6 | 2005-01-30 22:41:54 +0000 | [diff] [blame] | 622 | if ((loglevel & CPU_LOG_EXEC)) { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 623 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
| 624 | (long)tb->tc_ptr, tb->pc, |
| 625 | lookup_symbol(tb->pc)); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 626 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 627 | #endif |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 628 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 629 | T0 = tmp_T0; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 630 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 631 | /* see if we can patch the calling TB. When the TB |
| 632 | spans two pages, we cannot safely do a direct |
| 633 | jump. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 634 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 635 | if (T0 != 0 && |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 636 | #if USE_KQEMU |
| 637 | (env->kqemu_enabled != 2) && |
| 638 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 639 | tb->page_addr[1] == -1 |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 640 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 641 | && (tb->cflags & CF_CODE_COPY) == |
| 642 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) |
| 643 | #endif |
| 644 | ) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 645 | spin_lock(&tb_lock); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 646 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 647 | #if defined(USE_CODE_COPY) |
| 648 | /* propagates the FP use info */ |
| 649 | ((TranslationBlock *)(T0 & ~3))->cflags |= |
| 650 | (tb->cflags & CF_FP_USED); |
| 651 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 652 | spin_unlock(&tb_lock); |
| 653 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 654 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 655 | tc_ptr = tb->tc_ptr; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 656 | env->current_tb = tb; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 657 | /* execute the generated code */ |
| 658 | gen_func = (void *)tc_ptr; |
| 659 | #if defined(__sparc__) |
| 660 | __asm__ __volatile__("call %0\n\t" |
| 661 | "mov %%o7,%%i0" |
| 662 | : /* no outputs */ |
| 663 | : "r" (gen_func) |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 664 | : "i0", "i1", "i2", "i3", "i4", "i5", |
ths | faab759 | 2007-03-19 20:39:49 +0000 | [diff] [blame] | 665 | "o0", "o1", "o2", "o3", "o4", "o5", |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 666 | "l0", "l1", "l2", "l3", "l4", "l5", |
| 667 | "l6", "l7"); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 668 | #elif defined(__arm__) |
| 669 | asm volatile ("mov pc, %0\n\t" |
| 670 | ".global exec_loop\n\t" |
| 671 | "exec_loop:\n\t" |
| 672 | : /* no outputs */ |
| 673 | : "r" (gen_func) |
| 674 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 675 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 676 | { |
| 677 | if (!(tb->cflags & CF_CODE_COPY)) { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 678 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
| 679 | save_native_fp_state(env); |
| 680 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 681 | gen_func(); |
| 682 | } else { |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 683 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
| 684 | restore_native_fp_state(env); |
| 685 | } |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 686 | /* we work with native eflags */ |
| 687 | CC_SRC = cc_table[CC_OP].compute_all(); |
| 688 | CC_OP = CC_OP_EFLAGS; |
| 689 | asm(".globl exec_loop\n" |
| 690 | "\n" |
| 691 | "debug1:\n" |
| 692 | " pushl %%ebp\n" |
| 693 | " fs movl %10, %9\n" |
| 694 | " fs movl %11, %%eax\n" |
| 695 | " andl $0x400, %%eax\n" |
| 696 | " fs orl %8, %%eax\n" |
| 697 | " pushl %%eax\n" |
| 698 | " popf\n" |
| 699 | " fs movl %%esp, %12\n" |
| 700 | " fs movl %0, %%eax\n" |
| 701 | " fs movl %1, %%ecx\n" |
| 702 | " fs movl %2, %%edx\n" |
| 703 | " fs movl %3, %%ebx\n" |
| 704 | " fs movl %4, %%esp\n" |
| 705 | " fs movl %5, %%ebp\n" |
| 706 | " fs movl %6, %%esi\n" |
| 707 | " fs movl %7, %%edi\n" |
| 708 | " fs jmp *%9\n" |
| 709 | "exec_loop:\n" |
| 710 | " fs movl %%esp, %4\n" |
| 711 | " fs movl %12, %%esp\n" |
| 712 | " fs movl %%eax, %0\n" |
| 713 | " fs movl %%ecx, %1\n" |
| 714 | " fs movl %%edx, %2\n" |
| 715 | " fs movl %%ebx, %3\n" |
| 716 | " fs movl %%ebp, %5\n" |
| 717 | " fs movl %%esi, %6\n" |
| 718 | " fs movl %%edi, %7\n" |
| 719 | " pushf\n" |
| 720 | " popl %%eax\n" |
| 721 | " movl %%eax, %%ecx\n" |
| 722 | " andl $0x400, %%ecx\n" |
| 723 | " shrl $9, %%ecx\n" |
| 724 | " andl $0x8d5, %%eax\n" |
| 725 | " fs movl %%eax, %8\n" |
| 726 | " movl $1, %%eax\n" |
| 727 | " subl %%ecx, %%eax\n" |
| 728 | " fs movl %%eax, %11\n" |
| 729 | " fs movl %9, %%ebx\n" /* get T0 value */ |
| 730 | " popl %%ebp\n" |
| 731 | : |
| 732 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
| 733 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
| 734 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
| 735 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
| 736 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
| 737 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
| 738 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
| 739 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
| 740 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), |
| 741 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), |
| 742 | "a" (gen_func), |
| 743 | "m" (*(uint8_t *)offsetof(CPUState, df)), |
| 744 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) |
| 745 | : "%ecx", "%edx" |
| 746 | ); |
| 747 | } |
| 748 | } |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 749 | #elif defined(__ia64) |
| 750 | struct fptr { |
| 751 | void *ip; |
| 752 | void *gp; |
| 753 | } fp; |
| 754 | |
| 755 | fp.ip = tc_ptr; |
| 756 | fp.gp = code_gen_buffer + 2 * (1 << 20); |
| 757 | (*(void (*)(void)) &fp)(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 758 | #else |
| 759 | gen_func(); |
| 760 | #endif |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 761 | env->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 762 | /* reset soft MMU for next block (it can currently |
| 763 | only be set by a memory fault) */ |
| 764 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 765 | if (env->hflags & HF_SOFTMMU_MASK) { |
| 766 | env->hflags &= ~HF_SOFTMMU_MASK; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 767 | /* do not allow linking to another block */ |
| 768 | T0 = 0; |
| 769 | } |
| 770 | #endif |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 771 | #if defined(USE_KQEMU) |
| 772 | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) |
| 773 | if (kqemu_is_ok(env) && |
| 774 | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { |
| 775 | cpu_loop_exit(); |
| 776 | } |
| 777 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 778 | } |
| 779 | } else { |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 780 | env_to_regs(); |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 781 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 782 | } /* for(;;) */ |
| 783 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 784 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 785 | #if defined(TARGET_I386) |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 786 | #if defined(USE_CODE_COPY) |
| 787 | if (env->native_fp_regs) { |
| 788 | save_native_fp_state(env); |
| 789 | } |
| 790 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 791 | /* restore flags in standard format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 792 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 793 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 794 | /* XXX: Save/restore host fpu exception state?. */ |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 795 | #elif defined(TARGET_SPARC) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 796 | #if defined(reg_REGWPTR) |
| 797 | REGWPTR = saved_regwptr; |
| 798 | #endif |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 799 | #elif defined(TARGET_PPC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 800 | #elif defined(TARGET_M68K) |
| 801 | cpu_m68k_flush_flags(env, env->cc_op); |
| 802 | env->cc_op = CC_OP_FLAGS; |
| 803 | env->sr = (env->sr & 0xffe0) |
| 804 | | env->cc_dest | (env->cc_x << 4); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 805 | #elif defined(TARGET_MIPS) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 806 | #elif defined(TARGET_SH4) |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 807 | #elif defined(TARGET_ALPHA) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 808 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 809 | #else |
| 810 | #error unsupported target CPU |
| 811 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 812 | |
| 813 | /* restore global registers */ |
bellard | fdbb469 | 2006-06-14 17:32:25 +0000 | [diff] [blame] | 814 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 815 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 816 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 817 | #include "hostregs_helper.h" |
| 818 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 819 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
| 820 | cpu_single_env = NULL; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 821 | return ret; |
| 822 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 823 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 824 | /* must only be called from the generated code as an exception can be |
| 825 | generated */ |
| 826 | void tb_invalidate_page_range(target_ulong start, target_ulong end) |
| 827 | { |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 828 | /* XXX: cannot enable it yet because it yields to MMU exception |
| 829 | where NIP != read address on PowerPC */ |
| 830 | #if 0 |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 831 | target_ulong phys_addr; |
| 832 | phys_addr = get_phys_addr_code(env, start); |
| 833 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); |
bellard | dc5d0b3 | 2004-06-22 18:43:30 +0000 | [diff] [blame] | 834 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 835 | } |
| 836 | |
bellard | 1a18c71 | 2003-10-30 01:07:51 +0000 | [diff] [blame] | 837 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 838 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 839 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 840 | { |
| 841 | CPUX86State *saved_env; |
| 842 | |
| 843 | saved_env = env; |
| 844 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 845 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 846 | selector &= 0xffff; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 847 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 848 | (selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 849 | } else { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 850 | load_seg(seg_reg, selector); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 851 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 852 | env = saved_env; |
| 853 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 854 | |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 855 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 856 | { |
| 857 | CPUX86State *saved_env; |
| 858 | |
| 859 | saved_env = env; |
| 860 | env = s; |
| 861 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 862 | helper_fsave((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 863 | |
| 864 | env = saved_env; |
| 865 | } |
| 866 | |
| 867 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 868 | { |
| 869 | CPUX86State *saved_env; |
| 870 | |
| 871 | saved_env = env; |
| 872 | env = s; |
| 873 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 874 | helper_frstor((target_ulong)ptr, data32); |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 875 | |
| 876 | env = saved_env; |
| 877 | } |
| 878 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 879 | #endif /* TARGET_I386 */ |
| 880 | |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 881 | #if !defined(CONFIG_SOFTMMU) |
| 882 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 883 | #if defined(TARGET_I386) |
| 884 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 885 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 886 | the effective address of the memory exception. 'is_write' is 1 if a |
| 887 | write caused the exception and otherwise 0'. 'old_set' is the |
| 888 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 889 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 890 | int is_write, sigset_t *old_set, |
| 891 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 892 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 893 | TranslationBlock *tb; |
| 894 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 895 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 896 | if (cpu_single_env) |
| 897 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 898 | #if defined(DEBUG_SIGNAL) |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 899 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 900 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 901 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 902 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 903 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 904 | return 1; |
| 905 | } |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 906 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 907 | /* see if it is an MMU fault */ |
bellard | 93a40ea | 2003-10-27 21:13:06 +0000 | [diff] [blame] | 908 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
| 909 | ((env->hflags & HF_CPL_MASK) == 3), 0); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 910 | if (ret < 0) |
| 911 | return 0; /* not an MMU fault */ |
| 912 | if (ret == 0) |
| 913 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 914 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 915 | tb = tb_find_pc(pc); |
| 916 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 917 | /* the PC is inside the translated code. It means that we have |
| 918 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 919 | cpu_restore_state(tb, env, pc, puc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 920 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 921 | if (ret == 1) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 922 | #if 0 |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 923 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
| 924 | env->eip, env->cr[2], env->error_code); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 925 | #endif |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 926 | /* we restore the process signal mask as the sigreturn should |
| 927 | do it (XXX: use sigsetjmp) */ |
| 928 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 54ca909 | 2005-12-04 18:46:06 +0000 | [diff] [blame] | 929 | raise_exception_err(env->exception_index, env->error_code); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 930 | } else { |
| 931 | /* activate soft MMU for this block */ |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 932 | env->hflags |= HF_SOFTMMU_MASK; |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 933 | cpu_resume_from_signal(env, puc); |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 934 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 935 | /* never comes here */ |
| 936 | return 1; |
| 937 | } |
| 938 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 939 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 940 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 941 | int is_write, sigset_t *old_set, |
| 942 | void *puc) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 943 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 944 | TranslationBlock *tb; |
| 945 | int ret; |
| 946 | |
| 947 | if (cpu_single_env) |
| 948 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 949 | #if defined(DEBUG_SIGNAL) |
| 950 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 951 | pc, address, is_write, *(unsigned long *)old_set); |
| 952 | #endif |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 953 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 954 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 9f0777e | 2005-02-02 20:42:01 +0000 | [diff] [blame] | 955 | return 1; |
| 956 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 957 | /* see if it is an MMU fault */ |
| 958 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
| 959 | if (ret < 0) |
| 960 | return 0; /* not an MMU fault */ |
| 961 | if (ret == 0) |
| 962 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 963 | /* now we have a real cpu fault */ |
| 964 | tb = tb_find_pc(pc); |
| 965 | if (tb) { |
| 966 | /* the PC is inside the translated code. It means that we have |
| 967 | a virtual CPU fault */ |
| 968 | cpu_restore_state(tb, env, pc, puc); |
| 969 | } |
| 970 | /* we restore the process signal mask as the sigreturn should |
| 971 | do it (XXX: use sigsetjmp) */ |
| 972 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 973 | cpu_loop_exit(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 974 | } |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 975 | #elif defined(TARGET_SPARC) |
| 976 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 977 | int is_write, sigset_t *old_set, |
| 978 | void *puc) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 979 | { |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 980 | TranslationBlock *tb; |
| 981 | int ret; |
| 982 | |
| 983 | if (cpu_single_env) |
| 984 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 985 | #if defined(DEBUG_SIGNAL) |
| 986 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 987 | pc, address, is_write, *(unsigned long *)old_set); |
| 988 | #endif |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 989 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 990 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | b453b70 | 2004-01-04 15:45:21 +0000 | [diff] [blame] | 991 | return 1; |
| 992 | } |
bellard | 68016c6 | 2005-02-07 23:12:27 +0000 | [diff] [blame] | 993 | /* see if it is an MMU fault */ |
| 994 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
| 995 | if (ret < 0) |
| 996 | return 0; /* not an MMU fault */ |
| 997 | if (ret == 0) |
| 998 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 999 | /* now we have a real cpu fault */ |
| 1000 | tb = tb_find_pc(pc); |
| 1001 | if (tb) { |
| 1002 | /* the PC is inside the translated code. It means that we have |
| 1003 | a virtual CPU fault */ |
| 1004 | cpu_restore_state(tb, env, pc, puc); |
| 1005 | } |
| 1006 | /* we restore the process signal mask as the sigreturn should |
| 1007 | do it (XXX: use sigsetjmp) */ |
| 1008 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1009 | cpu_loop_exit(); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 1010 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1011 | #elif defined (TARGET_PPC) |
| 1012 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1013 | int is_write, sigset_t *old_set, |
| 1014 | void *puc) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1015 | { |
| 1016 | TranslationBlock *tb; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1017 | int ret; |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1018 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1019 | if (cpu_single_env) |
| 1020 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1021 | #if defined(DEBUG_SIGNAL) |
| 1022 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1023 | pc, address, is_write, *(unsigned long *)old_set); |
| 1024 | #endif |
| 1025 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1026 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1027 | return 1; |
| 1028 | } |
| 1029 | |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1030 | /* see if it is an MMU fault */ |
bellard | 7f957d2 | 2004-01-18 23:19:48 +0000 | [diff] [blame] | 1031 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1032 | if (ret < 0) |
| 1033 | return 0; /* not an MMU fault */ |
| 1034 | if (ret == 0) |
| 1035 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1036 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1037 | /* now we have a real cpu fault */ |
| 1038 | tb = tb_find_pc(pc); |
| 1039 | if (tb) { |
| 1040 | /* the PC is inside the translated code. It means that we have |
| 1041 | a virtual CPU fault */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1042 | cpu_restore_state(tb, env, pc, puc); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1043 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1044 | if (ret == 1) { |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1045 | #if 0 |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1046 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
| 1047 | env->nip, env->error_code, tb); |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1048 | #endif |
| 1049 | /* we restore the process signal mask as the sigreturn should |
| 1050 | do it (XXX: use sigsetjmp) */ |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1051 | sigprocmask(SIG_SETMASK, old_set, NULL); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1052 | do_raise_exception_err(env->exception_index, env->error_code); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1053 | } else { |
| 1054 | /* activate soft MMU for this block */ |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 1055 | cpu_resume_from_signal(env, puc); |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 1056 | } |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 1057 | /* never comes here */ |
| 1058 | return 1; |
| 1059 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1060 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 1061 | #elif defined(TARGET_M68K) |
| 1062 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1063 | int is_write, sigset_t *old_set, |
| 1064 | void *puc) |
| 1065 | { |
| 1066 | TranslationBlock *tb; |
| 1067 | int ret; |
| 1068 | |
| 1069 | if (cpu_single_env) |
| 1070 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1071 | #if defined(DEBUG_SIGNAL) |
| 1072 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1073 | pc, address, is_write, *(unsigned long *)old_set); |
| 1074 | #endif |
| 1075 | /* XXX: locking issue */ |
| 1076 | if (is_write && page_unprotect(address, pc, puc)) { |
| 1077 | return 1; |
| 1078 | } |
| 1079 | /* see if it is an MMU fault */ |
| 1080 | ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1081 | if (ret < 0) |
| 1082 | return 0; /* not an MMU fault */ |
| 1083 | if (ret == 0) |
| 1084 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1085 | /* now we have a real cpu fault */ |
| 1086 | tb = tb_find_pc(pc); |
| 1087 | if (tb) { |
| 1088 | /* the PC is inside the translated code. It means that we have |
| 1089 | a virtual CPU fault */ |
| 1090 | cpu_restore_state(tb, env, pc, puc); |
| 1091 | } |
| 1092 | /* we restore the process signal mask as the sigreturn should |
| 1093 | do it (XXX: use sigsetjmp) */ |
| 1094 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1095 | cpu_loop_exit(); |
| 1096 | /* never comes here */ |
| 1097 | return 1; |
| 1098 | } |
| 1099 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1100 | #elif defined (TARGET_MIPS) |
| 1101 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1102 | int is_write, sigset_t *old_set, |
| 1103 | void *puc) |
| 1104 | { |
| 1105 | TranslationBlock *tb; |
| 1106 | int ret; |
| 1107 | |
| 1108 | if (cpu_single_env) |
| 1109 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1110 | #if defined(DEBUG_SIGNAL) |
| 1111 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1112 | pc, address, is_write, *(unsigned long *)old_set); |
| 1113 | #endif |
| 1114 | /* XXX: locking issue */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1115 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1116 | return 1; |
| 1117 | } |
| 1118 | |
| 1119 | /* see if it is an MMU fault */ |
bellard | cc9442b | 2005-11-26 18:43:28 +0000 | [diff] [blame] | 1120 | ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1121 | if (ret < 0) |
| 1122 | return 0; /* not an MMU fault */ |
| 1123 | if (ret == 0) |
| 1124 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1125 | |
| 1126 | /* now we have a real cpu fault */ |
| 1127 | tb = tb_find_pc(pc); |
| 1128 | if (tb) { |
| 1129 | /* the PC is inside the translated code. It means that we have |
| 1130 | a virtual CPU fault */ |
| 1131 | cpu_restore_state(tb, env, pc, puc); |
| 1132 | } |
| 1133 | if (ret == 1) { |
| 1134 | #if 0 |
ths | 1eb5207 | 2007-05-12 16:57:42 +0000 | [diff] [blame] | 1135 | printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n", |
| 1136 | env->PC, env->error_code, tb); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1137 | #endif |
| 1138 | /* we restore the process signal mask as the sigreturn should |
| 1139 | do it (XXX: use sigsetjmp) */ |
| 1140 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1141 | do_raise_exception_err(env->exception_index, env->error_code); |
| 1142 | } else { |
| 1143 | /* activate soft MMU for this block */ |
| 1144 | cpu_resume_from_signal(env, puc); |
| 1145 | } |
| 1146 | /* never comes here */ |
| 1147 | return 1; |
| 1148 | } |
| 1149 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1150 | #elif defined (TARGET_SH4) |
| 1151 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1152 | int is_write, sigset_t *old_set, |
| 1153 | void *puc) |
| 1154 | { |
| 1155 | TranslationBlock *tb; |
| 1156 | int ret; |
| 1157 | |
| 1158 | if (cpu_single_env) |
| 1159 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1160 | #if defined(DEBUG_SIGNAL) |
| 1161 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1162 | pc, address, is_write, *(unsigned long *)old_set); |
| 1163 | #endif |
| 1164 | /* XXX: locking issue */ |
| 1165 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1166 | return 1; |
| 1167 | } |
| 1168 | |
| 1169 | /* see if it is an MMU fault */ |
| 1170 | ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1171 | if (ret < 0) |
| 1172 | return 0; /* not an MMU fault */ |
| 1173 | if (ret == 0) |
| 1174 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1175 | |
| 1176 | /* now we have a real cpu fault */ |
| 1177 | tb = tb_find_pc(pc); |
| 1178 | if (tb) { |
| 1179 | /* the PC is inside the translated code. It means that we have |
| 1180 | a virtual CPU fault */ |
| 1181 | cpu_restore_state(tb, env, pc, puc); |
| 1182 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1183 | #if 0 |
| 1184 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
| 1185 | env->nip, env->error_code, tb); |
| 1186 | #endif |
| 1187 | /* we restore the process signal mask as the sigreturn should |
| 1188 | do it (XXX: use sigsetjmp) */ |
pbrook | 355fb23 | 2006-06-17 19:58:25 +0000 | [diff] [blame] | 1189 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1190 | cpu_loop_exit(); |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1191 | /* never comes here */ |
| 1192 | return 1; |
| 1193 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 1194 | |
| 1195 | #elif defined (TARGET_ALPHA) |
| 1196 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 1197 | int is_write, sigset_t *old_set, |
| 1198 | void *puc) |
| 1199 | { |
| 1200 | TranslationBlock *tb; |
| 1201 | int ret; |
| 1202 | |
| 1203 | if (cpu_single_env) |
| 1204 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1205 | #if defined(DEBUG_SIGNAL) |
| 1206 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
| 1207 | pc, address, is_write, *(unsigned long *)old_set); |
| 1208 | #endif |
| 1209 | /* XXX: locking issue */ |
| 1210 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
| 1211 | return 1; |
| 1212 | } |
| 1213 | |
| 1214 | /* see if it is an MMU fault */ |
| 1215 | ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0); |
| 1216 | if (ret < 0) |
| 1217 | return 0; /* not an MMU fault */ |
| 1218 | if (ret == 0) |
| 1219 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 1220 | |
| 1221 | /* now we have a real cpu fault */ |
| 1222 | tb = tb_find_pc(pc); |
| 1223 | if (tb) { |
| 1224 | /* the PC is inside the translated code. It means that we have |
| 1225 | a virtual CPU fault */ |
| 1226 | cpu_restore_state(tb, env, pc, puc); |
| 1227 | } |
| 1228 | #if 0 |
| 1229 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
| 1230 | env->nip, env->error_code, tb); |
| 1231 | #endif |
| 1232 | /* we restore the process signal mask as the sigreturn should |
| 1233 | do it (XXX: use sigsetjmp) */ |
| 1234 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 1235 | cpu_loop_exit(); |
| 1236 | /* never comes here */ |
| 1237 | return 1; |
| 1238 | } |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1239 | #else |
| 1240 | #error unsupported target CPU |
| 1241 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1242 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1243 | #if defined(__i386__) |
| 1244 | |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1245 | #if defined(__APPLE__) |
| 1246 | # include <sys/ucontext.h> |
| 1247 | |
| 1248 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) |
| 1249 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) |
| 1250 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) |
| 1251 | #else |
| 1252 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) |
| 1253 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) |
| 1254 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) |
| 1255 | #endif |
| 1256 | |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1257 | #if defined(USE_CODE_COPY) |
| 1258 | static void cpu_send_trap(unsigned long pc, int trap, |
| 1259 | struct ucontext *uc) |
| 1260 | { |
| 1261 | TranslationBlock *tb; |
| 1262 | |
| 1263 | if (cpu_single_env) |
| 1264 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
| 1265 | /* now we have a real cpu fault */ |
| 1266 | tb = tb_find_pc(pc); |
| 1267 | if (tb) { |
| 1268 | /* the PC is inside the translated code. It means that we have |
| 1269 | a virtual CPU fault */ |
| 1270 | cpu_restore_state(tb, env, pc, uc); |
| 1271 | } |
| 1272 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
| 1273 | raise_exception_err(trap, env->error_code); |
| 1274 | } |
| 1275 | #endif |
| 1276 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1277 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1278 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1279 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1280 | siginfo_t *info = pinfo; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1281 | struct ucontext *uc = puc; |
| 1282 | unsigned long pc; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1283 | int trapno; |
bellard | 97eb5b1 | 2004-02-25 23:19:55 +0000 | [diff] [blame] | 1284 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1285 | #ifndef REG_EIP |
| 1286 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1287 | #define REG_EIP EIP |
| 1288 | #define REG_ERR ERR |
| 1289 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 1290 | #endif |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1291 | pc = EIP_sig(uc); |
| 1292 | trapno = TRAP_sig(uc); |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1293 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
| 1294 | if (trapno == 0x00 || trapno == 0x05) { |
| 1295 | /* send division by zero or bound exception */ |
| 1296 | cpu_send_trap(pc, trapno, uc); |
| 1297 | return 1; |
| 1298 | } else |
| 1299 | #endif |
| 1300 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1301 | trapno == 0xe ? |
bellard | d8ecc0b | 2007-02-05 21:41:46 +0000 | [diff] [blame] | 1302 | (ERROR_sig(uc) >> 1) & 1 : 0, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1303 | &uc->uc_sigmask, puc); |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1304 | } |
| 1305 | |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1306 | #elif defined(__x86_64__) |
| 1307 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1308 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1309 | void *puc) |
| 1310 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1311 | siginfo_t *info = pinfo; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 1312 | struct ucontext *uc = puc; |
| 1313 | unsigned long pc; |
| 1314 | |
| 1315 | pc = uc->uc_mcontext.gregs[REG_RIP]; |
| 1316 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1317 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
| 1318 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
| 1319 | &uc->uc_sigmask, puc); |
| 1320 | } |
| 1321 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1322 | #elif defined(__powerpc__) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1323 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1324 | /*********************************************************************** |
| 1325 | * signal context platform-specific definitions |
| 1326 | * From Wine |
| 1327 | */ |
| 1328 | #ifdef linux |
| 1329 | /* All Registers access - only for local access */ |
| 1330 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) |
| 1331 | /* Gpr Registers access */ |
| 1332 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) |
| 1333 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
| 1334 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
| 1335 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
| 1336 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
| 1337 | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
| 1338 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
| 1339 | /* Float Registers access */ |
| 1340 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
| 1341 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
| 1342 | /* Exception Registers access */ |
| 1343 | # define DAR_sig(context) REG_sig(dar, context) |
| 1344 | # define DSISR_sig(context) REG_sig(dsisr, context) |
| 1345 | # define TRAP_sig(context) REG_sig(trap, context) |
| 1346 | #endif /* linux */ |
| 1347 | |
| 1348 | #ifdef __APPLE__ |
| 1349 | # include <sys/ucontext.h> |
| 1350 | typedef struct ucontext SIGCONTEXT; |
| 1351 | /* All Registers access - only for local access */ |
| 1352 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) |
| 1353 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) |
| 1354 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) |
| 1355 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) |
| 1356 | /* Gpr Registers access */ |
| 1357 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
| 1358 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
| 1359 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
| 1360 | # define CTR_sig(context) REG_sig(ctr, context) |
| 1361 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
| 1362 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
| 1363 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
| 1364 | /* Float Registers access */ |
| 1365 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) |
| 1366 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
| 1367 | /* Exception Registers access */ |
| 1368 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
| 1369 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) |
| 1370 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
| 1371 | #endif /* __APPLE__ */ |
| 1372 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1373 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1374 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1375 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1376 | siginfo_t *info = pinfo; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1377 | struct ucontext *uc = puc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1378 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1379 | int is_write; |
| 1380 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1381 | pc = IAR_sig(uc); |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1382 | is_write = 0; |
| 1383 | #if 0 |
| 1384 | /* ppc 4xx case */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1385 | if (DSISR_sig(uc) & 0x00800000) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1386 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1387 | #else |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 1388 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 1389 | is_write = 1; |
| 1390 | #endif |
| 1391 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1392 | is_write, &uc->uc_sigmask, puc); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 1393 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1394 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1395 | #elif defined(__alpha__) |
| 1396 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1397 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1398 | void *puc) |
| 1399 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1400 | siginfo_t *info = pinfo; |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1401 | struct ucontext *uc = puc; |
| 1402 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 1403 | uint32_t insn = *pc; |
| 1404 | int is_write = 0; |
| 1405 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1406 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1407 | switch (insn >> 26) { |
| 1408 | case 0x0d: // stw |
| 1409 | case 0x0e: // stb |
| 1410 | case 0x0f: // stq_u |
| 1411 | case 0x24: // stf |
| 1412 | case 0x25: // stg |
| 1413 | case 0x26: // sts |
| 1414 | case 0x27: // stt |
| 1415 | case 0x2c: // stl |
| 1416 | case 0x2d: // stq |
| 1417 | case 0x2e: // stl_c |
| 1418 | case 0x2f: // stq_c |
| 1419 | is_write = 1; |
| 1420 | } |
| 1421 | |
| 1422 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1423 | is_write, &uc->uc_sigmask, puc); |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 1424 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1425 | #elif defined(__sparc__) |
| 1426 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1427 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1428 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1429 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1430 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1431 | uint32_t *regs = (uint32_t *)(info + 1); |
| 1432 | void *sigmask = (regs + 20); |
| 1433 | unsigned long pc; |
| 1434 | int is_write; |
| 1435 | uint32_t insn; |
| 1436 | |
| 1437 | /* XXX: is there a standard glibc define ? */ |
| 1438 | pc = regs[1]; |
| 1439 | /* XXX: need kernel patch to get write flag faster */ |
| 1440 | is_write = 0; |
| 1441 | insn = *(uint32_t *)pc; |
| 1442 | if ((insn >> 30) == 3) { |
| 1443 | switch((insn >> 19) & 0x3f) { |
| 1444 | case 0x05: // stb |
| 1445 | case 0x06: // sth |
| 1446 | case 0x04: // st |
| 1447 | case 0x07: // std |
| 1448 | case 0x24: // stf |
| 1449 | case 0x27: // stdf |
| 1450 | case 0x25: // stfsr |
| 1451 | is_write = 1; |
| 1452 | break; |
| 1453 | } |
| 1454 | } |
| 1455 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1456 | is_write, sigmask, NULL); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | #elif defined(__arm__) |
| 1460 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1461 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 1462 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1463 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1464 | siginfo_t *info = pinfo; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1465 | struct ucontext *uc = puc; |
| 1466 | unsigned long pc; |
| 1467 | int is_write; |
| 1468 | |
| 1469 | pc = uc->uc_mcontext.gregs[R15]; |
| 1470 | /* XXX: compute is_write */ |
| 1471 | is_write = 0; |
| 1472 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1473 | is_write, |
pbrook | f3a9676 | 2006-07-29 19:09:31 +0000 | [diff] [blame] | 1474 | &uc->uc_sigmask, puc); |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 1475 | } |
| 1476 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1477 | #elif defined(__mc68000) |
| 1478 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1479 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1480 | void *puc) |
| 1481 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1482 | siginfo_t *info = pinfo; |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1483 | struct ucontext *uc = puc; |
| 1484 | unsigned long pc; |
| 1485 | int is_write; |
| 1486 | |
| 1487 | pc = uc->uc_mcontext.gregs[16]; |
| 1488 | /* XXX: compute is_write */ |
| 1489 | is_write = 0; |
| 1490 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1491 | is_write, |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 1492 | &uc->uc_sigmask, puc); |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 1493 | } |
| 1494 | |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1495 | #elif defined(__ia64) |
| 1496 | |
| 1497 | #ifndef __ISR_VALID |
| 1498 | /* This ought to be in <bits/siginfo.h>... */ |
| 1499 | # define __ISR_VALID 1 |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1500 | #endif |
| 1501 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1502 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1503 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1504 | siginfo_t *info = pinfo; |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1505 | struct ucontext *uc = puc; |
| 1506 | unsigned long ip; |
| 1507 | int is_write = 0; |
| 1508 | |
| 1509 | ip = uc->uc_mcontext.sc_ip; |
| 1510 | switch (host_signum) { |
| 1511 | case SIGILL: |
| 1512 | case SIGFPE: |
| 1513 | case SIGSEGV: |
| 1514 | case SIGBUS: |
| 1515 | case SIGTRAP: |
bellard | fd4a43e | 2006-04-24 20:32:17 +0000 | [diff] [blame] | 1516 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
bellard | b8076a7 | 2005-04-07 22:20:31 +0000 | [diff] [blame] | 1517 | /* ISR.W (write-access) is bit 33: */ |
| 1518 | is_write = (info->si_isr >> 33) & 1; |
| 1519 | break; |
| 1520 | |
| 1521 | default: |
| 1522 | break; |
| 1523 | } |
| 1524 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
| 1525 | is_write, |
| 1526 | &uc->uc_sigmask, puc); |
| 1527 | } |
| 1528 | |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1529 | #elif defined(__s390__) |
| 1530 | |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1531 | int cpu_signal_handler(int host_signum, void *pinfo, |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1532 | void *puc) |
| 1533 | { |
ths | 5a7b542 | 2007-01-31 12:16:51 +0000 | [diff] [blame] | 1534 | siginfo_t *info = pinfo; |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1535 | struct ucontext *uc = puc; |
| 1536 | unsigned long pc; |
| 1537 | int is_write; |
| 1538 | |
| 1539 | pc = uc->uc_mcontext.psw.addr; |
| 1540 | /* XXX: compute is_write */ |
| 1541 | is_write = 0; |
| 1542 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1543 | is_write, &uc->uc_sigmask, puc); |
| 1544 | } |
| 1545 | |
| 1546 | #elif defined(__mips__) |
| 1547 | |
ths | 9617efe | 2007-05-08 21:05:55 +0000 | [diff] [blame] | 1548 | int cpu_signal_handler(int host_signum, void *pinfo, |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1549 | void *puc) |
| 1550 | { |
ths | 9617efe | 2007-05-08 21:05:55 +0000 | [diff] [blame] | 1551 | siginfo_t *info = pinfo; |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1552 | struct ucontext *uc = puc; |
| 1553 | greg_t pc = uc->uc_mcontext.pc; |
| 1554 | int is_write; |
| 1555 | |
| 1556 | /* XXX: compute is_write */ |
| 1557 | is_write = 0; |
| 1558 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 1559 | is_write, &uc->uc_sigmask, puc); |
bellard | 90cb949 | 2005-07-24 15:11:38 +0000 | [diff] [blame] | 1560 | } |
| 1561 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1562 | #else |
| 1563 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 1564 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 1565 | |
| 1566 | #endif |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 1567 | |
| 1568 | #endif /* !defined(CONFIG_SOFTMMU) */ |