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bellard54936002003-05-13 00:25:15 +00001/*
bellardfd6ce8f2003-05-14 19:00:11 +00002 * virtual page mapping and translated block handling
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard54936002003-05-13 00:25:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
aurel32fad6cb12009-01-04 22:05:52 +000018 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
bellard54936002003-05-13 00:25:15 +000019 */
bellard67b915a2004-03-31 23:37:16 +000020#include "config.h"
bellardd5a8f072004-09-29 21:15:28 +000021#ifdef _WIN32
ths4fddf622007-12-17 04:42:29 +000022#define WIN32_LEAN_AND_MEAN
bellardd5a8f072004-09-29 21:15:28 +000023#include <windows.h>
24#else
bellarda98d49b2004-11-14 16:22:05 +000025#include <sys/types.h>
bellardd5a8f072004-09-29 21:15:28 +000026#include <sys/mman.h>
27#endif
bellard54936002003-05-13 00:25:15 +000028#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <errno.h>
33#include <unistd.h>
34#include <inttypes.h>
35
bellard6180a182003-09-30 21:04:53 +000036#include "cpu.h"
37#include "exec-all.h"
aurel32ca10f862008-04-11 21:35:42 +000038#include "qemu-common.h"
bellardb67d9a52008-05-23 09:57:34 +000039#include "tcg.h"
pbrookb3c77242008-06-30 16:31:04 +000040#include "hw/hw.h"
aliguori74576192008-10-06 14:02:03 +000041#include "osdep.h"
aliguori7ba1e612008-11-05 16:04:33 +000042#include "kvm.h"
pbrook53a59602006-03-25 19:31:22 +000043#if defined(CONFIG_USER_ONLY)
44#include <qemu.h>
45#endif
bellard54936002003-05-13 00:25:15 +000046
bellardfd6ce8f2003-05-14 19:00:11 +000047//#define DEBUG_TB_INVALIDATE
bellard66e85a22003-06-24 13:28:12 +000048//#define DEBUG_FLUSH
bellard9fa3e852004-01-04 18:06:42 +000049//#define DEBUG_TLB
pbrook67d3b952006-12-18 05:03:52 +000050//#define DEBUG_UNASSIGNED
bellardfd6ce8f2003-05-14 19:00:11 +000051
52/* make various TB consistency checks */
ths5fafdf22007-09-16 21:08:06 +000053//#define DEBUG_TB_CHECK
54//#define DEBUG_TLB_CHECK
bellardfd6ce8f2003-05-14 19:00:11 +000055
ths1196be32007-03-17 15:17:58 +000056//#define DEBUG_IOPORT
blueswir1db7b5422007-05-26 17:36:03 +000057//#define DEBUG_SUBPAGE
ths1196be32007-03-17 15:17:58 +000058
pbrook99773bd2006-04-16 15:14:59 +000059#if !defined(CONFIG_USER_ONLY)
60/* TB consistency checks only implemented for usermode emulation. */
61#undef DEBUG_TB_CHECK
62#endif
63
bellard9fa3e852004-01-04 18:06:42 +000064#define SMC_BITMAP_USE_THRESHOLD 10
65
66#define MMAP_AREA_START 0x00000000
67#define MMAP_AREA_END 0xa8000000
bellardfd6ce8f2003-05-14 19:00:11 +000068
bellard108c49b2005-07-24 12:55:09 +000069#if defined(TARGET_SPARC64)
70#define TARGET_PHYS_ADDR_SPACE_BITS 41
blueswir15dcb6b92007-05-19 12:58:30 +000071#elif defined(TARGET_SPARC)
72#define TARGET_PHYS_ADDR_SPACE_BITS 36
j_mayerbedb69e2007-04-05 20:08:21 +000073#elif defined(TARGET_ALPHA)
74#define TARGET_PHYS_ADDR_SPACE_BITS 42
75#define TARGET_VIRT_ADDR_SPACE_BITS 42
bellard108c49b2005-07-24 12:55:09 +000076#elif defined(TARGET_PPC64)
77#define TARGET_PHYS_ADDR_SPACE_BITS 42
aurel3200f82b82008-04-27 21:12:55 +000078#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
79#define TARGET_PHYS_ADDR_SPACE_BITS 42
80#elif defined(TARGET_I386) && !defined(USE_KQEMU)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
bellard108c49b2005-07-24 12:55:09 +000082#else
83/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
84#define TARGET_PHYS_ADDR_SPACE_BITS 32
85#endif
86
blueswir1bdaf78e2008-10-04 07:24:27 +000087static TranslationBlock *tbs;
bellard26a5f132008-05-28 12:30:31 +000088int code_gen_max_blocks;
bellard9fa3e852004-01-04 18:06:42 +000089TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +000090static int nb_tbs;
bellardeb51d102003-05-14 21:51:13 +000091/* any access to the tbs or the page table must use this lock */
92spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
bellardfd6ce8f2003-05-14 19:00:11 +000093
blueswir1141ac462008-07-26 15:05:57 +000094#if defined(__arm__) || defined(__sparc_v9__)
95/* The prologue must be reachable with a direct jump. ARM and Sparc64
96 have limited branch ranges (possibly also PPC) so place it in a
blueswir1d03d8602008-07-10 17:21:31 +000097 section close to code segment. */
98#define code_gen_section \
99 __attribute__((__section__(".gen_code"))) \
100 __attribute__((aligned (32)))
101#else
102#define code_gen_section \
103 __attribute__((aligned (32)))
104#endif
105
106uint8_t code_gen_prologue[1024] code_gen_section;
blueswir1bdaf78e2008-10-04 07:24:27 +0000107static uint8_t *code_gen_buffer;
108static unsigned long code_gen_buffer_size;
bellard26a5f132008-05-28 12:30:31 +0000109/* threshold to flush the translated code buffer */
blueswir1bdaf78e2008-10-04 07:24:27 +0000110static unsigned long code_gen_buffer_max_size;
bellardfd6ce8f2003-05-14 19:00:11 +0000111uint8_t *code_gen_ptr;
112
pbrooke2eef172008-06-08 01:09:01 +0000113#if !defined(CONFIG_USER_ONLY)
aurel3200f82b82008-04-27 21:12:55 +0000114ram_addr_t phys_ram_size;
bellard9fa3e852004-01-04 18:06:42 +0000115int phys_ram_fd;
116uint8_t *phys_ram_base;
bellard1ccde1c2004-02-06 19:46:14 +0000117uint8_t *phys_ram_dirty;
aliguori74576192008-10-06 14:02:03 +0000118static int in_migration;
bellarde9a1ab12007-02-08 23:08:38 +0000119static ram_addr_t phys_ram_alloc_offset = 0;
pbrooke2eef172008-06-08 01:09:01 +0000120#endif
bellard9fa3e852004-01-04 18:06:42 +0000121
bellard6a00d602005-11-21 23:25:50 +0000122CPUState *first_cpu;
123/* current CPU in the current thread. It is only valid inside
124 cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000125CPUState *cpu_single_env;
pbrook2e70f6e2008-06-29 01:03:05 +0000126/* 0 = Do not count executed instructions.
thsbf20dc02008-06-30 17:22:19 +0000127 1 = Precise instruction counting.
pbrook2e70f6e2008-06-29 01:03:05 +0000128 2 = Adaptive rate instruction counting. */
129int use_icount = 0;
130/* Current instruction counter. While executing translated code this may
131 include some instructions that have not yet been executed. */
132int64_t qemu_icount;
bellard6a00d602005-11-21 23:25:50 +0000133
bellard54936002003-05-13 00:25:15 +0000134typedef struct PageDesc {
bellard92e873b2004-05-21 14:52:29 +0000135 /* list of TBs intersecting this ram page */
bellardfd6ce8f2003-05-14 19:00:11 +0000136 TranslationBlock *first_tb;
bellard9fa3e852004-01-04 18:06:42 +0000137 /* in order to optimize self modifying code, we count the number
138 of lookups we do to a given page to use a bitmap */
139 unsigned int code_write_count;
140 uint8_t *code_bitmap;
141#if defined(CONFIG_USER_ONLY)
142 unsigned long flags;
143#endif
bellard54936002003-05-13 00:25:15 +0000144} PageDesc;
145
bellard92e873b2004-05-21 14:52:29 +0000146typedef struct PhysPageDesc {
pbrook0f459d12008-06-09 00:20:13 +0000147 /* offset in host memory of the page + io_index in the low bits */
aurel3200f82b82008-04-27 21:12:55 +0000148 ram_addr_t phys_offset;
pbrook8da3ff12008-12-01 18:59:50 +0000149 ram_addr_t region_offset;
bellard92e873b2004-05-21 14:52:29 +0000150} PhysPageDesc;
151
bellard54936002003-05-13 00:25:15 +0000152#define L2_BITS 10
j_mayerbedb69e2007-04-05 20:08:21 +0000153#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
154/* XXX: this is a temporary hack for alpha target.
155 * In the future, this is to be replaced by a multi-level table
156 * to actually be able to handle the complete 64 bits address space.
157 */
158#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
159#else
aurel3203875442008-04-22 20:45:18 +0000160#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
j_mayerbedb69e2007-04-05 20:08:21 +0000161#endif
bellard54936002003-05-13 00:25:15 +0000162
163#define L1_SIZE (1 << L1_BITS)
164#define L2_SIZE (1 << L2_BITS)
165
bellard83fb7ad2004-07-05 21:25:26 +0000166unsigned long qemu_real_host_page_size;
167unsigned long qemu_host_page_bits;
168unsigned long qemu_host_page_size;
169unsigned long qemu_host_page_mask;
bellard54936002003-05-13 00:25:15 +0000170
bellard92e873b2004-05-21 14:52:29 +0000171/* XXX: for system emulation, it could just be an array */
bellard54936002003-05-13 00:25:15 +0000172static PageDesc *l1_map[L1_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +0000173static PhysPageDesc **l1_phys_map;
bellard54936002003-05-13 00:25:15 +0000174
pbrooke2eef172008-06-08 01:09:01 +0000175#if !defined(CONFIG_USER_ONLY)
176static void io_mem_init(void);
177
bellard33417e72003-08-10 21:47:01 +0000178/* io memory support */
bellard33417e72003-08-10 21:47:01 +0000179CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
180CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000181void *io_mem_opaque[IO_MEM_NB_ENTRIES];
blueswir1511d2b12009-03-07 15:32:56 +0000182static char io_mem_used[IO_MEM_NB_ENTRIES];
pbrook6658ffb2007-03-16 23:58:11 +0000183static int io_mem_watch;
184#endif
bellard33417e72003-08-10 21:47:01 +0000185
bellard34865132003-10-05 14:28:56 +0000186/* log support */
blueswir1d9b630f2008-10-05 09:57:08 +0000187static const char *logfilename = "/tmp/qemu.log";
bellard34865132003-10-05 14:28:56 +0000188FILE *logfile;
189int loglevel;
pbrooke735b912007-06-30 13:53:24 +0000190static int log_append = 0;
bellard34865132003-10-05 14:28:56 +0000191
bellarde3db7222005-01-26 22:00:47 +0000192/* statistics */
193static int tlb_flush_count;
194static int tb_flush_count;
195static int tb_phys_invalidate_count;
196
blueswir1db7b5422007-05-26 17:36:03 +0000197#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
198typedef struct subpage_t {
199 target_phys_addr_t base;
blueswir13ee89922008-01-02 19:45:26 +0000200 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
201 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
202 void *opaque[TARGET_PAGE_SIZE][2][4];
pbrook8da3ff12008-12-01 18:59:50 +0000203 ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
blueswir1db7b5422007-05-26 17:36:03 +0000204} subpage_t;
205
bellard7cb69ca2008-05-10 10:55:51 +0000206#ifdef _WIN32
207static void map_exec(void *addr, long size)
208{
209 DWORD old_protect;
210 VirtualProtect(addr, size,
211 PAGE_EXECUTE_READWRITE, &old_protect);
212
213}
214#else
215static void map_exec(void *addr, long size)
216{
bellard43694152008-05-29 09:35:57 +0000217 unsigned long start, end, page_size;
bellard7cb69ca2008-05-10 10:55:51 +0000218
bellard43694152008-05-29 09:35:57 +0000219 page_size = getpagesize();
bellard7cb69ca2008-05-10 10:55:51 +0000220 start = (unsigned long)addr;
bellard43694152008-05-29 09:35:57 +0000221 start &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000222
223 end = (unsigned long)addr + size;
bellard43694152008-05-29 09:35:57 +0000224 end += page_size - 1;
225 end &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000226
227 mprotect((void *)start, end - start,
228 PROT_READ | PROT_WRITE | PROT_EXEC);
229}
230#endif
231
bellardb346ff42003-06-15 20:05:50 +0000232static void page_init(void)
bellard54936002003-05-13 00:25:15 +0000233{
bellard83fb7ad2004-07-05 21:25:26 +0000234 /* NOTE: we can always suppose that qemu_host_page_size >=
bellard54936002003-05-13 00:25:15 +0000235 TARGET_PAGE_SIZE */
aliguoric2b48b62008-11-11 22:06:42 +0000236#ifdef _WIN32
237 {
238 SYSTEM_INFO system_info;
239
240 GetSystemInfo(&system_info);
241 qemu_real_host_page_size = system_info.dwPageSize;
242 }
243#else
244 qemu_real_host_page_size = getpagesize();
245#endif
bellard83fb7ad2004-07-05 21:25:26 +0000246 if (qemu_host_page_size == 0)
247 qemu_host_page_size = qemu_real_host_page_size;
248 if (qemu_host_page_size < TARGET_PAGE_SIZE)
249 qemu_host_page_size = TARGET_PAGE_SIZE;
250 qemu_host_page_bits = 0;
251 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
252 qemu_host_page_bits++;
253 qemu_host_page_mask = ~(qemu_host_page_size - 1);
bellard108c49b2005-07-24 12:55:09 +0000254 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
255 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
balrog50a95692007-12-12 01:16:23 +0000256
257#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
258 {
259 long long startaddr, endaddr;
260 FILE *f;
261 int n;
262
pbrookc8a706f2008-06-02 16:16:42 +0000263 mmap_lock();
pbrook07765902008-05-31 16:33:53 +0000264 last_brk = (unsigned long)sbrk(0);
balrog50a95692007-12-12 01:16:23 +0000265 f = fopen("/proc/self/maps", "r");
266 if (f) {
267 do {
268 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
269 if (n == 2) {
blueswir1e0b8d652008-05-03 17:51:24 +0000270 startaddr = MIN(startaddr,
271 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
272 endaddr = MIN(endaddr,
273 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
pbrookb5fc9092008-05-29 13:56:10 +0000274 page_set_flags(startaddr & TARGET_PAGE_MASK,
balrog50a95692007-12-12 01:16:23 +0000275 TARGET_PAGE_ALIGN(endaddr),
276 PAGE_RESERVED);
277 }
278 } while (!feof(f));
279 fclose(f);
280 }
pbrookc8a706f2008-06-02 16:16:42 +0000281 mmap_unlock();
balrog50a95692007-12-12 01:16:23 +0000282 }
283#endif
bellard54936002003-05-13 00:25:15 +0000284}
285
aliguori434929b2008-09-15 15:56:30 +0000286static inline PageDesc **page_l1_map(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000287{
pbrook17e23772008-06-09 13:47:45 +0000288#if TARGET_LONG_BITS > 32
289 /* Host memory outside guest VM. For 32-bit targets we have already
290 excluded high addresses. */
thsd8173e02008-08-29 13:10:00 +0000291 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
pbrook17e23772008-06-09 13:47:45 +0000292 return NULL;
293#endif
aliguori434929b2008-09-15 15:56:30 +0000294 return &l1_map[index >> L2_BITS];
295}
296
297static inline PageDesc *page_find_alloc(target_ulong index)
298{
299 PageDesc **lp, *p;
300 lp = page_l1_map(index);
301 if (!lp)
302 return NULL;
303
bellard54936002003-05-13 00:25:15 +0000304 p = *lp;
305 if (!p) {
306 /* allocate if not found */
pbrook17e23772008-06-09 13:47:45 +0000307#if defined(CONFIG_USER_ONLY)
pbrook17e23772008-06-09 13:47:45 +0000308 size_t len = sizeof(PageDesc) * L2_SIZE;
309 /* Don't use qemu_malloc because it may recurse. */
310 p = mmap(0, len, PROT_READ | PROT_WRITE,
311 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
bellard54936002003-05-13 00:25:15 +0000312 *lp = p;
aurel32fb1c2cd2008-12-08 18:12:26 +0000313 if (h2g_valid(p)) {
314 unsigned long addr = h2g(p);
pbrook17e23772008-06-09 13:47:45 +0000315 page_set_flags(addr & TARGET_PAGE_MASK,
316 TARGET_PAGE_ALIGN(addr + len),
317 PAGE_RESERVED);
318 }
319#else
320 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
321 *lp = p;
322#endif
bellard54936002003-05-13 00:25:15 +0000323 }
324 return p + (index & (L2_SIZE - 1));
325}
326
aurel3200f82b82008-04-27 21:12:55 +0000327static inline PageDesc *page_find(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000328{
aliguori434929b2008-09-15 15:56:30 +0000329 PageDesc **lp, *p;
330 lp = page_l1_map(index);
331 if (!lp)
332 return NULL;
bellard54936002003-05-13 00:25:15 +0000333
aliguori434929b2008-09-15 15:56:30 +0000334 p = *lp;
bellard54936002003-05-13 00:25:15 +0000335 if (!p)
336 return 0;
bellardfd6ce8f2003-05-14 19:00:11 +0000337 return p + (index & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000338}
339
bellard108c49b2005-07-24 12:55:09 +0000340static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
bellard92e873b2004-05-21 14:52:29 +0000341{
bellard108c49b2005-07-24 12:55:09 +0000342 void **lp, **p;
pbrooke3f4e2a2006-04-08 20:02:06 +0000343 PhysPageDesc *pd;
bellard92e873b2004-05-21 14:52:29 +0000344
bellard108c49b2005-07-24 12:55:09 +0000345 p = (void **)l1_phys_map;
346#if TARGET_PHYS_ADDR_SPACE_BITS > 32
347
348#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
349#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
350#endif
351 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000352 p = *lp;
353 if (!p) {
354 /* allocate if not found */
bellard108c49b2005-07-24 12:55:09 +0000355 if (!alloc)
356 return NULL;
357 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
358 memset(p, 0, sizeof(void *) * L1_SIZE);
359 *lp = p;
360 }
361#endif
362 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pbrooke3f4e2a2006-04-08 20:02:06 +0000363 pd = *lp;
364 if (!pd) {
365 int i;
bellard108c49b2005-07-24 12:55:09 +0000366 /* allocate if not found */
367 if (!alloc)
368 return NULL;
pbrooke3f4e2a2006-04-08 20:02:06 +0000369 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
370 *lp = pd;
pbrook67c4d232009-02-23 13:16:07 +0000371 for (i = 0; i < L2_SIZE; i++) {
pbrooke3f4e2a2006-04-08 20:02:06 +0000372 pd[i].phys_offset = IO_MEM_UNASSIGNED;
pbrook67c4d232009-02-23 13:16:07 +0000373 pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
374 }
bellard92e873b2004-05-21 14:52:29 +0000375 }
pbrooke3f4e2a2006-04-08 20:02:06 +0000376 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000377}
378
bellard108c49b2005-07-24 12:55:09 +0000379static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
bellard92e873b2004-05-21 14:52:29 +0000380{
bellard108c49b2005-07-24 12:55:09 +0000381 return phys_page_find_alloc(index, 0);
bellard92e873b2004-05-21 14:52:29 +0000382}
383
bellard9fa3e852004-01-04 18:06:42 +0000384#if !defined(CONFIG_USER_ONLY)
bellard6a00d602005-11-21 23:25:50 +0000385static void tlb_protect_code(ram_addr_t ram_addr);
ths5fafdf22007-09-16 21:08:06 +0000386static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +0000387 target_ulong vaddr);
pbrookc8a706f2008-06-02 16:16:42 +0000388#define mmap_lock() do { } while(0)
389#define mmap_unlock() do { } while(0)
bellard9fa3e852004-01-04 18:06:42 +0000390#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000391
bellard43694152008-05-29 09:35:57 +0000392#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
393
394#if defined(CONFIG_USER_ONLY)
395/* Currently it is not recommanded to allocate big chunks of data in
396 user mode. It will change when a dedicated libc will be used */
397#define USE_STATIC_CODE_GEN_BUFFER
398#endif
399
400#ifdef USE_STATIC_CODE_GEN_BUFFER
401static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
402#endif
403
blueswir18fcd3692008-08-17 20:26:25 +0000404static void code_gen_alloc(unsigned long tb_size)
bellard26a5f132008-05-28 12:30:31 +0000405{
bellard43694152008-05-29 09:35:57 +0000406#ifdef USE_STATIC_CODE_GEN_BUFFER
407 code_gen_buffer = static_code_gen_buffer;
408 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
409 map_exec(code_gen_buffer, code_gen_buffer_size);
410#else
bellard26a5f132008-05-28 12:30:31 +0000411 code_gen_buffer_size = tb_size;
412 if (code_gen_buffer_size == 0) {
bellard43694152008-05-29 09:35:57 +0000413#if defined(CONFIG_USER_ONLY)
414 /* in user mode, phys_ram_size is not meaningful */
415 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
416#else
bellard26a5f132008-05-28 12:30:31 +0000417 /* XXX: needs ajustments */
aliguori174a9a12008-09-24 14:10:36 +0000418 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
bellard43694152008-05-29 09:35:57 +0000419#endif
bellard26a5f132008-05-28 12:30:31 +0000420 }
421 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
422 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
423 /* The code gen buffer location may have constraints depending on
424 the host cpu and OS */
425#if defined(__linux__)
426 {
427 int flags;
blueswir1141ac462008-07-26 15:05:57 +0000428 void *start = NULL;
429
bellard26a5f132008-05-28 12:30:31 +0000430 flags = MAP_PRIVATE | MAP_ANONYMOUS;
431#if defined(__x86_64__)
432 flags |= MAP_32BIT;
433 /* Cannot map more than that */
434 if (code_gen_buffer_size > (800 * 1024 * 1024))
435 code_gen_buffer_size = (800 * 1024 * 1024);
blueswir1141ac462008-07-26 15:05:57 +0000436#elif defined(__sparc_v9__)
437 // Map the buffer below 2G, so we can use direct calls and branches
438 flags |= MAP_FIXED;
439 start = (void *) 0x60000000UL;
440 if (code_gen_buffer_size > (512 * 1024 * 1024))
441 code_gen_buffer_size = (512 * 1024 * 1024);
balrog1cb06612008-12-01 02:10:17 +0000442#elif defined(__arm__)
balrog63d41242008-12-01 02:19:41 +0000443 /* Map the buffer below 32M, so we can use direct calls and branches */
balrog1cb06612008-12-01 02:10:17 +0000444 flags |= MAP_FIXED;
445 start = (void *) 0x01000000UL;
446 if (code_gen_buffer_size > 16 * 1024 * 1024)
447 code_gen_buffer_size = 16 * 1024 * 1024;
bellard26a5f132008-05-28 12:30:31 +0000448#endif
blueswir1141ac462008-07-26 15:05:57 +0000449 code_gen_buffer = mmap(start, code_gen_buffer_size,
450 PROT_WRITE | PROT_READ | PROT_EXEC,
bellard26a5f132008-05-28 12:30:31 +0000451 flags, -1, 0);
452 if (code_gen_buffer == MAP_FAILED) {
453 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
454 exit(1);
455 }
456 }
blueswir1c5e97232009-03-07 20:06:23 +0000457#elif defined(__FreeBSD__) || defined(__DragonFly__)
aliguori06e67a82008-09-27 15:32:41 +0000458 {
459 int flags;
460 void *addr = NULL;
461 flags = MAP_PRIVATE | MAP_ANONYMOUS;
462#if defined(__x86_64__)
463 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
464 * 0x40000000 is free */
465 flags |= MAP_FIXED;
466 addr = (void *)0x40000000;
467 /* Cannot map more than that */
468 if (code_gen_buffer_size > (800 * 1024 * 1024))
469 code_gen_buffer_size = (800 * 1024 * 1024);
470#endif
471 code_gen_buffer = mmap(addr, code_gen_buffer_size,
472 PROT_WRITE | PROT_READ | PROT_EXEC,
473 flags, -1, 0);
474 if (code_gen_buffer == MAP_FAILED) {
475 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
476 exit(1);
477 }
478 }
bellard26a5f132008-05-28 12:30:31 +0000479#else
480 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
bellard26a5f132008-05-28 12:30:31 +0000481 map_exec(code_gen_buffer, code_gen_buffer_size);
482#endif
bellard43694152008-05-29 09:35:57 +0000483#endif /* !USE_STATIC_CODE_GEN_BUFFER */
bellard26a5f132008-05-28 12:30:31 +0000484 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
485 code_gen_buffer_max_size = code_gen_buffer_size -
486 code_gen_max_block_size();
487 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
488 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
489}
490
491/* Must be called before using the QEMU cpus. 'tb_size' is the size
492 (in bytes) allocated to the translation buffer. Zero means default
493 size. */
494void cpu_exec_init_all(unsigned long tb_size)
495{
bellard26a5f132008-05-28 12:30:31 +0000496 cpu_gen_init();
497 code_gen_alloc(tb_size);
498 code_gen_ptr = code_gen_buffer;
bellard43694152008-05-29 09:35:57 +0000499 page_init();
pbrooke2eef172008-06-08 01:09:01 +0000500#if !defined(CONFIG_USER_ONLY)
bellard26a5f132008-05-28 12:30:31 +0000501 io_mem_init();
pbrooke2eef172008-06-08 01:09:01 +0000502#endif
bellard26a5f132008-05-28 12:30:31 +0000503}
504
pbrook9656f322008-07-01 20:01:19 +0000505#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
506
507#define CPU_COMMON_SAVE_VERSION 1
508
509static void cpu_common_save(QEMUFile *f, void *opaque)
510{
511 CPUState *env = opaque;
512
513 qemu_put_be32s(f, &env->halted);
514 qemu_put_be32s(f, &env->interrupt_request);
515}
516
517static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
518{
519 CPUState *env = opaque;
520
521 if (version_id != CPU_COMMON_SAVE_VERSION)
522 return -EINVAL;
523
524 qemu_get_be32s(f, &env->halted);
pbrook75f482a2008-07-01 21:53:33 +0000525 qemu_get_be32s(f, &env->interrupt_request);
aurel323098dba2009-03-07 21:28:24 +0000526 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
527 version_id is increased. */
528 env->interrupt_request &= ~0x01;
pbrook9656f322008-07-01 20:01:19 +0000529 tlb_flush(env, 1);
530
531 return 0;
532}
533#endif
534
bellard6a00d602005-11-21 23:25:50 +0000535void cpu_exec_init(CPUState *env)
bellardfd6ce8f2003-05-14 19:00:11 +0000536{
bellard6a00d602005-11-21 23:25:50 +0000537 CPUState **penv;
538 int cpu_index;
539
pbrookc2764712009-03-07 15:24:59 +0000540#if defined(CONFIG_USER_ONLY)
541 cpu_list_lock();
542#endif
bellard6a00d602005-11-21 23:25:50 +0000543 env->next_cpu = NULL;
544 penv = &first_cpu;
545 cpu_index = 0;
546 while (*penv != NULL) {
547 penv = (CPUState **)&(*penv)->next_cpu;
548 cpu_index++;
549 }
550 env->cpu_index = cpu_index;
aliguoric0ce9982008-11-25 22:13:57 +0000551 TAILQ_INIT(&env->breakpoints);
552 TAILQ_INIT(&env->watchpoints);
bellard6a00d602005-11-21 23:25:50 +0000553 *penv = env;
pbrookc2764712009-03-07 15:24:59 +0000554#if defined(CONFIG_USER_ONLY)
555 cpu_list_unlock();
556#endif
pbrookb3c77242008-06-30 16:31:04 +0000557#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
pbrook9656f322008-07-01 20:01:19 +0000558 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
559 cpu_common_save, cpu_common_load, env);
pbrookb3c77242008-06-30 16:31:04 +0000560 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
561 cpu_save, cpu_load, env);
562#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000563}
564
bellard9fa3e852004-01-04 18:06:42 +0000565static inline void invalidate_page_bitmap(PageDesc *p)
566{
567 if (p->code_bitmap) {
bellard59817cc2004-02-16 22:01:13 +0000568 qemu_free(p->code_bitmap);
bellard9fa3e852004-01-04 18:06:42 +0000569 p->code_bitmap = NULL;
570 }
571 p->code_write_count = 0;
572}
573
bellardfd6ce8f2003-05-14 19:00:11 +0000574/* set to NULL all the 'first_tb' fields in all PageDescs */
575static void page_flush_tb(void)
576{
577 int i, j;
578 PageDesc *p;
579
580 for(i = 0; i < L1_SIZE; i++) {
581 p = l1_map[i];
582 if (p) {
bellard9fa3e852004-01-04 18:06:42 +0000583 for(j = 0; j < L2_SIZE; j++) {
584 p->first_tb = NULL;
585 invalidate_page_bitmap(p);
586 p++;
587 }
bellardfd6ce8f2003-05-14 19:00:11 +0000588 }
589 }
590}
591
592/* flush all the translation blocks */
bellardd4e81642003-05-25 16:46:15 +0000593/* XXX: tb_flush is currently not thread safe */
bellard6a00d602005-11-21 23:25:50 +0000594void tb_flush(CPUState *env1)
bellardfd6ce8f2003-05-14 19:00:11 +0000595{
bellard6a00d602005-11-21 23:25:50 +0000596 CPUState *env;
bellard01243112004-01-04 15:48:17 +0000597#if defined(DEBUG_FLUSH)
blueswir1ab3d1722007-11-04 07:31:40 +0000598 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
599 (unsigned long)(code_gen_ptr - code_gen_buffer),
600 nb_tbs, nb_tbs > 0 ?
601 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
bellardfd6ce8f2003-05-14 19:00:11 +0000602#endif
bellard26a5f132008-05-28 12:30:31 +0000603 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
pbrooka208e542008-03-31 17:07:36 +0000604 cpu_abort(env1, "Internal error: code buffer overflow\n");
605
bellardfd6ce8f2003-05-14 19:00:11 +0000606 nb_tbs = 0;
ths3b46e622007-09-17 08:09:54 +0000607
bellard6a00d602005-11-21 23:25:50 +0000608 for(env = first_cpu; env != NULL; env = env->next_cpu) {
609 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
610 }
bellard9fa3e852004-01-04 18:06:42 +0000611
bellard8a8a6082004-10-03 13:36:49 +0000612 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
bellardfd6ce8f2003-05-14 19:00:11 +0000613 page_flush_tb();
bellard9fa3e852004-01-04 18:06:42 +0000614
bellardfd6ce8f2003-05-14 19:00:11 +0000615 code_gen_ptr = code_gen_buffer;
bellardd4e81642003-05-25 16:46:15 +0000616 /* XXX: flush processor icache at this point if cache flush is
617 expensive */
bellarde3db7222005-01-26 22:00:47 +0000618 tb_flush_count++;
bellardfd6ce8f2003-05-14 19:00:11 +0000619}
620
621#ifdef DEBUG_TB_CHECK
622
j_mayerbc98a7e2007-04-04 07:55:12 +0000623static void tb_invalidate_check(target_ulong address)
bellardfd6ce8f2003-05-14 19:00:11 +0000624{
625 TranslationBlock *tb;
626 int i;
627 address &= TARGET_PAGE_MASK;
pbrook99773bd2006-04-16 15:14:59 +0000628 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
629 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000630 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
631 address >= tb->pc + tb->size)) {
632 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
pbrook99773bd2006-04-16 15:14:59 +0000633 address, (long)tb->pc, tb->size);
bellardfd6ce8f2003-05-14 19:00:11 +0000634 }
635 }
636 }
637}
638
639/* verify that all the pages have correct rights for code */
640static void tb_page_check(void)
641{
642 TranslationBlock *tb;
643 int i, flags1, flags2;
ths3b46e622007-09-17 08:09:54 +0000644
pbrook99773bd2006-04-16 15:14:59 +0000645 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
646 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000647 flags1 = page_get_flags(tb->pc);
648 flags2 = page_get_flags(tb->pc + tb->size - 1);
649 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
650 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
pbrook99773bd2006-04-16 15:14:59 +0000651 (long)tb->pc, tb->size, flags1, flags2);
bellardfd6ce8f2003-05-14 19:00:11 +0000652 }
653 }
654 }
655}
656
blueswir1bdaf78e2008-10-04 07:24:27 +0000657static void tb_jmp_check(TranslationBlock *tb)
bellardd4e81642003-05-25 16:46:15 +0000658{
659 TranslationBlock *tb1;
660 unsigned int n1;
661
662 /* suppress any remaining jumps to this TB */
663 tb1 = tb->jmp_first;
664 for(;;) {
665 n1 = (long)tb1 & 3;
666 tb1 = (TranslationBlock *)((long)tb1 & ~3);
667 if (n1 == 2)
668 break;
669 tb1 = tb1->jmp_next[n1];
670 }
671 /* check end of list */
672 if (tb1 != tb) {
673 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
674 }
675}
676
bellardfd6ce8f2003-05-14 19:00:11 +0000677#endif
678
679/* invalidate one TB */
680static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
681 int next_offset)
682{
683 TranslationBlock *tb1;
684 for(;;) {
685 tb1 = *ptb;
686 if (tb1 == tb) {
687 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
688 break;
689 }
690 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
691 }
692}
693
bellard9fa3e852004-01-04 18:06:42 +0000694static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
695{
696 TranslationBlock *tb1;
697 unsigned int n1;
698
699 for(;;) {
700 tb1 = *ptb;
701 n1 = (long)tb1 & 3;
702 tb1 = (TranslationBlock *)((long)tb1 & ~3);
703 if (tb1 == tb) {
704 *ptb = tb1->page_next[n1];
705 break;
706 }
707 ptb = &tb1->page_next[n1];
708 }
709}
710
bellardd4e81642003-05-25 16:46:15 +0000711static inline void tb_jmp_remove(TranslationBlock *tb, int n)
712{
713 TranslationBlock *tb1, **ptb;
714 unsigned int n1;
715
716 ptb = &tb->jmp_next[n];
717 tb1 = *ptb;
718 if (tb1) {
719 /* find tb(n) in circular list */
720 for(;;) {
721 tb1 = *ptb;
722 n1 = (long)tb1 & 3;
723 tb1 = (TranslationBlock *)((long)tb1 & ~3);
724 if (n1 == n && tb1 == tb)
725 break;
726 if (n1 == 2) {
727 ptb = &tb1->jmp_first;
728 } else {
729 ptb = &tb1->jmp_next[n1];
730 }
731 }
732 /* now we can suppress tb(n) from the list */
733 *ptb = tb->jmp_next[n];
734
735 tb->jmp_next[n] = NULL;
736 }
737}
738
739/* reset the jump entry 'n' of a TB so that it is not chained to
740 another TB */
741static inline void tb_reset_jump(TranslationBlock *tb, int n)
742{
743 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
744}
745
pbrook2e70f6e2008-06-29 01:03:05 +0000746void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000747{
bellard6a00d602005-11-21 23:25:50 +0000748 CPUState *env;
bellardfd6ce8f2003-05-14 19:00:11 +0000749 PageDesc *p;
bellard8a40a182005-11-20 10:35:40 +0000750 unsigned int h, n1;
aurel3200f82b82008-04-27 21:12:55 +0000751 target_phys_addr_t phys_pc;
bellard8a40a182005-11-20 10:35:40 +0000752 TranslationBlock *tb1, *tb2;
ths3b46e622007-09-17 08:09:54 +0000753
bellard9fa3e852004-01-04 18:06:42 +0000754 /* remove the TB from the hash list */
755 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
756 h = tb_phys_hash_func(phys_pc);
ths5fafdf22007-09-16 21:08:06 +0000757 tb_remove(&tb_phys_hash[h], tb,
bellard9fa3e852004-01-04 18:06:42 +0000758 offsetof(TranslationBlock, phys_hash_next));
bellardfd6ce8f2003-05-14 19:00:11 +0000759
bellard9fa3e852004-01-04 18:06:42 +0000760 /* remove the TB from the page list */
761 if (tb->page_addr[0] != page_addr) {
762 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
763 tb_page_remove(&p->first_tb, tb);
764 invalidate_page_bitmap(p);
765 }
766 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
767 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
768 tb_page_remove(&p->first_tb, tb);
769 invalidate_page_bitmap(p);
770 }
771
bellard8a40a182005-11-20 10:35:40 +0000772 tb_invalidated_flag = 1;
773
774 /* remove the TB from the hash list */
775 h = tb_jmp_cache_hash_func(tb->pc);
bellard6a00d602005-11-21 23:25:50 +0000776 for(env = first_cpu; env != NULL; env = env->next_cpu) {
777 if (env->tb_jmp_cache[h] == tb)
778 env->tb_jmp_cache[h] = NULL;
779 }
bellard8a40a182005-11-20 10:35:40 +0000780
781 /* suppress this TB from the two jump lists */
782 tb_jmp_remove(tb, 0);
783 tb_jmp_remove(tb, 1);
784
785 /* suppress any remaining jumps to this TB */
786 tb1 = tb->jmp_first;
787 for(;;) {
788 n1 = (long)tb1 & 3;
789 if (n1 == 2)
790 break;
791 tb1 = (TranslationBlock *)((long)tb1 & ~3);
792 tb2 = tb1->jmp_next[n1];
793 tb_reset_jump(tb1, n1);
794 tb1->jmp_next[n1] = NULL;
795 tb1 = tb2;
796 }
797 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
798
bellarde3db7222005-01-26 22:00:47 +0000799 tb_phys_invalidate_count++;
bellard9fa3e852004-01-04 18:06:42 +0000800}
801
802static inline void set_bits(uint8_t *tab, int start, int len)
803{
804 int end, mask, end1;
805
806 end = start + len;
807 tab += start >> 3;
808 mask = 0xff << (start & 7);
809 if ((start & ~7) == (end & ~7)) {
810 if (start < end) {
811 mask &= ~(0xff << (end & 7));
812 *tab |= mask;
813 }
814 } else {
815 *tab++ |= mask;
816 start = (start + 8) & ~7;
817 end1 = end & ~7;
818 while (start < end1) {
819 *tab++ = 0xff;
820 start += 8;
821 }
822 if (start < end) {
823 mask = ~(0xff << (end & 7));
824 *tab |= mask;
825 }
826 }
827}
828
829static void build_page_bitmap(PageDesc *p)
830{
831 int n, tb_start, tb_end;
832 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +0000833
pbrookb2a70812008-06-09 13:57:23 +0000834 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
bellard9fa3e852004-01-04 18:06:42 +0000835
836 tb = p->first_tb;
837 while (tb != NULL) {
838 n = (long)tb & 3;
839 tb = (TranslationBlock *)((long)tb & ~3);
840 /* NOTE: this is subtle as a TB may span two physical pages */
841 if (n == 0) {
842 /* NOTE: tb_end may be after the end of the page, but
843 it is not a problem */
844 tb_start = tb->pc & ~TARGET_PAGE_MASK;
845 tb_end = tb_start + tb->size;
846 if (tb_end > TARGET_PAGE_SIZE)
847 tb_end = TARGET_PAGE_SIZE;
848 } else {
849 tb_start = 0;
850 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
851 }
852 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
853 tb = tb->page_next[n];
854 }
855}
856
pbrook2e70f6e2008-06-29 01:03:05 +0000857TranslationBlock *tb_gen_code(CPUState *env,
858 target_ulong pc, target_ulong cs_base,
859 int flags, int cflags)
bellardd720b932004-04-25 17:57:43 +0000860{
861 TranslationBlock *tb;
862 uint8_t *tc_ptr;
863 target_ulong phys_pc, phys_page2, virt_page2;
864 int code_gen_size;
865
bellardc27004e2005-01-03 23:35:10 +0000866 phys_pc = get_phys_addr_code(env, pc);
867 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000868 if (!tb) {
869 /* flush must be done */
870 tb_flush(env);
871 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000872 tb = tb_alloc(pc);
pbrook2e70f6e2008-06-29 01:03:05 +0000873 /* Don't forget to invalidate previous TB info. */
874 tb_invalidated_flag = 1;
bellardd720b932004-04-25 17:57:43 +0000875 }
876 tc_ptr = code_gen_ptr;
877 tb->tc_ptr = tc_ptr;
878 tb->cs_base = cs_base;
879 tb->flags = flags;
880 tb->cflags = cflags;
blueswir1d07bde82007-12-11 19:35:45 +0000881 cpu_gen_code(env, tb, &code_gen_size);
bellardd720b932004-04-25 17:57:43 +0000882 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000883
bellardd720b932004-04-25 17:57:43 +0000884 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000885 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellardd720b932004-04-25 17:57:43 +0000886 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000887 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
bellardd720b932004-04-25 17:57:43 +0000888 phys_page2 = get_phys_addr_code(env, virt_page2);
889 }
890 tb_link_phys(tb, phys_pc, phys_page2);
pbrook2e70f6e2008-06-29 01:03:05 +0000891 return tb;
bellardd720b932004-04-25 17:57:43 +0000892}
ths3b46e622007-09-17 08:09:54 +0000893
bellard9fa3e852004-01-04 18:06:42 +0000894/* invalidate all TBs which intersect with the target physical page
895 starting in range [start;end[. NOTE: start and end must refer to
bellardd720b932004-04-25 17:57:43 +0000896 the same physical page. 'is_cpu_write_access' should be true if called
897 from a real cpu write access: the virtual CPU will exit the current
898 TB if code is modified inside this TB. */
aurel3200f82b82008-04-27 21:12:55 +0000899void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
bellardd720b932004-04-25 17:57:43 +0000900 int is_cpu_write_access)
bellard9fa3e852004-01-04 18:06:42 +0000901{
aliguori6b917542008-11-18 19:46:41 +0000902 TranslationBlock *tb, *tb_next, *saved_tb;
bellardd720b932004-04-25 17:57:43 +0000903 CPUState *env = cpu_single_env;
bellard9fa3e852004-01-04 18:06:42 +0000904 target_ulong tb_start, tb_end;
aliguori6b917542008-11-18 19:46:41 +0000905 PageDesc *p;
906 int n;
907#ifdef TARGET_HAS_PRECISE_SMC
908 int current_tb_not_found = is_cpu_write_access;
909 TranslationBlock *current_tb = NULL;
910 int current_tb_modified = 0;
911 target_ulong current_pc = 0;
912 target_ulong current_cs_base = 0;
913 int current_flags = 0;
914#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +0000915
916 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000917 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000918 return;
ths5fafdf22007-09-16 21:08:06 +0000919 if (!p->code_bitmap &&
bellardd720b932004-04-25 17:57:43 +0000920 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
921 is_cpu_write_access) {
bellard9fa3e852004-01-04 18:06:42 +0000922 /* build code bitmap */
923 build_page_bitmap(p);
924 }
925
926 /* we remove all the TBs in the range [start, end[ */
927 /* XXX: see if in some cases it could be faster to invalidate all the code */
928 tb = p->first_tb;
929 while (tb != NULL) {
930 n = (long)tb & 3;
931 tb = (TranslationBlock *)((long)tb & ~3);
932 tb_next = tb->page_next[n];
933 /* NOTE: this is subtle as a TB may span two physical pages */
934 if (n == 0) {
935 /* NOTE: tb_end may be after the end of the page, but
936 it is not a problem */
937 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
938 tb_end = tb_start + tb->size;
939 } else {
940 tb_start = tb->page_addr[1];
941 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
942 }
943 if (!(tb_end <= start || tb_start >= end)) {
bellardd720b932004-04-25 17:57:43 +0000944#ifdef TARGET_HAS_PRECISE_SMC
945 if (current_tb_not_found) {
946 current_tb_not_found = 0;
947 current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000948 if (env->mem_io_pc) {
bellardd720b932004-04-25 17:57:43 +0000949 /* now we have a real cpu fault */
pbrook2e70f6e2008-06-29 01:03:05 +0000950 current_tb = tb_find_pc(env->mem_io_pc);
bellardd720b932004-04-25 17:57:43 +0000951 }
952 }
953 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +0000954 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +0000955 /* If we are modifying the current TB, we must stop
956 its execution. We could be more precise by checking
957 that the modification is after the current PC, but it
958 would require a specialized function to partially
959 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +0000960
bellardd720b932004-04-25 17:57:43 +0000961 current_tb_modified = 1;
ths5fafdf22007-09-16 21:08:06 +0000962 cpu_restore_state(current_tb, env,
pbrook2e70f6e2008-06-29 01:03:05 +0000963 env->mem_io_pc, NULL);
aliguori6b917542008-11-18 19:46:41 +0000964 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
965 &current_flags);
bellardd720b932004-04-25 17:57:43 +0000966 }
967#endif /* TARGET_HAS_PRECISE_SMC */
bellard6f5a9f72005-11-26 20:12:28 +0000968 /* we need to do that to handle the case where a signal
969 occurs while doing tb_phys_invalidate() */
970 saved_tb = NULL;
971 if (env) {
972 saved_tb = env->current_tb;
973 env->current_tb = NULL;
974 }
bellard9fa3e852004-01-04 18:06:42 +0000975 tb_phys_invalidate(tb, -1);
bellard6f5a9f72005-11-26 20:12:28 +0000976 if (env) {
977 env->current_tb = saved_tb;
978 if (env->interrupt_request && env->current_tb)
979 cpu_interrupt(env, env->interrupt_request);
980 }
bellard9fa3e852004-01-04 18:06:42 +0000981 }
982 tb = tb_next;
983 }
984#if !defined(CONFIG_USER_ONLY)
985 /* if no code remaining, no need to continue to use slow writes */
986 if (!p->first_tb) {
987 invalidate_page_bitmap(p);
bellardd720b932004-04-25 17:57:43 +0000988 if (is_cpu_write_access) {
pbrook2e70f6e2008-06-29 01:03:05 +0000989 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
bellardd720b932004-04-25 17:57:43 +0000990 }
991 }
992#endif
993#ifdef TARGET_HAS_PRECISE_SMC
994 if (current_tb_modified) {
995 /* we generate a block containing just the instruction
996 modifying the memory. It will ensure that it cannot modify
997 itself */
bellardea1c1802004-06-14 18:56:36 +0000998 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000999 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001000 cpu_resume_from_signal(env, NULL);
bellard9fa3e852004-01-04 18:06:42 +00001001 }
1002#endif
1003}
1004
1005/* len must be <= 8 and start must be a multiple of len */
aurel3200f82b82008-04-27 21:12:55 +00001006static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
bellard9fa3e852004-01-04 18:06:42 +00001007{
1008 PageDesc *p;
1009 int offset, b;
bellard59817cc2004-02-16 22:01:13 +00001010#if 0
bellarda4193c82004-06-03 14:01:43 +00001011 if (1) {
aliguori93fcfe32009-01-15 22:34:14 +00001012 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1013 cpu_single_env->mem_io_vaddr, len,
1014 cpu_single_env->eip,
1015 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
bellard59817cc2004-02-16 22:01:13 +00001016 }
1017#endif
bellard9fa3e852004-01-04 18:06:42 +00001018 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001019 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00001020 return;
1021 if (p->code_bitmap) {
1022 offset = start & ~TARGET_PAGE_MASK;
1023 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1024 if (b & ((1 << len) - 1))
1025 goto do_invalidate;
1026 } else {
1027 do_invalidate:
bellardd720b932004-04-25 17:57:43 +00001028 tb_invalidate_phys_page_range(start, start + len, 1);
bellard9fa3e852004-01-04 18:06:42 +00001029 }
1030}
1031
bellard9fa3e852004-01-04 18:06:42 +00001032#if !defined(CONFIG_SOFTMMU)
aurel3200f82b82008-04-27 21:12:55 +00001033static void tb_invalidate_phys_page(target_phys_addr_t addr,
bellardd720b932004-04-25 17:57:43 +00001034 unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001035{
aliguori6b917542008-11-18 19:46:41 +00001036 TranslationBlock *tb;
bellard9fa3e852004-01-04 18:06:42 +00001037 PageDesc *p;
aliguori6b917542008-11-18 19:46:41 +00001038 int n;
bellardd720b932004-04-25 17:57:43 +00001039#ifdef TARGET_HAS_PRECISE_SMC
aliguori6b917542008-11-18 19:46:41 +00001040 TranslationBlock *current_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001041 CPUState *env = cpu_single_env;
aliguori6b917542008-11-18 19:46:41 +00001042 int current_tb_modified = 0;
1043 target_ulong current_pc = 0;
1044 target_ulong current_cs_base = 0;
1045 int current_flags = 0;
bellardd720b932004-04-25 17:57:43 +00001046#endif
bellard9fa3e852004-01-04 18:06:42 +00001047
1048 addr &= TARGET_PAGE_MASK;
1049 p = page_find(addr >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001050 if (!p)
bellardfd6ce8f2003-05-14 19:00:11 +00001051 return;
1052 tb = p->first_tb;
bellardd720b932004-04-25 17:57:43 +00001053#ifdef TARGET_HAS_PRECISE_SMC
1054 if (tb && pc != 0) {
1055 current_tb = tb_find_pc(pc);
1056 }
1057#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001058 while (tb != NULL) {
bellard9fa3e852004-01-04 18:06:42 +00001059 n = (long)tb & 3;
1060 tb = (TranslationBlock *)((long)tb & ~3);
bellardd720b932004-04-25 17:57:43 +00001061#ifdef TARGET_HAS_PRECISE_SMC
1062 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +00001063 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +00001064 /* If we are modifying the current TB, we must stop
1065 its execution. We could be more precise by checking
1066 that the modification is after the current PC, but it
1067 would require a specialized function to partially
1068 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +00001069
bellardd720b932004-04-25 17:57:43 +00001070 current_tb_modified = 1;
1071 cpu_restore_state(current_tb, env, pc, puc);
aliguori6b917542008-11-18 19:46:41 +00001072 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1073 &current_flags);
bellardd720b932004-04-25 17:57:43 +00001074 }
1075#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +00001076 tb_phys_invalidate(tb, addr);
1077 tb = tb->page_next[n];
bellardfd6ce8f2003-05-14 19:00:11 +00001078 }
1079 p->first_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001080#ifdef TARGET_HAS_PRECISE_SMC
1081 if (current_tb_modified) {
1082 /* we generate a block containing just the instruction
1083 modifying the memory. It will ensure that it cannot modify
1084 itself */
bellardea1c1802004-06-14 18:56:36 +00001085 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001086 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001087 cpu_resume_from_signal(env, puc);
1088 }
1089#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001090}
bellard9fa3e852004-01-04 18:06:42 +00001091#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001092
1093/* add the tb in the target page and protect it if necessary */
ths5fafdf22007-09-16 21:08:06 +00001094static inline void tb_alloc_page(TranslationBlock *tb,
pbrook53a59602006-03-25 19:31:22 +00001095 unsigned int n, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +00001096{
1097 PageDesc *p;
bellard9fa3e852004-01-04 18:06:42 +00001098 TranslationBlock *last_first_tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001099
bellard9fa3e852004-01-04 18:06:42 +00001100 tb->page_addr[n] = page_addr;
bellard3a7d9292005-08-21 09:26:42 +00001101 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001102 tb->page_next[n] = p->first_tb;
1103 last_first_tb = p->first_tb;
1104 p->first_tb = (TranslationBlock *)((long)tb | n);
1105 invalidate_page_bitmap(p);
1106
bellard107db442004-06-22 18:48:46 +00001107#if defined(TARGET_HAS_SMC) || 1
bellardd720b932004-04-25 17:57:43 +00001108
bellard9fa3e852004-01-04 18:06:42 +00001109#if defined(CONFIG_USER_ONLY)
bellardfd6ce8f2003-05-14 19:00:11 +00001110 if (p->flags & PAGE_WRITE) {
pbrook53a59602006-03-25 19:31:22 +00001111 target_ulong addr;
1112 PageDesc *p2;
bellard9fa3e852004-01-04 18:06:42 +00001113 int prot;
1114
bellardfd6ce8f2003-05-14 19:00:11 +00001115 /* force the host page as non writable (writes will have a
1116 page fault + mprotect overhead) */
pbrook53a59602006-03-25 19:31:22 +00001117 page_addr &= qemu_host_page_mask;
bellardfd6ce8f2003-05-14 19:00:11 +00001118 prot = 0;
pbrook53a59602006-03-25 19:31:22 +00001119 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1120 addr += TARGET_PAGE_SIZE) {
1121
1122 p2 = page_find (addr >> TARGET_PAGE_BITS);
1123 if (!p2)
1124 continue;
1125 prot |= p2->flags;
1126 p2->flags &= ~PAGE_WRITE;
1127 page_get_flags(addr);
1128 }
ths5fafdf22007-09-16 21:08:06 +00001129 mprotect(g2h(page_addr), qemu_host_page_size,
bellardfd6ce8f2003-05-14 19:00:11 +00001130 (prot & PAGE_BITS) & ~PAGE_WRITE);
1131#ifdef DEBUG_TB_INVALIDATE
blueswir1ab3d1722007-11-04 07:31:40 +00001132 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
pbrook53a59602006-03-25 19:31:22 +00001133 page_addr);
bellardfd6ce8f2003-05-14 19:00:11 +00001134#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001135 }
bellard9fa3e852004-01-04 18:06:42 +00001136#else
1137 /* if some code is already present, then the pages are already
1138 protected. So we handle the case where only the first TB is
1139 allocated in a physical page */
1140 if (!last_first_tb) {
bellard6a00d602005-11-21 23:25:50 +00001141 tlb_protect_code(page_addr);
bellard9fa3e852004-01-04 18:06:42 +00001142 }
1143#endif
bellardd720b932004-04-25 17:57:43 +00001144
1145#endif /* TARGET_HAS_SMC */
bellardfd6ce8f2003-05-14 19:00:11 +00001146}
1147
1148/* Allocate a new translation block. Flush the translation buffer if
1149 too many translation blocks or too much generated code. */
bellardc27004e2005-01-03 23:35:10 +00001150TranslationBlock *tb_alloc(target_ulong pc)
bellardfd6ce8f2003-05-14 19:00:11 +00001151{
1152 TranslationBlock *tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001153
bellard26a5f132008-05-28 12:30:31 +00001154 if (nb_tbs >= code_gen_max_blocks ||
1155 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
bellardd4e81642003-05-25 16:46:15 +00001156 return NULL;
bellardfd6ce8f2003-05-14 19:00:11 +00001157 tb = &tbs[nb_tbs++];
1158 tb->pc = pc;
bellardb448f2f2004-02-25 23:24:04 +00001159 tb->cflags = 0;
bellardd4e81642003-05-25 16:46:15 +00001160 return tb;
1161}
1162
pbrook2e70f6e2008-06-29 01:03:05 +00001163void tb_free(TranslationBlock *tb)
1164{
thsbf20dc02008-06-30 17:22:19 +00001165 /* In practice this is mostly used for single use temporary TB
pbrook2e70f6e2008-06-29 01:03:05 +00001166 Ignore the hard cases and just back up if this TB happens to
1167 be the last one generated. */
1168 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1169 code_gen_ptr = tb->tc_ptr;
1170 nb_tbs--;
1171 }
1172}
1173
bellard9fa3e852004-01-04 18:06:42 +00001174/* add a new TB and link it to the physical page tables. phys_page2 is
1175 (-1) to indicate that only one page contains the TB. */
ths5fafdf22007-09-16 21:08:06 +00001176void tb_link_phys(TranslationBlock *tb,
bellard9fa3e852004-01-04 18:06:42 +00001177 target_ulong phys_pc, target_ulong phys_page2)
bellardd4e81642003-05-25 16:46:15 +00001178{
bellard9fa3e852004-01-04 18:06:42 +00001179 unsigned int h;
1180 TranslationBlock **ptb;
1181
pbrookc8a706f2008-06-02 16:16:42 +00001182 /* Grab the mmap lock to stop another thread invalidating this TB
1183 before we are done. */
1184 mmap_lock();
bellard9fa3e852004-01-04 18:06:42 +00001185 /* add in the physical hash table */
1186 h = tb_phys_hash_func(phys_pc);
1187 ptb = &tb_phys_hash[h];
1188 tb->phys_hash_next = *ptb;
1189 *ptb = tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001190
1191 /* add in the page list */
bellard9fa3e852004-01-04 18:06:42 +00001192 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1193 if (phys_page2 != -1)
1194 tb_alloc_page(tb, 1, phys_page2);
1195 else
1196 tb->page_addr[1] = -1;
bellard9fa3e852004-01-04 18:06:42 +00001197
bellardd4e81642003-05-25 16:46:15 +00001198 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1199 tb->jmp_next[0] = NULL;
1200 tb->jmp_next[1] = NULL;
1201
1202 /* init original jump addresses */
1203 if (tb->tb_next_offset[0] != 0xffff)
1204 tb_reset_jump(tb, 0);
1205 if (tb->tb_next_offset[1] != 0xffff)
1206 tb_reset_jump(tb, 1);
bellard8a40a182005-11-20 10:35:40 +00001207
1208#ifdef DEBUG_TB_CHECK
1209 tb_page_check();
1210#endif
pbrookc8a706f2008-06-02 16:16:42 +00001211 mmap_unlock();
bellardfd6ce8f2003-05-14 19:00:11 +00001212}
1213
bellarda513fe12003-05-27 23:29:48 +00001214/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1215 tb[1].tc_ptr. Return NULL if not found */
1216TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1217{
1218 int m_min, m_max, m;
1219 unsigned long v;
1220 TranslationBlock *tb;
1221
1222 if (nb_tbs <= 0)
1223 return NULL;
1224 if (tc_ptr < (unsigned long)code_gen_buffer ||
1225 tc_ptr >= (unsigned long)code_gen_ptr)
1226 return NULL;
1227 /* binary search (cf Knuth) */
1228 m_min = 0;
1229 m_max = nb_tbs - 1;
1230 while (m_min <= m_max) {
1231 m = (m_min + m_max) >> 1;
1232 tb = &tbs[m];
1233 v = (unsigned long)tb->tc_ptr;
1234 if (v == tc_ptr)
1235 return tb;
1236 else if (tc_ptr < v) {
1237 m_max = m - 1;
1238 } else {
1239 m_min = m + 1;
1240 }
ths5fafdf22007-09-16 21:08:06 +00001241 }
bellarda513fe12003-05-27 23:29:48 +00001242 return &tbs[m_max];
1243}
bellard75012672003-06-21 13:11:07 +00001244
bellardea041c02003-06-25 16:16:50 +00001245static void tb_reset_jump_recursive(TranslationBlock *tb);
1246
1247static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1248{
1249 TranslationBlock *tb1, *tb_next, **ptb;
1250 unsigned int n1;
1251
1252 tb1 = tb->jmp_next[n];
1253 if (tb1 != NULL) {
1254 /* find head of list */
1255 for(;;) {
1256 n1 = (long)tb1 & 3;
1257 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1258 if (n1 == 2)
1259 break;
1260 tb1 = tb1->jmp_next[n1];
1261 }
1262 /* we are now sure now that tb jumps to tb1 */
1263 tb_next = tb1;
1264
1265 /* remove tb from the jmp_first list */
1266 ptb = &tb_next->jmp_first;
1267 for(;;) {
1268 tb1 = *ptb;
1269 n1 = (long)tb1 & 3;
1270 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1271 if (n1 == n && tb1 == tb)
1272 break;
1273 ptb = &tb1->jmp_next[n1];
1274 }
1275 *ptb = tb->jmp_next[n];
1276 tb->jmp_next[n] = NULL;
ths3b46e622007-09-17 08:09:54 +00001277
bellardea041c02003-06-25 16:16:50 +00001278 /* suppress the jump to next tb in generated code */
1279 tb_reset_jump(tb, n);
1280
bellard01243112004-01-04 15:48:17 +00001281 /* suppress jumps in the tb on which we could have jumped */
bellardea041c02003-06-25 16:16:50 +00001282 tb_reset_jump_recursive(tb_next);
1283 }
1284}
1285
1286static void tb_reset_jump_recursive(TranslationBlock *tb)
1287{
1288 tb_reset_jump_recursive2(tb, 0);
1289 tb_reset_jump_recursive2(tb, 1);
1290}
1291
bellard1fddef42005-04-17 19:16:13 +00001292#if defined(TARGET_HAS_ICE)
bellardd720b932004-04-25 17:57:43 +00001293static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1294{
j_mayer9b3c35e2007-04-07 11:21:28 +00001295 target_phys_addr_t addr;
1296 target_ulong pd;
pbrookc2f07f82006-04-08 17:14:56 +00001297 ram_addr_t ram_addr;
1298 PhysPageDesc *p;
bellardd720b932004-04-25 17:57:43 +00001299
pbrookc2f07f82006-04-08 17:14:56 +00001300 addr = cpu_get_phys_page_debug(env, pc);
1301 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1302 if (!p) {
1303 pd = IO_MEM_UNASSIGNED;
1304 } else {
1305 pd = p->phys_offset;
1306 }
1307 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
pbrook706cd4b2006-04-08 17:36:21 +00001308 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
bellardd720b932004-04-25 17:57:43 +00001309}
bellardc27004e2005-01-03 23:35:10 +00001310#endif
bellardd720b932004-04-25 17:57:43 +00001311
pbrook6658ffb2007-03-16 23:58:11 +00001312/* Add a watchpoint. */
aliguoria1d1bb32008-11-18 20:07:32 +00001313int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1314 int flags, CPUWatchpoint **watchpoint)
pbrook6658ffb2007-03-16 23:58:11 +00001315{
aliguorib4051332008-11-18 20:14:20 +00001316 target_ulong len_mask = ~(len - 1);
aliguoric0ce9982008-11-25 22:13:57 +00001317 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001318
aliguorib4051332008-11-18 20:14:20 +00001319 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1320 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1321 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1322 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1323 return -EINVAL;
1324 }
aliguoria1d1bb32008-11-18 20:07:32 +00001325 wp = qemu_malloc(sizeof(*wp));
pbrook6658ffb2007-03-16 23:58:11 +00001326
aliguoria1d1bb32008-11-18 20:07:32 +00001327 wp->vaddr = addr;
aliguorib4051332008-11-18 20:14:20 +00001328 wp->len_mask = len_mask;
aliguoria1d1bb32008-11-18 20:07:32 +00001329 wp->flags = flags;
1330
aliguori2dc9f412008-11-18 20:56:59 +00001331 /* keep all GDB-injected watchpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001332 if (flags & BP_GDB)
1333 TAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
1334 else
1335 TAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001336
pbrook6658ffb2007-03-16 23:58:11 +00001337 tlb_flush_page(env, addr);
aliguoria1d1bb32008-11-18 20:07:32 +00001338
1339 if (watchpoint)
1340 *watchpoint = wp;
1341 return 0;
pbrook6658ffb2007-03-16 23:58:11 +00001342}
1343
aliguoria1d1bb32008-11-18 20:07:32 +00001344/* Remove a specific watchpoint. */
1345int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1346 int flags)
pbrook6658ffb2007-03-16 23:58:11 +00001347{
aliguorib4051332008-11-18 20:14:20 +00001348 target_ulong len_mask = ~(len - 1);
aliguoria1d1bb32008-11-18 20:07:32 +00001349 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001350
aliguoric0ce9982008-11-25 22:13:57 +00001351 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00001352 if (addr == wp->vaddr && len_mask == wp->len_mask
aliguori6e140f22008-11-18 20:37:55 +00001353 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
aliguoria1d1bb32008-11-18 20:07:32 +00001354 cpu_watchpoint_remove_by_ref(env, wp);
pbrook6658ffb2007-03-16 23:58:11 +00001355 return 0;
1356 }
1357 }
aliguoria1d1bb32008-11-18 20:07:32 +00001358 return -ENOENT;
pbrook6658ffb2007-03-16 23:58:11 +00001359}
1360
aliguoria1d1bb32008-11-18 20:07:32 +00001361/* Remove a specific watchpoint by reference. */
1362void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1363{
aliguoric0ce9982008-11-25 22:13:57 +00001364 TAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
edgar_igl7d03f822008-05-17 18:58:29 +00001365
aliguoria1d1bb32008-11-18 20:07:32 +00001366 tlb_flush_page(env, watchpoint->vaddr);
1367
1368 qemu_free(watchpoint);
edgar_igl7d03f822008-05-17 18:58:29 +00001369}
1370
aliguoria1d1bb32008-11-18 20:07:32 +00001371/* Remove all matching watchpoints. */
1372void cpu_watchpoint_remove_all(CPUState *env, int mask)
1373{
aliguoric0ce9982008-11-25 22:13:57 +00001374 CPUWatchpoint *wp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001375
aliguoric0ce9982008-11-25 22:13:57 +00001376 TAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001377 if (wp->flags & mask)
1378 cpu_watchpoint_remove_by_ref(env, wp);
aliguoric0ce9982008-11-25 22:13:57 +00001379 }
aliguoria1d1bb32008-11-18 20:07:32 +00001380}
1381
1382/* Add a breakpoint. */
1383int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1384 CPUBreakpoint **breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001385{
bellard1fddef42005-04-17 19:16:13 +00001386#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001387 CPUBreakpoint *bp;
ths3b46e622007-09-17 08:09:54 +00001388
aliguoria1d1bb32008-11-18 20:07:32 +00001389 bp = qemu_malloc(sizeof(*bp));
aliguoria1d1bb32008-11-18 20:07:32 +00001390
1391 bp->pc = pc;
1392 bp->flags = flags;
1393
aliguori2dc9f412008-11-18 20:56:59 +00001394 /* keep all GDB-injected breakpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001395 if (flags & BP_GDB)
1396 TAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
1397 else
1398 TAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001399
1400 breakpoint_invalidate(env, pc);
1401
1402 if (breakpoint)
1403 *breakpoint = bp;
1404 return 0;
1405#else
1406 return -ENOSYS;
1407#endif
1408}
1409
1410/* Remove a specific breakpoint. */
1411int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1412{
1413#if defined(TARGET_HAS_ICE)
1414 CPUBreakpoint *bp;
1415
aliguoric0ce9982008-11-25 22:13:57 +00001416 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00001417 if (bp->pc == pc && bp->flags == flags) {
1418 cpu_breakpoint_remove_by_ref(env, bp);
bellard4c3a88a2003-07-26 12:06:08 +00001419 return 0;
aliguoria1d1bb32008-11-18 20:07:32 +00001420 }
bellard4c3a88a2003-07-26 12:06:08 +00001421 }
aliguoria1d1bb32008-11-18 20:07:32 +00001422 return -ENOENT;
bellard4c3a88a2003-07-26 12:06:08 +00001423#else
aliguoria1d1bb32008-11-18 20:07:32 +00001424 return -ENOSYS;
bellard4c3a88a2003-07-26 12:06:08 +00001425#endif
1426}
1427
aliguoria1d1bb32008-11-18 20:07:32 +00001428/* Remove a specific breakpoint by reference. */
1429void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001430{
bellard1fddef42005-04-17 19:16:13 +00001431#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001432 TAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
bellardd720b932004-04-25 17:57:43 +00001433
aliguoria1d1bb32008-11-18 20:07:32 +00001434 breakpoint_invalidate(env, breakpoint->pc);
1435
1436 qemu_free(breakpoint);
1437#endif
1438}
1439
1440/* Remove all matching breakpoints. */
1441void cpu_breakpoint_remove_all(CPUState *env, int mask)
1442{
1443#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001444 CPUBreakpoint *bp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001445
aliguoric0ce9982008-11-25 22:13:57 +00001446 TAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001447 if (bp->flags & mask)
1448 cpu_breakpoint_remove_by_ref(env, bp);
aliguoric0ce9982008-11-25 22:13:57 +00001449 }
bellard4c3a88a2003-07-26 12:06:08 +00001450#endif
1451}
1452
bellardc33a3462003-07-29 20:50:33 +00001453/* enable or disable single step mode. EXCP_DEBUG is returned by the
1454 CPU loop after each instruction */
1455void cpu_single_step(CPUState *env, int enabled)
1456{
bellard1fddef42005-04-17 19:16:13 +00001457#if defined(TARGET_HAS_ICE)
bellardc33a3462003-07-29 20:50:33 +00001458 if (env->singlestep_enabled != enabled) {
1459 env->singlestep_enabled = enabled;
1460 /* must flush all the translated code to avoid inconsistancies */
bellard9fa3e852004-01-04 18:06:42 +00001461 /* XXX: only flush what is necessary */
bellard01243112004-01-04 15:48:17 +00001462 tb_flush(env);
bellardc33a3462003-07-29 20:50:33 +00001463 }
1464#endif
1465}
1466
bellard34865132003-10-05 14:28:56 +00001467/* enable or disable low levels log */
1468void cpu_set_log(int log_flags)
1469{
1470 loglevel = log_flags;
1471 if (loglevel && !logfile) {
pbrook11fcfab2007-07-01 18:21:11 +00001472 logfile = fopen(logfilename, log_append ? "a" : "w");
bellard34865132003-10-05 14:28:56 +00001473 if (!logfile) {
1474 perror(logfilename);
1475 _exit(1);
1476 }
bellard9fa3e852004-01-04 18:06:42 +00001477#if !defined(CONFIG_SOFTMMU)
1478 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1479 {
blueswir1b55266b2008-09-20 08:07:15 +00001480 static char logfile_buf[4096];
bellard9fa3e852004-01-04 18:06:42 +00001481 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1482 }
1483#else
bellard34865132003-10-05 14:28:56 +00001484 setvbuf(logfile, NULL, _IOLBF, 0);
bellard9fa3e852004-01-04 18:06:42 +00001485#endif
pbrooke735b912007-06-30 13:53:24 +00001486 log_append = 1;
1487 }
1488 if (!loglevel && logfile) {
1489 fclose(logfile);
1490 logfile = NULL;
bellard34865132003-10-05 14:28:56 +00001491 }
1492}
1493
1494void cpu_set_log_filename(const char *filename)
1495{
1496 logfilename = strdup(filename);
pbrooke735b912007-06-30 13:53:24 +00001497 if (logfile) {
1498 fclose(logfile);
1499 logfile = NULL;
1500 }
1501 cpu_set_log(loglevel);
bellard34865132003-10-05 14:28:56 +00001502}
bellardc33a3462003-07-29 20:50:33 +00001503
aurel323098dba2009-03-07 21:28:24 +00001504static void cpu_unlink_tb(CPUState *env)
bellardea041c02003-06-25 16:16:50 +00001505{
pbrookd5975362008-06-07 20:50:51 +00001506#if defined(USE_NPTL)
1507 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1508 problem and hope the cpu will stop of its own accord. For userspace
1509 emulation this often isn't actually as bad as it sounds. Often
1510 signals are used primarily to interrupt blocking syscalls. */
1511#else
aurel323098dba2009-03-07 21:28:24 +00001512 TranslationBlock *tb;
1513 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1514
1515 tb = env->current_tb;
1516 /* if the cpu is currently executing code, we must unlink it and
1517 all the potentially executing TB */
1518 if (tb && !testandset(&interrupt_lock)) {
1519 env->current_tb = NULL;
1520 tb_reset_jump_recursive(tb);
1521 resetlock(&interrupt_lock);
1522 }
1523#endif
1524}
1525
1526/* mask must never be zero, except for A20 change call */
1527void cpu_interrupt(CPUState *env, int mask)
1528{
1529 int old_mask;
1530
1531 old_mask = env->interrupt_request;
1532 env->interrupt_request |= mask;
1533
pbrook2e70f6e2008-06-29 01:03:05 +00001534 if (use_icount) {
pbrook266910c2008-07-09 15:31:50 +00001535 env->icount_decr.u16.high = 0xffff;
pbrook2e70f6e2008-06-29 01:03:05 +00001536#ifndef CONFIG_USER_ONLY
pbrook2e70f6e2008-06-29 01:03:05 +00001537 if (!can_do_io(env)
aurel32be214e62009-03-06 21:48:00 +00001538 && (mask & ~old_mask) != 0) {
pbrook2e70f6e2008-06-29 01:03:05 +00001539 cpu_abort(env, "Raised interrupt while not in I/O function");
1540 }
1541#endif
1542 } else {
aurel323098dba2009-03-07 21:28:24 +00001543 cpu_unlink_tb(env);
bellardea041c02003-06-25 16:16:50 +00001544 }
1545}
1546
bellardb54ad042004-05-20 13:42:52 +00001547void cpu_reset_interrupt(CPUState *env, int mask)
1548{
1549 env->interrupt_request &= ~mask;
1550}
1551
aurel323098dba2009-03-07 21:28:24 +00001552void cpu_exit(CPUState *env)
1553{
1554 env->exit_request = 1;
1555 cpu_unlink_tb(env);
1556}
1557
blueswir1c7cd6a32008-10-02 18:27:46 +00001558const CPULogItem cpu_log_items[] = {
ths5fafdf22007-09-16 21:08:06 +00001559 { CPU_LOG_TB_OUT_ASM, "out_asm",
bellardf193c792004-03-21 17:06:25 +00001560 "show generated host assembly code for each compiled TB" },
1561 { CPU_LOG_TB_IN_ASM, "in_asm",
1562 "show target assembly code for each compiled TB" },
ths5fafdf22007-09-16 21:08:06 +00001563 { CPU_LOG_TB_OP, "op",
bellard57fec1f2008-02-01 10:50:11 +00001564 "show micro ops for each compiled TB" },
bellardf193c792004-03-21 17:06:25 +00001565 { CPU_LOG_TB_OP_OPT, "op_opt",
blueswir1e01a1152008-03-14 17:37:11 +00001566 "show micro ops "
1567#ifdef TARGET_I386
1568 "before eflags optimization and "
bellardf193c792004-03-21 17:06:25 +00001569#endif
blueswir1e01a1152008-03-14 17:37:11 +00001570 "after liveness analysis" },
bellardf193c792004-03-21 17:06:25 +00001571 { CPU_LOG_INT, "int",
1572 "show interrupts/exceptions in short format" },
1573 { CPU_LOG_EXEC, "exec",
1574 "show trace before each executed TB (lots of logs)" },
bellard9fddaa02004-05-21 12:59:32 +00001575 { CPU_LOG_TB_CPU, "cpu",
thse91c8a72007-06-03 13:35:16 +00001576 "show CPU state before block translation" },
bellardf193c792004-03-21 17:06:25 +00001577#ifdef TARGET_I386
1578 { CPU_LOG_PCALL, "pcall",
1579 "show protected mode far calls/returns/exceptions" },
aliguorieca1bdf2009-01-26 19:54:31 +00001580 { CPU_LOG_RESET, "cpu_reset",
1581 "show CPU state before CPU resets" },
bellardf193c792004-03-21 17:06:25 +00001582#endif
bellard8e3a9fd2004-10-09 17:32:58 +00001583#ifdef DEBUG_IOPORT
bellardfd872592004-05-12 19:11:15 +00001584 { CPU_LOG_IOPORT, "ioport",
1585 "show all i/o ports accesses" },
bellard8e3a9fd2004-10-09 17:32:58 +00001586#endif
bellardf193c792004-03-21 17:06:25 +00001587 { 0, NULL, NULL },
1588};
1589
1590static int cmp1(const char *s1, int n, const char *s2)
1591{
1592 if (strlen(s2) != n)
1593 return 0;
1594 return memcmp(s1, s2, n) == 0;
1595}
ths3b46e622007-09-17 08:09:54 +00001596
bellardf193c792004-03-21 17:06:25 +00001597/* takes a comma separated list of log masks. Return 0 if error. */
1598int cpu_str_to_log_mask(const char *str)
1599{
blueswir1c7cd6a32008-10-02 18:27:46 +00001600 const CPULogItem *item;
bellardf193c792004-03-21 17:06:25 +00001601 int mask;
1602 const char *p, *p1;
1603
1604 p = str;
1605 mask = 0;
1606 for(;;) {
1607 p1 = strchr(p, ',');
1608 if (!p1)
1609 p1 = p + strlen(p);
bellard8e3a9fd2004-10-09 17:32:58 +00001610 if(cmp1(p,p1-p,"all")) {
1611 for(item = cpu_log_items; item->mask != 0; item++) {
1612 mask |= item->mask;
1613 }
1614 } else {
bellardf193c792004-03-21 17:06:25 +00001615 for(item = cpu_log_items; item->mask != 0; item++) {
1616 if (cmp1(p, p1 - p, item->name))
1617 goto found;
1618 }
1619 return 0;
bellard8e3a9fd2004-10-09 17:32:58 +00001620 }
bellardf193c792004-03-21 17:06:25 +00001621 found:
1622 mask |= item->mask;
1623 if (*p1 != ',')
1624 break;
1625 p = p1 + 1;
1626 }
1627 return mask;
1628}
bellardea041c02003-06-25 16:16:50 +00001629
bellard75012672003-06-21 13:11:07 +00001630void cpu_abort(CPUState *env, const char *fmt, ...)
1631{
1632 va_list ap;
pbrook493ae1f2007-11-23 16:53:59 +00001633 va_list ap2;
bellard75012672003-06-21 13:11:07 +00001634
1635 va_start(ap, fmt);
pbrook493ae1f2007-11-23 16:53:59 +00001636 va_copy(ap2, ap);
bellard75012672003-06-21 13:11:07 +00001637 fprintf(stderr, "qemu: fatal: ");
1638 vfprintf(stderr, fmt, ap);
1639 fprintf(stderr, "\n");
1640#ifdef TARGET_I386
bellard7fe48482004-10-09 18:08:01 +00001641 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1642#else
1643 cpu_dump_state(env, stderr, fprintf, 0);
bellard75012672003-06-21 13:11:07 +00001644#endif
aliguori93fcfe32009-01-15 22:34:14 +00001645 if (qemu_log_enabled()) {
1646 qemu_log("qemu: fatal: ");
1647 qemu_log_vprintf(fmt, ap2);
1648 qemu_log("\n");
j_mayerf9373292007-09-29 12:18:20 +00001649#ifdef TARGET_I386
aliguori93fcfe32009-01-15 22:34:14 +00001650 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
j_mayerf9373292007-09-29 12:18:20 +00001651#else
aliguori93fcfe32009-01-15 22:34:14 +00001652 log_cpu_state(env, 0);
j_mayerf9373292007-09-29 12:18:20 +00001653#endif
aliguori31b1a7b2009-01-15 22:35:09 +00001654 qemu_log_flush();
aliguori93fcfe32009-01-15 22:34:14 +00001655 qemu_log_close();
balrog924edca2007-06-10 14:07:13 +00001656 }
pbrook493ae1f2007-11-23 16:53:59 +00001657 va_end(ap2);
j_mayerf9373292007-09-29 12:18:20 +00001658 va_end(ap);
bellard75012672003-06-21 13:11:07 +00001659 abort();
1660}
1661
thsc5be9f02007-02-28 20:20:53 +00001662CPUState *cpu_copy(CPUState *env)
1663{
ths01ba9812007-12-09 02:22:57 +00001664 CPUState *new_env = cpu_init(env->cpu_model_str);
thsc5be9f02007-02-28 20:20:53 +00001665 CPUState *next_cpu = new_env->next_cpu;
1666 int cpu_index = new_env->cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001667#if defined(TARGET_HAS_ICE)
1668 CPUBreakpoint *bp;
1669 CPUWatchpoint *wp;
1670#endif
1671
thsc5be9f02007-02-28 20:20:53 +00001672 memcpy(new_env, env, sizeof(CPUState));
aliguori5a38f082009-01-15 20:16:51 +00001673
1674 /* Preserve chaining and index. */
thsc5be9f02007-02-28 20:20:53 +00001675 new_env->next_cpu = next_cpu;
1676 new_env->cpu_index = cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001677
1678 /* Clone all break/watchpoints.
1679 Note: Once we support ptrace with hw-debug register access, make sure
1680 BP_CPU break/watchpoints are handled correctly on clone. */
1681 TAILQ_INIT(&env->breakpoints);
1682 TAILQ_INIT(&env->watchpoints);
1683#if defined(TARGET_HAS_ICE)
1684 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1685 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
1686 }
1687 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
1688 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
1689 wp->flags, NULL);
1690 }
1691#endif
1692
thsc5be9f02007-02-28 20:20:53 +00001693 return new_env;
1694}
1695
bellard01243112004-01-04 15:48:17 +00001696#if !defined(CONFIG_USER_ONLY)
1697
edgar_igl5c751e92008-05-06 08:44:21 +00001698static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1699{
1700 unsigned int i;
1701
1702 /* Discard jump cache entries for any tb which might potentially
1703 overlap the flushed page. */
1704 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1705 memset (&env->tb_jmp_cache[i], 0,
1706 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1707
1708 i = tb_jmp_cache_hash_page(addr);
1709 memset (&env->tb_jmp_cache[i], 0,
1710 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1711}
1712
bellardee8b7022004-02-03 23:35:10 +00001713/* NOTE: if flush_global is true, also flush global entries (not
1714 implemented yet) */
1715void tlb_flush(CPUState *env, int flush_global)
bellard33417e72003-08-10 21:47:01 +00001716{
bellard33417e72003-08-10 21:47:01 +00001717 int i;
bellard01243112004-01-04 15:48:17 +00001718
bellard9fa3e852004-01-04 18:06:42 +00001719#if defined(DEBUG_TLB)
1720 printf("tlb_flush:\n");
1721#endif
bellard01243112004-01-04 15:48:17 +00001722 /* must reset current TB so that interrupts cannot modify the
1723 links while we are modifying them */
1724 env->current_tb = NULL;
1725
bellard33417e72003-08-10 21:47:01 +00001726 for(i = 0; i < CPU_TLB_SIZE; i++) {
bellard84b7b8e2005-11-28 21:19:04 +00001727 env->tlb_table[0][i].addr_read = -1;
1728 env->tlb_table[0][i].addr_write = -1;
1729 env->tlb_table[0][i].addr_code = -1;
1730 env->tlb_table[1][i].addr_read = -1;
1731 env->tlb_table[1][i].addr_write = -1;
1732 env->tlb_table[1][i].addr_code = -1;
j_mayer6fa4cea2007-04-05 06:43:27 +00001733#if (NB_MMU_MODES >= 3)
1734 env->tlb_table[2][i].addr_read = -1;
1735 env->tlb_table[2][i].addr_write = -1;
1736 env->tlb_table[2][i].addr_code = -1;
1737#if (NB_MMU_MODES == 4)
1738 env->tlb_table[3][i].addr_read = -1;
1739 env->tlb_table[3][i].addr_write = -1;
1740 env->tlb_table[3][i].addr_code = -1;
1741#endif
1742#endif
bellard33417e72003-08-10 21:47:01 +00001743 }
bellard9fa3e852004-01-04 18:06:42 +00001744
bellard8a40a182005-11-20 10:35:40 +00001745 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
bellard9fa3e852004-01-04 18:06:42 +00001746
bellard0a962c02005-02-10 22:00:27 +00001747#ifdef USE_KQEMU
1748 if (env->kqemu_enabled) {
1749 kqemu_flush(env, flush_global);
1750 }
1751#endif
bellarde3db7222005-01-26 22:00:47 +00001752 tlb_flush_count++;
bellard33417e72003-08-10 21:47:01 +00001753}
1754
bellard274da6b2004-05-20 21:56:27 +00001755static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
bellard61382a52003-10-27 21:22:23 +00001756{
ths5fafdf22007-09-16 21:08:06 +00001757 if (addr == (tlb_entry->addr_read &
bellard84b7b8e2005-11-28 21:19:04 +00001758 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001759 addr == (tlb_entry->addr_write &
bellard84b7b8e2005-11-28 21:19:04 +00001760 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001761 addr == (tlb_entry->addr_code &
bellard84b7b8e2005-11-28 21:19:04 +00001762 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1763 tlb_entry->addr_read = -1;
1764 tlb_entry->addr_write = -1;
1765 tlb_entry->addr_code = -1;
1766 }
bellard61382a52003-10-27 21:22:23 +00001767}
1768
bellard2e126692004-04-25 21:28:44 +00001769void tlb_flush_page(CPUState *env, target_ulong addr)
bellard33417e72003-08-10 21:47:01 +00001770{
bellard8a40a182005-11-20 10:35:40 +00001771 int i;
bellard01243112004-01-04 15:48:17 +00001772
bellard9fa3e852004-01-04 18:06:42 +00001773#if defined(DEBUG_TLB)
bellard108c49b2005-07-24 12:55:09 +00001774 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
bellard9fa3e852004-01-04 18:06:42 +00001775#endif
bellard01243112004-01-04 15:48:17 +00001776 /* must reset current TB so that interrupts cannot modify the
1777 links while we are modifying them */
1778 env->current_tb = NULL;
bellard33417e72003-08-10 21:47:01 +00001779
bellard61382a52003-10-27 21:22:23 +00001780 addr &= TARGET_PAGE_MASK;
bellard33417e72003-08-10 21:47:01 +00001781 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard84b7b8e2005-11-28 21:19:04 +00001782 tlb_flush_entry(&env->tlb_table[0][i], addr);
1783 tlb_flush_entry(&env->tlb_table[1][i], addr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001784#if (NB_MMU_MODES >= 3)
1785 tlb_flush_entry(&env->tlb_table[2][i], addr);
1786#if (NB_MMU_MODES == 4)
1787 tlb_flush_entry(&env->tlb_table[3][i], addr);
1788#endif
1789#endif
bellard01243112004-01-04 15:48:17 +00001790
edgar_igl5c751e92008-05-06 08:44:21 +00001791 tlb_flush_jmp_cache(env, addr);
bellard9fa3e852004-01-04 18:06:42 +00001792
bellard0a962c02005-02-10 22:00:27 +00001793#ifdef USE_KQEMU
1794 if (env->kqemu_enabled) {
1795 kqemu_flush_page(env, addr);
1796 }
1797#endif
bellard9fa3e852004-01-04 18:06:42 +00001798}
1799
bellard9fa3e852004-01-04 18:06:42 +00001800/* update the TLBs so that writes to code in the virtual page 'addr'
1801 can be detected */
bellard6a00d602005-11-21 23:25:50 +00001802static void tlb_protect_code(ram_addr_t ram_addr)
bellard61382a52003-10-27 21:22:23 +00001803{
ths5fafdf22007-09-16 21:08:06 +00001804 cpu_physical_memory_reset_dirty(ram_addr,
bellard6a00d602005-11-21 23:25:50 +00001805 ram_addr + TARGET_PAGE_SIZE,
1806 CODE_DIRTY_FLAG);
bellard9fa3e852004-01-04 18:06:42 +00001807}
1808
bellard9fa3e852004-01-04 18:06:42 +00001809/* update the TLB so that writes in physical page 'phys_addr' are no longer
bellard3a7d9292005-08-21 09:26:42 +00001810 tested for self modifying code */
ths5fafdf22007-09-16 21:08:06 +00001811static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +00001812 target_ulong vaddr)
bellard9fa3e852004-01-04 18:06:42 +00001813{
bellard3a7d9292005-08-21 09:26:42 +00001814 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
bellard1ccde1c2004-02-06 19:46:14 +00001815}
1816
ths5fafdf22007-09-16 21:08:06 +00001817static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
bellard1ccde1c2004-02-06 19:46:14 +00001818 unsigned long start, unsigned long length)
1819{
1820 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00001821 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1822 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00001823 if ((addr - start) < length) {
pbrook0f459d12008-06-09 00:20:13 +00001824 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
bellard1ccde1c2004-02-06 19:46:14 +00001825 }
1826 }
1827}
1828
bellard3a7d9292005-08-21 09:26:42 +00001829void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +00001830 int dirty_flags)
bellard1ccde1c2004-02-06 19:46:14 +00001831{
1832 CPUState *env;
bellard4f2ac232004-04-26 19:44:02 +00001833 unsigned long length, start1;
bellard0a962c02005-02-10 22:00:27 +00001834 int i, mask, len;
1835 uint8_t *p;
bellard1ccde1c2004-02-06 19:46:14 +00001836
1837 start &= TARGET_PAGE_MASK;
1838 end = TARGET_PAGE_ALIGN(end);
1839
1840 length = end - start;
1841 if (length == 0)
1842 return;
bellard0a962c02005-02-10 22:00:27 +00001843 len = length >> TARGET_PAGE_BITS;
bellard3a7d9292005-08-21 09:26:42 +00001844#ifdef USE_KQEMU
bellard6a00d602005-11-21 23:25:50 +00001845 /* XXX: should not depend on cpu context */
1846 env = first_cpu;
bellard3a7d9292005-08-21 09:26:42 +00001847 if (env->kqemu_enabled) {
bellardf23db162005-08-21 19:12:28 +00001848 ram_addr_t addr;
1849 addr = start;
1850 for(i = 0; i < len; i++) {
1851 kqemu_set_notdirty(env, addr);
1852 addr += TARGET_PAGE_SIZE;
1853 }
bellard3a7d9292005-08-21 09:26:42 +00001854 }
1855#endif
bellardf23db162005-08-21 19:12:28 +00001856 mask = ~dirty_flags;
1857 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1858 for(i = 0; i < len; i++)
1859 p[i] &= mask;
1860
bellard1ccde1c2004-02-06 19:46:14 +00001861 /* we modify the TLB cache so that the dirty bit will be set again
1862 when accessing the range */
bellard59817cc2004-02-16 22:01:13 +00001863 start1 = start + (unsigned long)phys_ram_base;
bellard6a00d602005-11-21 23:25:50 +00001864 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1865 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001866 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
bellard6a00d602005-11-21 23:25:50 +00001867 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001868 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
j_mayer6fa4cea2007-04-05 06:43:27 +00001869#if (NB_MMU_MODES >= 3)
1870 for(i = 0; i < CPU_TLB_SIZE; i++)
1871 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1872#if (NB_MMU_MODES == 4)
1873 for(i = 0; i < CPU_TLB_SIZE; i++)
1874 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1875#endif
1876#endif
bellard6a00d602005-11-21 23:25:50 +00001877 }
bellard1ccde1c2004-02-06 19:46:14 +00001878}
1879
aliguori74576192008-10-06 14:02:03 +00001880int cpu_physical_memory_set_dirty_tracking(int enable)
1881{
1882 in_migration = enable;
1883 return 0;
1884}
1885
1886int cpu_physical_memory_get_dirty_tracking(void)
1887{
1888 return in_migration;
1889}
1890
aliguori2bec46d2008-11-24 20:21:41 +00001891void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr)
1892{
1893 if (kvm_enabled())
1894 kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
1895}
1896
bellard3a7d9292005-08-21 09:26:42 +00001897static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1898{
1899 ram_addr_t ram_addr;
1900
bellard84b7b8e2005-11-28 21:19:04 +00001901 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
ths5fafdf22007-09-16 21:08:06 +00001902 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
bellard3a7d9292005-08-21 09:26:42 +00001903 tlb_entry->addend - (unsigned long)phys_ram_base;
1904 if (!cpu_physical_memory_is_dirty(ram_addr)) {
pbrook0f459d12008-06-09 00:20:13 +00001905 tlb_entry->addr_write |= TLB_NOTDIRTY;
bellard3a7d9292005-08-21 09:26:42 +00001906 }
1907 }
1908}
1909
1910/* update the TLB according to the current state of the dirty bits */
1911void cpu_tlb_update_dirty(CPUState *env)
1912{
1913 int i;
1914 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001915 tlb_update_dirty(&env->tlb_table[0][i]);
bellard3a7d9292005-08-21 09:26:42 +00001916 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001917 tlb_update_dirty(&env->tlb_table[1][i]);
j_mayer6fa4cea2007-04-05 06:43:27 +00001918#if (NB_MMU_MODES >= 3)
1919 for(i = 0; i < CPU_TLB_SIZE; i++)
1920 tlb_update_dirty(&env->tlb_table[2][i]);
1921#if (NB_MMU_MODES == 4)
1922 for(i = 0; i < CPU_TLB_SIZE; i++)
1923 tlb_update_dirty(&env->tlb_table[3][i]);
1924#endif
1925#endif
bellard3a7d9292005-08-21 09:26:42 +00001926}
1927
pbrook0f459d12008-06-09 00:20:13 +00001928static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001929{
pbrook0f459d12008-06-09 00:20:13 +00001930 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
1931 tlb_entry->addr_write = vaddr;
bellard1ccde1c2004-02-06 19:46:14 +00001932}
1933
pbrook0f459d12008-06-09 00:20:13 +00001934/* update the TLB corresponding to virtual page vaddr
1935 so that it is no longer dirty */
1936static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001937{
bellard1ccde1c2004-02-06 19:46:14 +00001938 int i;
1939
pbrook0f459d12008-06-09 00:20:13 +00001940 vaddr &= TARGET_PAGE_MASK;
bellard1ccde1c2004-02-06 19:46:14 +00001941 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
pbrook0f459d12008-06-09 00:20:13 +00001942 tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
1943 tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001944#if (NB_MMU_MODES >= 3)
pbrook0f459d12008-06-09 00:20:13 +00001945 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001946#if (NB_MMU_MODES == 4)
pbrook0f459d12008-06-09 00:20:13 +00001947 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001948#endif
1949#endif
bellard9fa3e852004-01-04 18:06:42 +00001950}
1951
bellard59817cc2004-02-16 22:01:13 +00001952/* add a new TLB entry. At most one entry for a given virtual address
1953 is permitted. Return 0 if OK or 2 if the page could not be mapped
1954 (can only happen in non SOFTMMU mode for I/O pages or pages
1955 conflicting with the host address space). */
ths5fafdf22007-09-16 21:08:06 +00001956int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1957 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00001958 int mmu_idx, int is_softmmu)
bellard9fa3e852004-01-04 18:06:42 +00001959{
bellard92e873b2004-05-21 14:52:29 +00001960 PhysPageDesc *p;
bellard4f2ac232004-04-26 19:44:02 +00001961 unsigned long pd;
bellard9fa3e852004-01-04 18:06:42 +00001962 unsigned int index;
bellard4f2ac232004-04-26 19:44:02 +00001963 target_ulong address;
pbrook0f459d12008-06-09 00:20:13 +00001964 target_ulong code_address;
bellard108c49b2005-07-24 12:55:09 +00001965 target_phys_addr_t addend;
bellard9fa3e852004-01-04 18:06:42 +00001966 int ret;
bellard84b7b8e2005-11-28 21:19:04 +00001967 CPUTLBEntry *te;
aliguoria1d1bb32008-11-18 20:07:32 +00001968 CPUWatchpoint *wp;
pbrook0f459d12008-06-09 00:20:13 +00001969 target_phys_addr_t iotlb;
bellard9fa3e852004-01-04 18:06:42 +00001970
bellard92e873b2004-05-21 14:52:29 +00001971 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001972 if (!p) {
1973 pd = IO_MEM_UNASSIGNED;
bellard9fa3e852004-01-04 18:06:42 +00001974 } else {
1975 pd = p->phys_offset;
bellard9fa3e852004-01-04 18:06:42 +00001976 }
1977#if defined(DEBUG_TLB)
j_mayer6ebbf392007-10-14 07:07:08 +00001978 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1979 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
bellard9fa3e852004-01-04 18:06:42 +00001980#endif
1981
1982 ret = 0;
pbrook0f459d12008-06-09 00:20:13 +00001983 address = vaddr;
1984 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1985 /* IO memory case (romd handled later) */
1986 address |= TLB_MMIO;
1987 }
1988 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1989 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
1990 /* Normal RAM. */
1991 iotlb = pd & TARGET_PAGE_MASK;
1992 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
1993 iotlb |= IO_MEM_NOTDIRTY;
1994 else
1995 iotlb |= IO_MEM_ROM;
1996 } else {
1997 /* IO handlers are currently passed a phsical address.
1998 It would be nice to pass an offset from the base address
1999 of that region. This would avoid having to special case RAM,
2000 and avoid full address decoding in every device.
2001 We can't use the high bits of pd for this because
2002 IO_MEM_ROMD uses these as a ram address. */
pbrook8da3ff12008-12-01 18:59:50 +00002003 iotlb = (pd & ~TARGET_PAGE_MASK);
2004 if (p) {
pbrook8da3ff12008-12-01 18:59:50 +00002005 iotlb += p->region_offset;
2006 } else {
2007 iotlb += paddr;
2008 }
pbrook0f459d12008-06-09 00:20:13 +00002009 }
pbrook6658ffb2007-03-16 23:58:11 +00002010
pbrook0f459d12008-06-09 00:20:13 +00002011 code_address = address;
2012 /* Make accesses to pages with watchpoints go via the
2013 watchpoint trap routines. */
aliguoric0ce9982008-11-25 22:13:57 +00002014 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00002015 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
pbrook0f459d12008-06-09 00:20:13 +00002016 iotlb = io_mem_watch + paddr;
2017 /* TODO: The memory case can be optimized by not trapping
2018 reads of pages with a write breakpoint. */
2019 address |= TLB_MMIO;
pbrook6658ffb2007-03-16 23:58:11 +00002020 }
pbrook0f459d12008-06-09 00:20:13 +00002021 }
balrogd79acba2007-06-26 20:01:13 +00002022
pbrook0f459d12008-06-09 00:20:13 +00002023 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2024 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2025 te = &env->tlb_table[mmu_idx][index];
2026 te->addend = addend - vaddr;
2027 if (prot & PAGE_READ) {
2028 te->addr_read = address;
2029 } else {
2030 te->addr_read = -1;
2031 }
edgar_igl5c751e92008-05-06 08:44:21 +00002032
pbrook0f459d12008-06-09 00:20:13 +00002033 if (prot & PAGE_EXEC) {
2034 te->addr_code = code_address;
2035 } else {
2036 te->addr_code = -1;
2037 }
2038 if (prot & PAGE_WRITE) {
2039 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2040 (pd & IO_MEM_ROMD)) {
2041 /* Write access calls the I/O callback. */
2042 te->addr_write = address | TLB_MMIO;
2043 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2044 !cpu_physical_memory_is_dirty(pd)) {
2045 te->addr_write = address | TLB_NOTDIRTY;
bellard84b7b8e2005-11-28 21:19:04 +00002046 } else {
pbrook0f459d12008-06-09 00:20:13 +00002047 te->addr_write = address;
bellard9fa3e852004-01-04 18:06:42 +00002048 }
pbrook0f459d12008-06-09 00:20:13 +00002049 } else {
2050 te->addr_write = -1;
bellard9fa3e852004-01-04 18:06:42 +00002051 }
bellard9fa3e852004-01-04 18:06:42 +00002052 return ret;
2053}
2054
bellard01243112004-01-04 15:48:17 +00002055#else
2056
bellardee8b7022004-02-03 23:35:10 +00002057void tlb_flush(CPUState *env, int flush_global)
bellard01243112004-01-04 15:48:17 +00002058{
2059}
2060
bellard2e126692004-04-25 21:28:44 +00002061void tlb_flush_page(CPUState *env, target_ulong addr)
bellard01243112004-01-04 15:48:17 +00002062{
2063}
2064
ths5fafdf22007-09-16 21:08:06 +00002065int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2066 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00002067 int mmu_idx, int is_softmmu)
bellard33417e72003-08-10 21:47:01 +00002068{
bellard9fa3e852004-01-04 18:06:42 +00002069 return 0;
2070}
bellard33417e72003-08-10 21:47:01 +00002071
bellard9fa3e852004-01-04 18:06:42 +00002072/* dump memory mappings */
2073void page_dump(FILE *f)
2074{
2075 unsigned long start, end;
2076 int i, j, prot, prot1;
2077 PageDesc *p;
2078
2079 fprintf(f, "%-8s %-8s %-8s %s\n",
2080 "start", "end", "size", "prot");
2081 start = -1;
2082 end = -1;
2083 prot = 0;
2084 for(i = 0; i <= L1_SIZE; i++) {
2085 if (i < L1_SIZE)
2086 p = l1_map[i];
2087 else
2088 p = NULL;
2089 for(j = 0;j < L2_SIZE; j++) {
2090 if (!p)
2091 prot1 = 0;
2092 else
2093 prot1 = p[j].flags;
2094 if (prot1 != prot) {
2095 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2096 if (start != -1) {
2097 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
ths5fafdf22007-09-16 21:08:06 +00002098 start, end, end - start,
bellard9fa3e852004-01-04 18:06:42 +00002099 prot & PAGE_READ ? 'r' : '-',
2100 prot & PAGE_WRITE ? 'w' : '-',
2101 prot & PAGE_EXEC ? 'x' : '-');
2102 }
2103 if (prot1 != 0)
2104 start = end;
2105 else
2106 start = -1;
2107 prot = prot1;
2108 }
2109 if (!p)
2110 break;
2111 }
bellard33417e72003-08-10 21:47:01 +00002112 }
bellard33417e72003-08-10 21:47:01 +00002113}
2114
pbrook53a59602006-03-25 19:31:22 +00002115int page_get_flags(target_ulong address)
bellard33417e72003-08-10 21:47:01 +00002116{
bellard9fa3e852004-01-04 18:06:42 +00002117 PageDesc *p;
2118
2119 p = page_find(address >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002120 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00002121 return 0;
2122 return p->flags;
bellard33417e72003-08-10 21:47:01 +00002123}
2124
bellard9fa3e852004-01-04 18:06:42 +00002125/* modify the flags of a page and invalidate the code if
2126 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2127 depending on PAGE_WRITE */
pbrook53a59602006-03-25 19:31:22 +00002128void page_set_flags(target_ulong start, target_ulong end, int flags)
bellard9fa3e852004-01-04 18:06:42 +00002129{
2130 PageDesc *p;
pbrook53a59602006-03-25 19:31:22 +00002131 target_ulong addr;
bellard9fa3e852004-01-04 18:06:42 +00002132
pbrookc8a706f2008-06-02 16:16:42 +00002133 /* mmap_lock should already be held. */
bellard9fa3e852004-01-04 18:06:42 +00002134 start = start & TARGET_PAGE_MASK;
2135 end = TARGET_PAGE_ALIGN(end);
2136 if (flags & PAGE_WRITE)
2137 flags |= PAGE_WRITE_ORG;
bellard9fa3e852004-01-04 18:06:42 +00002138 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2139 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
pbrook17e23772008-06-09 13:47:45 +00002140 /* We may be called for host regions that are outside guest
2141 address space. */
2142 if (!p)
2143 return;
bellard9fa3e852004-01-04 18:06:42 +00002144 /* if the write protection is set, then we invalidate the code
2145 inside */
ths5fafdf22007-09-16 21:08:06 +00002146 if (!(p->flags & PAGE_WRITE) &&
bellard9fa3e852004-01-04 18:06:42 +00002147 (flags & PAGE_WRITE) &&
2148 p->first_tb) {
bellardd720b932004-04-25 17:57:43 +00002149 tb_invalidate_phys_page(addr, 0, NULL);
bellard9fa3e852004-01-04 18:06:42 +00002150 }
2151 p->flags = flags;
2152 }
bellard9fa3e852004-01-04 18:06:42 +00002153}
2154
ths3d97b402007-11-02 19:02:07 +00002155int page_check_range(target_ulong start, target_ulong len, int flags)
2156{
2157 PageDesc *p;
2158 target_ulong end;
2159 target_ulong addr;
2160
balrog55f280c2008-10-28 10:24:11 +00002161 if (start + len < start)
2162 /* we've wrapped around */
2163 return -1;
2164
ths3d97b402007-11-02 19:02:07 +00002165 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2166 start = start & TARGET_PAGE_MASK;
2167
ths3d97b402007-11-02 19:02:07 +00002168 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2169 p = page_find(addr >> TARGET_PAGE_BITS);
2170 if( !p )
2171 return -1;
2172 if( !(p->flags & PAGE_VALID) )
2173 return -1;
2174
bellarddae32702007-11-14 10:51:00 +00002175 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
ths3d97b402007-11-02 19:02:07 +00002176 return -1;
bellarddae32702007-11-14 10:51:00 +00002177 if (flags & PAGE_WRITE) {
2178 if (!(p->flags & PAGE_WRITE_ORG))
2179 return -1;
2180 /* unprotect the page if it was put read-only because it
2181 contains translated code */
2182 if (!(p->flags & PAGE_WRITE)) {
2183 if (!page_unprotect(addr, 0, NULL))
2184 return -1;
2185 }
2186 return 0;
2187 }
ths3d97b402007-11-02 19:02:07 +00002188 }
2189 return 0;
2190}
2191
bellard9fa3e852004-01-04 18:06:42 +00002192/* called from signal handler: invalidate the code and unprotect the
2193 page. Return TRUE if the fault was succesfully handled. */
pbrook53a59602006-03-25 19:31:22 +00002194int page_unprotect(target_ulong address, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00002195{
2196 unsigned int page_index, prot, pindex;
2197 PageDesc *p, *p1;
pbrook53a59602006-03-25 19:31:22 +00002198 target_ulong host_start, host_end, addr;
bellard9fa3e852004-01-04 18:06:42 +00002199
pbrookc8a706f2008-06-02 16:16:42 +00002200 /* Technically this isn't safe inside a signal handler. However we
2201 know this only ever happens in a synchronous SEGV handler, so in
2202 practice it seems to be ok. */
2203 mmap_lock();
2204
bellard83fb7ad2004-07-05 21:25:26 +00002205 host_start = address & qemu_host_page_mask;
bellard9fa3e852004-01-04 18:06:42 +00002206 page_index = host_start >> TARGET_PAGE_BITS;
2207 p1 = page_find(page_index);
pbrookc8a706f2008-06-02 16:16:42 +00002208 if (!p1) {
2209 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002210 return 0;
pbrookc8a706f2008-06-02 16:16:42 +00002211 }
bellard83fb7ad2004-07-05 21:25:26 +00002212 host_end = host_start + qemu_host_page_size;
bellard9fa3e852004-01-04 18:06:42 +00002213 p = p1;
2214 prot = 0;
2215 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2216 prot |= p->flags;
2217 p++;
2218 }
2219 /* if the page was really writable, then we change its
2220 protection back to writable */
2221 if (prot & PAGE_WRITE_ORG) {
2222 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2223 if (!(p1[pindex].flags & PAGE_WRITE)) {
ths5fafdf22007-09-16 21:08:06 +00002224 mprotect((void *)g2h(host_start), qemu_host_page_size,
bellard9fa3e852004-01-04 18:06:42 +00002225 (prot & PAGE_BITS) | PAGE_WRITE);
2226 p1[pindex].flags |= PAGE_WRITE;
2227 /* and since the content will be modified, we must invalidate
2228 the corresponding translated code. */
bellardd720b932004-04-25 17:57:43 +00002229 tb_invalidate_phys_page(address, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00002230#ifdef DEBUG_TB_CHECK
2231 tb_invalidate_check(address);
2232#endif
pbrookc8a706f2008-06-02 16:16:42 +00002233 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002234 return 1;
2235 }
2236 }
pbrookc8a706f2008-06-02 16:16:42 +00002237 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002238 return 0;
2239}
2240
bellard6a00d602005-11-21 23:25:50 +00002241static inline void tlb_set_dirty(CPUState *env,
2242 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002243{
2244}
bellard9fa3e852004-01-04 18:06:42 +00002245#endif /* defined(CONFIG_USER_ONLY) */
2246
pbrooke2eef172008-06-08 01:09:01 +00002247#if !defined(CONFIG_USER_ONLY)
pbrook8da3ff12008-12-01 18:59:50 +00002248
blueswir1db7b5422007-05-26 17:36:03 +00002249static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
pbrook8da3ff12008-12-01 18:59:50 +00002250 ram_addr_t memory, ram_addr_t region_offset);
aurel3200f82b82008-04-27 21:12:55 +00002251static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
pbrook8da3ff12008-12-01 18:59:50 +00002252 ram_addr_t orig_memory, ram_addr_t region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002253#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2254 need_subpage) \
2255 do { \
2256 if (addr > start_addr) \
2257 start_addr2 = 0; \
2258 else { \
2259 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2260 if (start_addr2 > 0) \
2261 need_subpage = 1; \
2262 } \
2263 \
blueswir149e9fba2007-05-30 17:25:06 +00002264 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
blueswir1db7b5422007-05-26 17:36:03 +00002265 end_addr2 = TARGET_PAGE_SIZE - 1; \
2266 else { \
2267 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2268 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2269 need_subpage = 1; \
2270 } \
2271 } while (0)
2272
bellard33417e72003-08-10 21:47:01 +00002273/* register physical memory. 'size' must be a multiple of the target
2274 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
pbrook8da3ff12008-12-01 18:59:50 +00002275 io memory page. The address used when calling the IO function is
2276 the offset from the start of the region, plus region_offset. Both
2277 start_region and regon_offset are rounded down to a page boundary
2278 before calculating this offset. This should not be a problem unless
2279 the low bits of start_addr and region_offset differ. */
2280void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
2281 ram_addr_t size,
2282 ram_addr_t phys_offset,
2283 ram_addr_t region_offset)
bellard33417e72003-08-10 21:47:01 +00002284{
bellard108c49b2005-07-24 12:55:09 +00002285 target_phys_addr_t addr, end_addr;
bellard92e873b2004-05-21 14:52:29 +00002286 PhysPageDesc *p;
bellard9d420372006-06-25 22:25:22 +00002287 CPUState *env;
aurel3200f82b82008-04-27 21:12:55 +00002288 ram_addr_t orig_size = size;
blueswir1db7b5422007-05-26 17:36:03 +00002289 void *subpage;
bellard33417e72003-08-10 21:47:01 +00002290
bellardda260242008-05-30 20:48:25 +00002291#ifdef USE_KQEMU
2292 /* XXX: should not depend on cpu context */
2293 env = first_cpu;
2294 if (env->kqemu_enabled) {
2295 kqemu_set_phys_mem(start_addr, size, phys_offset);
2296 }
2297#endif
aliguori7ba1e612008-11-05 16:04:33 +00002298 if (kvm_enabled())
2299 kvm_set_phys_mem(start_addr, size, phys_offset);
2300
pbrook67c4d232009-02-23 13:16:07 +00002301 if (phys_offset == IO_MEM_UNASSIGNED) {
2302 region_offset = start_addr;
2303 }
pbrook8da3ff12008-12-01 18:59:50 +00002304 region_offset &= TARGET_PAGE_MASK;
bellard5fd386f2004-05-23 21:11:22 +00002305 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
blueswir149e9fba2007-05-30 17:25:06 +00002306 end_addr = start_addr + (target_phys_addr_t)size;
2307 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
blueswir1db7b5422007-05-26 17:36:03 +00002308 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2309 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
aurel3200f82b82008-04-27 21:12:55 +00002310 ram_addr_t orig_memory = p->phys_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002311 target_phys_addr_t start_addr2, end_addr2;
2312 int need_subpage = 0;
2313
2314 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2315 need_subpage);
blueswir14254fab2008-01-01 16:57:19 +00002316 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002317 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2318 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002319 &p->phys_offset, orig_memory,
2320 p->region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002321 } else {
2322 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2323 >> IO_MEM_SHIFT];
2324 }
pbrook8da3ff12008-12-01 18:59:50 +00002325 subpage_register(subpage, start_addr2, end_addr2, phys_offset,
2326 region_offset);
2327 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002328 } else {
2329 p->phys_offset = phys_offset;
2330 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2331 (phys_offset & IO_MEM_ROMD))
2332 phys_offset += TARGET_PAGE_SIZE;
2333 }
2334 } else {
2335 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2336 p->phys_offset = phys_offset;
pbrook8da3ff12008-12-01 18:59:50 +00002337 p->region_offset = region_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002338 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
pbrook8da3ff12008-12-01 18:59:50 +00002339 (phys_offset & IO_MEM_ROMD)) {
blueswir1db7b5422007-05-26 17:36:03 +00002340 phys_offset += TARGET_PAGE_SIZE;
pbrook0e8f0962008-12-02 09:02:15 +00002341 } else {
blueswir1db7b5422007-05-26 17:36:03 +00002342 target_phys_addr_t start_addr2, end_addr2;
2343 int need_subpage = 0;
2344
2345 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2346 end_addr2, need_subpage);
2347
blueswir14254fab2008-01-01 16:57:19 +00002348 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002349 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002350 &p->phys_offset, IO_MEM_UNASSIGNED,
pbrook67c4d232009-02-23 13:16:07 +00002351 addr & TARGET_PAGE_MASK);
blueswir1db7b5422007-05-26 17:36:03 +00002352 subpage_register(subpage, start_addr2, end_addr2,
pbrook8da3ff12008-12-01 18:59:50 +00002353 phys_offset, region_offset);
2354 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002355 }
2356 }
2357 }
pbrook8da3ff12008-12-01 18:59:50 +00002358 region_offset += TARGET_PAGE_SIZE;
bellard33417e72003-08-10 21:47:01 +00002359 }
ths3b46e622007-09-17 08:09:54 +00002360
bellard9d420372006-06-25 22:25:22 +00002361 /* since each CPU stores ram addresses in its TLB cache, we must
2362 reset the modified entries */
2363 /* XXX: slow ! */
2364 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2365 tlb_flush(env, 1);
2366 }
bellard33417e72003-08-10 21:47:01 +00002367}
2368
bellardba863452006-09-24 18:41:10 +00002369/* XXX: temporary until new memory mapping API */
aurel3200f82b82008-04-27 21:12:55 +00002370ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
bellardba863452006-09-24 18:41:10 +00002371{
2372 PhysPageDesc *p;
2373
2374 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2375 if (!p)
2376 return IO_MEM_UNASSIGNED;
2377 return p->phys_offset;
2378}
2379
aliguorif65ed4c2008-12-09 20:09:57 +00002380void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2381{
2382 if (kvm_enabled())
2383 kvm_coalesce_mmio_region(addr, size);
2384}
2385
2386void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2387{
2388 if (kvm_enabled())
2389 kvm_uncoalesce_mmio_region(addr, size);
2390}
2391
bellarde9a1ab12007-02-08 23:08:38 +00002392/* XXX: better than nothing */
aurel3200f82b82008-04-27 21:12:55 +00002393ram_addr_t qemu_ram_alloc(ram_addr_t size)
bellarde9a1ab12007-02-08 23:08:38 +00002394{
2395 ram_addr_t addr;
balrog7fb4fdc2008-04-24 17:59:27 +00002396 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
ths012a7042008-10-02 17:34:21 +00002397 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
bellarded441462008-05-23 11:56:45 +00002398 (uint64_t)size, (uint64_t)phys_ram_size);
bellarde9a1ab12007-02-08 23:08:38 +00002399 abort();
2400 }
2401 addr = phys_ram_alloc_offset;
2402 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2403 return addr;
2404}
2405
2406void qemu_ram_free(ram_addr_t addr)
2407{
2408}
2409
bellarda4193c82004-06-03 14:01:43 +00002410static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
bellard33417e72003-08-10 21:47:01 +00002411{
pbrook67d3b952006-12-18 05:03:52 +00002412#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002413 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
pbrook67d3b952006-12-18 05:03:52 +00002414#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002415#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002416 do_unassigned_access(addr, 0, 0, 0, 1);
2417#endif
2418 return 0;
2419}
2420
2421static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2422{
2423#ifdef DEBUG_UNASSIGNED
2424 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2425#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002426#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002427 do_unassigned_access(addr, 0, 0, 0, 2);
2428#endif
2429 return 0;
2430}
2431
2432static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2433{
2434#ifdef DEBUG_UNASSIGNED
2435 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2436#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002437#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002438 do_unassigned_access(addr, 0, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002439#endif
bellard33417e72003-08-10 21:47:01 +00002440 return 0;
2441}
2442
bellarda4193c82004-06-03 14:01:43 +00002443static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard33417e72003-08-10 21:47:01 +00002444{
pbrook67d3b952006-12-18 05:03:52 +00002445#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002446 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
pbrook67d3b952006-12-18 05:03:52 +00002447#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002448#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002449 do_unassigned_access(addr, 1, 0, 0, 1);
2450#endif
2451}
2452
2453static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2454{
2455#ifdef DEBUG_UNASSIGNED
2456 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2457#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002458#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002459 do_unassigned_access(addr, 1, 0, 0, 2);
2460#endif
2461}
2462
2463static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2464{
2465#ifdef DEBUG_UNASSIGNED
2466 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2467#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002468#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002469 do_unassigned_access(addr, 1, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002470#endif
bellard33417e72003-08-10 21:47:01 +00002471}
2472
2473static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2474 unassigned_mem_readb,
blueswir1e18231a2008-10-06 18:46:28 +00002475 unassigned_mem_readw,
2476 unassigned_mem_readl,
bellard33417e72003-08-10 21:47:01 +00002477};
2478
2479static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2480 unassigned_mem_writeb,
blueswir1e18231a2008-10-06 18:46:28 +00002481 unassigned_mem_writew,
2482 unassigned_mem_writel,
bellard33417e72003-08-10 21:47:01 +00002483};
2484
pbrook0f459d12008-06-09 00:20:13 +00002485static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2486 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002487{
bellard3a7d9292005-08-21 09:26:42 +00002488 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002489 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2490 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2491#if !defined(CONFIG_USER_ONLY)
2492 tb_invalidate_phys_page_fast(ram_addr, 1);
2493 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2494#endif
2495 }
pbrook0f459d12008-06-09 00:20:13 +00002496 stb_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002497#ifdef USE_KQEMU
2498 if (cpu_single_env->kqemu_enabled &&
2499 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2500 kqemu_modify_page(cpu_single_env, ram_addr);
2501#endif
bellardf23db162005-08-21 19:12:28 +00002502 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2503 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2504 /* we remove the notdirty callback only if the code has been
2505 flushed */
2506 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002507 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002508}
2509
pbrook0f459d12008-06-09 00:20:13 +00002510static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2511 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002512{
bellard3a7d9292005-08-21 09:26:42 +00002513 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002514 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2515 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2516#if !defined(CONFIG_USER_ONLY)
2517 tb_invalidate_phys_page_fast(ram_addr, 2);
2518 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2519#endif
2520 }
pbrook0f459d12008-06-09 00:20:13 +00002521 stw_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002522#ifdef USE_KQEMU
2523 if (cpu_single_env->kqemu_enabled &&
2524 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2525 kqemu_modify_page(cpu_single_env, ram_addr);
2526#endif
bellardf23db162005-08-21 19:12:28 +00002527 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2528 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2529 /* we remove the notdirty callback only if the code has been
2530 flushed */
2531 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002532 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002533}
2534
pbrook0f459d12008-06-09 00:20:13 +00002535static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2536 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002537{
bellard3a7d9292005-08-21 09:26:42 +00002538 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002539 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2540 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2541#if !defined(CONFIG_USER_ONLY)
2542 tb_invalidate_phys_page_fast(ram_addr, 4);
2543 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2544#endif
2545 }
pbrook0f459d12008-06-09 00:20:13 +00002546 stl_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002547#ifdef USE_KQEMU
2548 if (cpu_single_env->kqemu_enabled &&
2549 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2550 kqemu_modify_page(cpu_single_env, ram_addr);
2551#endif
bellardf23db162005-08-21 19:12:28 +00002552 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2553 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2554 /* we remove the notdirty callback only if the code has been
2555 flushed */
2556 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002557 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002558}
2559
bellard3a7d9292005-08-21 09:26:42 +00002560static CPUReadMemoryFunc *error_mem_read[3] = {
2561 NULL, /* never used */
2562 NULL, /* never used */
2563 NULL, /* never used */
2564};
2565
bellard1ccde1c2004-02-06 19:46:14 +00002566static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2567 notdirty_mem_writeb,
2568 notdirty_mem_writew,
2569 notdirty_mem_writel,
2570};
2571
pbrook0f459d12008-06-09 00:20:13 +00002572/* Generate a debug exception if a watchpoint has been hit. */
aliguorib4051332008-11-18 20:14:20 +00002573static void check_watchpoint(int offset, int len_mask, int flags)
pbrook0f459d12008-06-09 00:20:13 +00002574{
2575 CPUState *env = cpu_single_env;
aliguori06d55cc2008-11-18 20:24:06 +00002576 target_ulong pc, cs_base;
2577 TranslationBlock *tb;
pbrook0f459d12008-06-09 00:20:13 +00002578 target_ulong vaddr;
aliguoria1d1bb32008-11-18 20:07:32 +00002579 CPUWatchpoint *wp;
aliguori06d55cc2008-11-18 20:24:06 +00002580 int cpu_flags;
pbrook0f459d12008-06-09 00:20:13 +00002581
aliguori06d55cc2008-11-18 20:24:06 +00002582 if (env->watchpoint_hit) {
2583 /* We re-entered the check after replacing the TB. Now raise
2584 * the debug interrupt so that is will trigger after the
2585 * current instruction. */
2586 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2587 return;
2588 }
pbrook2e70f6e2008-06-29 01:03:05 +00002589 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
aliguoric0ce9982008-11-25 22:13:57 +00002590 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00002591 if ((vaddr == (wp->vaddr & len_mask) ||
2592 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
aliguori6e140f22008-11-18 20:37:55 +00002593 wp->flags |= BP_WATCHPOINT_HIT;
2594 if (!env->watchpoint_hit) {
2595 env->watchpoint_hit = wp;
2596 tb = tb_find_pc(env->mem_io_pc);
2597 if (!tb) {
2598 cpu_abort(env, "check_watchpoint: could not find TB for "
2599 "pc=%p", (void *)env->mem_io_pc);
2600 }
2601 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
2602 tb_phys_invalidate(tb, -1);
2603 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2604 env->exception_index = EXCP_DEBUG;
2605 } else {
2606 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2607 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
2608 }
2609 cpu_resume_from_signal(env, NULL);
aliguori06d55cc2008-11-18 20:24:06 +00002610 }
aliguori6e140f22008-11-18 20:37:55 +00002611 } else {
2612 wp->flags &= ~BP_WATCHPOINT_HIT;
pbrook0f459d12008-06-09 00:20:13 +00002613 }
2614 }
2615}
2616
pbrook6658ffb2007-03-16 23:58:11 +00002617/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2618 so these check for a hit then pass through to the normal out-of-line
2619 phys routines. */
2620static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2621{
aliguorib4051332008-11-18 20:14:20 +00002622 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002623 return ldub_phys(addr);
2624}
2625
2626static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2627{
aliguorib4051332008-11-18 20:14:20 +00002628 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002629 return lduw_phys(addr);
2630}
2631
2632static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2633{
aliguorib4051332008-11-18 20:14:20 +00002634 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002635 return ldl_phys(addr);
2636}
2637
pbrook6658ffb2007-03-16 23:58:11 +00002638static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2639 uint32_t val)
2640{
aliguorib4051332008-11-18 20:14:20 +00002641 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002642 stb_phys(addr, val);
2643}
2644
2645static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2646 uint32_t val)
2647{
aliguorib4051332008-11-18 20:14:20 +00002648 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002649 stw_phys(addr, val);
2650}
2651
2652static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2653 uint32_t val)
2654{
aliguorib4051332008-11-18 20:14:20 +00002655 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002656 stl_phys(addr, val);
2657}
2658
2659static CPUReadMemoryFunc *watch_mem_read[3] = {
2660 watch_mem_readb,
2661 watch_mem_readw,
2662 watch_mem_readl,
2663};
2664
2665static CPUWriteMemoryFunc *watch_mem_write[3] = {
2666 watch_mem_writeb,
2667 watch_mem_writew,
2668 watch_mem_writel,
2669};
pbrook6658ffb2007-03-16 23:58:11 +00002670
blueswir1db7b5422007-05-26 17:36:03 +00002671static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2672 unsigned int len)
2673{
blueswir1db7b5422007-05-26 17:36:03 +00002674 uint32_t ret;
2675 unsigned int idx;
2676
pbrook8da3ff12008-12-01 18:59:50 +00002677 idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00002678#if defined(DEBUG_SUBPAGE)
2679 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2680 mmio, len, addr, idx);
2681#endif
pbrook8da3ff12008-12-01 18:59:50 +00002682 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
2683 addr + mmio->region_offset[idx][0][len]);
blueswir1db7b5422007-05-26 17:36:03 +00002684
2685 return ret;
2686}
2687
2688static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2689 uint32_t value, unsigned int len)
2690{
blueswir1db7b5422007-05-26 17:36:03 +00002691 unsigned int idx;
2692
pbrook8da3ff12008-12-01 18:59:50 +00002693 idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00002694#if defined(DEBUG_SUBPAGE)
2695 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2696 mmio, len, addr, idx, value);
2697#endif
pbrook8da3ff12008-12-01 18:59:50 +00002698 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
2699 addr + mmio->region_offset[idx][1][len],
2700 value);
blueswir1db7b5422007-05-26 17:36:03 +00002701}
2702
2703static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2704{
2705#if defined(DEBUG_SUBPAGE)
2706 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2707#endif
2708
2709 return subpage_readlen(opaque, addr, 0);
2710}
2711
2712static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2713 uint32_t value)
2714{
2715#if defined(DEBUG_SUBPAGE)
2716 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2717#endif
2718 subpage_writelen(opaque, addr, value, 0);
2719}
2720
2721static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2722{
2723#if defined(DEBUG_SUBPAGE)
2724 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2725#endif
2726
2727 return subpage_readlen(opaque, addr, 1);
2728}
2729
2730static void subpage_writew (void *opaque, target_phys_addr_t addr,
2731 uint32_t value)
2732{
2733#if defined(DEBUG_SUBPAGE)
2734 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2735#endif
2736 subpage_writelen(opaque, addr, value, 1);
2737}
2738
2739static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2740{
2741#if defined(DEBUG_SUBPAGE)
2742 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2743#endif
2744
2745 return subpage_readlen(opaque, addr, 2);
2746}
2747
2748static void subpage_writel (void *opaque,
2749 target_phys_addr_t addr, uint32_t value)
2750{
2751#if defined(DEBUG_SUBPAGE)
2752 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2753#endif
2754 subpage_writelen(opaque, addr, value, 2);
2755}
2756
2757static CPUReadMemoryFunc *subpage_read[] = {
2758 &subpage_readb,
2759 &subpage_readw,
2760 &subpage_readl,
2761};
2762
2763static CPUWriteMemoryFunc *subpage_write[] = {
2764 &subpage_writeb,
2765 &subpage_writew,
2766 &subpage_writel,
2767};
2768
2769static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
pbrook8da3ff12008-12-01 18:59:50 +00002770 ram_addr_t memory, ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00002771{
2772 int idx, eidx;
blueswir14254fab2008-01-01 16:57:19 +00002773 unsigned int i;
blueswir1db7b5422007-05-26 17:36:03 +00002774
2775 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2776 return -1;
2777 idx = SUBPAGE_IDX(start);
2778 eidx = SUBPAGE_IDX(end);
2779#if defined(DEBUG_SUBPAGE)
2780 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2781 mmio, start, end, idx, eidx, memory);
2782#endif
2783 memory >>= IO_MEM_SHIFT;
2784 for (; idx <= eidx; idx++) {
blueswir14254fab2008-01-01 16:57:19 +00002785 for (i = 0; i < 4; i++) {
blueswir13ee89922008-01-02 19:45:26 +00002786 if (io_mem_read[memory][i]) {
2787 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2788 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
pbrook8da3ff12008-12-01 18:59:50 +00002789 mmio->region_offset[idx][0][i] = region_offset;
blueswir13ee89922008-01-02 19:45:26 +00002790 }
2791 if (io_mem_write[memory][i]) {
2792 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2793 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
pbrook8da3ff12008-12-01 18:59:50 +00002794 mmio->region_offset[idx][1][i] = region_offset;
blueswir13ee89922008-01-02 19:45:26 +00002795 }
blueswir14254fab2008-01-01 16:57:19 +00002796 }
blueswir1db7b5422007-05-26 17:36:03 +00002797 }
2798
2799 return 0;
2800}
2801
aurel3200f82b82008-04-27 21:12:55 +00002802static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
pbrook8da3ff12008-12-01 18:59:50 +00002803 ram_addr_t orig_memory, ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00002804{
2805 subpage_t *mmio;
2806 int subpage_memory;
2807
2808 mmio = qemu_mallocz(sizeof(subpage_t));
aliguori1eec6142009-02-05 22:06:18 +00002809
2810 mmio->base = base;
2811 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
blueswir1db7b5422007-05-26 17:36:03 +00002812#if defined(DEBUG_SUBPAGE)
aliguori1eec6142009-02-05 22:06:18 +00002813 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2814 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
blueswir1db7b5422007-05-26 17:36:03 +00002815#endif
aliguori1eec6142009-02-05 22:06:18 +00002816 *phys = subpage_memory | IO_MEM_SUBPAGE;
2817 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
pbrook8da3ff12008-12-01 18:59:50 +00002818 region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002819
2820 return mmio;
2821}
2822
aliguori88715652009-02-11 15:20:58 +00002823static int get_free_io_mem_idx(void)
2824{
2825 int i;
2826
2827 for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
2828 if (!io_mem_used[i]) {
2829 io_mem_used[i] = 1;
2830 return i;
2831 }
2832
2833 return -1;
2834}
2835
bellard33417e72003-08-10 21:47:01 +00002836static void io_mem_init(void)
2837{
aliguori88715652009-02-11 15:20:58 +00002838 int i;
2839
bellard3a7d9292005-08-21 09:26:42 +00002840 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
bellarda4193c82004-06-03 14:01:43 +00002841 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
bellard3a7d9292005-08-21 09:26:42 +00002842 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
aliguori88715652009-02-11 15:20:58 +00002843 for (i=0; i<5; i++)
2844 io_mem_used[i] = 1;
bellard1ccde1c2004-02-06 19:46:14 +00002845
pbrook0f459d12008-06-09 00:20:13 +00002846 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
pbrook6658ffb2007-03-16 23:58:11 +00002847 watch_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002848 /* alloc dirty bits array */
bellard0a962c02005-02-10 22:00:27 +00002849 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
bellard3a7d9292005-08-21 09:26:42 +00002850 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002851}
2852
2853/* mem_read and mem_write are arrays of functions containing the
2854 function to access byte (index 0), word (index 1) and dword (index
blueswir13ee89922008-01-02 19:45:26 +00002855 2). Functions can be omitted with a NULL function pointer. The
2856 registered functions may be modified dynamically later.
2857 If io_index is non zero, the corresponding io zone is
blueswir14254fab2008-01-01 16:57:19 +00002858 modified. If it is zero, a new io zone is allocated. The return
2859 value can be used with cpu_register_physical_memory(). (-1) is
2860 returned if error. */
bellard33417e72003-08-10 21:47:01 +00002861int cpu_register_io_memory(int io_index,
2862 CPUReadMemoryFunc **mem_read,
bellarda4193c82004-06-03 14:01:43 +00002863 CPUWriteMemoryFunc **mem_write,
2864 void *opaque)
bellard33417e72003-08-10 21:47:01 +00002865{
blueswir14254fab2008-01-01 16:57:19 +00002866 int i, subwidth = 0;
bellard33417e72003-08-10 21:47:01 +00002867
2868 if (io_index <= 0) {
aliguori88715652009-02-11 15:20:58 +00002869 io_index = get_free_io_mem_idx();
2870 if (io_index == -1)
2871 return io_index;
bellard33417e72003-08-10 21:47:01 +00002872 } else {
2873 if (io_index >= IO_MEM_NB_ENTRIES)
2874 return -1;
2875 }
bellardb5ff1b32005-11-26 10:38:39 +00002876
bellard33417e72003-08-10 21:47:01 +00002877 for(i = 0;i < 3; i++) {
blueswir14254fab2008-01-01 16:57:19 +00002878 if (!mem_read[i] || !mem_write[i])
2879 subwidth = IO_MEM_SUBWIDTH;
bellard33417e72003-08-10 21:47:01 +00002880 io_mem_read[io_index][i] = mem_read[i];
2881 io_mem_write[io_index][i] = mem_write[i];
2882 }
bellarda4193c82004-06-03 14:01:43 +00002883 io_mem_opaque[io_index] = opaque;
blueswir14254fab2008-01-01 16:57:19 +00002884 return (io_index << IO_MEM_SHIFT) | subwidth;
bellard33417e72003-08-10 21:47:01 +00002885}
bellard61382a52003-10-27 21:22:23 +00002886
aliguori88715652009-02-11 15:20:58 +00002887void cpu_unregister_io_memory(int io_table_address)
2888{
2889 int i;
2890 int io_index = io_table_address >> IO_MEM_SHIFT;
2891
2892 for (i=0;i < 3; i++) {
2893 io_mem_read[io_index][i] = unassigned_mem_read[i];
2894 io_mem_write[io_index][i] = unassigned_mem_write[i];
2895 }
2896 io_mem_opaque[io_index] = NULL;
2897 io_mem_used[io_index] = 0;
2898}
2899
bellard8926b512004-10-10 15:14:20 +00002900CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2901{
2902 return io_mem_write[io_index >> IO_MEM_SHIFT];
2903}
2904
2905CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2906{
2907 return io_mem_read[io_index >> IO_MEM_SHIFT];
2908}
2909
pbrooke2eef172008-06-08 01:09:01 +00002910#endif /* !defined(CONFIG_USER_ONLY) */
2911
bellard13eb76e2004-01-24 15:23:36 +00002912/* physical memory access (slow version, mainly for debug) */
2913#if defined(CONFIG_USER_ONLY)
ths5fafdf22007-09-16 21:08:06 +00002914void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002915 int len, int is_write)
2916{
2917 int l, flags;
2918 target_ulong page;
pbrook53a59602006-03-25 19:31:22 +00002919 void * p;
bellard13eb76e2004-01-24 15:23:36 +00002920
2921 while (len > 0) {
2922 page = addr & TARGET_PAGE_MASK;
2923 l = (page + TARGET_PAGE_SIZE) - addr;
2924 if (l > len)
2925 l = len;
2926 flags = page_get_flags(page);
2927 if (!(flags & PAGE_VALID))
2928 return;
2929 if (is_write) {
2930 if (!(flags & PAGE_WRITE))
2931 return;
bellard579a97f2007-11-11 14:26:47 +00002932 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002933 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
bellard579a97f2007-11-11 14:26:47 +00002934 /* FIXME - should this return an error rather than just fail? */
2935 return;
aurel3272fb7da2008-04-27 23:53:45 +00002936 memcpy(p, buf, l);
2937 unlock_user(p, addr, l);
bellard13eb76e2004-01-24 15:23:36 +00002938 } else {
2939 if (!(flags & PAGE_READ))
2940 return;
bellard579a97f2007-11-11 14:26:47 +00002941 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002942 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
bellard579a97f2007-11-11 14:26:47 +00002943 /* FIXME - should this return an error rather than just fail? */
2944 return;
aurel3272fb7da2008-04-27 23:53:45 +00002945 memcpy(buf, p, l);
aurel325b257572008-04-28 08:54:59 +00002946 unlock_user(p, addr, 0);
bellard13eb76e2004-01-24 15:23:36 +00002947 }
2948 len -= l;
2949 buf += l;
2950 addr += l;
2951 }
2952}
bellard8df1cd02005-01-28 22:37:22 +00002953
bellard13eb76e2004-01-24 15:23:36 +00002954#else
ths5fafdf22007-09-16 21:08:06 +00002955void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002956 int len, int is_write)
2957{
2958 int l, io_index;
2959 uint8_t *ptr;
2960 uint32_t val;
bellard2e126692004-04-25 21:28:44 +00002961 target_phys_addr_t page;
2962 unsigned long pd;
bellard92e873b2004-05-21 14:52:29 +00002963 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002964
bellard13eb76e2004-01-24 15:23:36 +00002965 while (len > 0) {
2966 page = addr & TARGET_PAGE_MASK;
2967 l = (page + TARGET_PAGE_SIZE) - addr;
2968 if (l > len)
2969 l = len;
bellard92e873b2004-05-21 14:52:29 +00002970 p = phys_page_find(page >> TARGET_PAGE_BITS);
bellard13eb76e2004-01-24 15:23:36 +00002971 if (!p) {
2972 pd = IO_MEM_UNASSIGNED;
2973 } else {
2974 pd = p->phys_offset;
2975 }
ths3b46e622007-09-17 08:09:54 +00002976
bellard13eb76e2004-01-24 15:23:36 +00002977 if (is_write) {
bellard3a7d9292005-08-21 09:26:42 +00002978 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
aurel326c2934d2009-02-18 21:37:17 +00002979 target_phys_addr_t addr1 = addr;
bellard13eb76e2004-01-24 15:23:36 +00002980 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00002981 if (p)
aurel326c2934d2009-02-18 21:37:17 +00002982 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard6a00d602005-11-21 23:25:50 +00002983 /* XXX: could force cpu_single_env to NULL to avoid
2984 potential bugs */
aurel326c2934d2009-02-18 21:37:17 +00002985 if (l >= 4 && ((addr1 & 3) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002986 /* 32 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002987 val = ldl_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00002988 io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00002989 l = 4;
aurel326c2934d2009-02-18 21:37:17 +00002990 } else if (l >= 2 && ((addr1 & 1) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002991 /* 16 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002992 val = lduw_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00002993 io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00002994 l = 2;
2995 } else {
bellard1c213d12005-09-03 10:49:04 +00002996 /* 8 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002997 val = ldub_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00002998 io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00002999 l = 1;
3000 }
3001 } else {
bellardb448f2f2004-02-25 23:24:04 +00003002 unsigned long addr1;
3003 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
bellard13eb76e2004-01-24 15:23:36 +00003004 /* RAM case */
bellardb448f2f2004-02-25 23:24:04 +00003005 ptr = phys_ram_base + addr1;
bellard13eb76e2004-01-24 15:23:36 +00003006 memcpy(ptr, buf, l);
bellard3a7d9292005-08-21 09:26:42 +00003007 if (!cpu_physical_memory_is_dirty(addr1)) {
3008 /* invalidate code */
3009 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3010 /* set dirty bit */
ths5fafdf22007-09-16 21:08:06 +00003011 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
bellardf23db162005-08-21 19:12:28 +00003012 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00003013 }
bellard13eb76e2004-01-24 15:23:36 +00003014 }
3015 } else {
ths5fafdf22007-09-16 21:08:06 +00003016 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00003017 !(pd & IO_MEM_ROMD)) {
aurel326c2934d2009-02-18 21:37:17 +00003018 target_phys_addr_t addr1 = addr;
bellard13eb76e2004-01-24 15:23:36 +00003019 /* I/O case */
3020 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003021 if (p)
aurel326c2934d2009-02-18 21:37:17 +00003022 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3023 if (l >= 4 && ((addr1 & 3) == 0)) {
bellard13eb76e2004-01-24 15:23:36 +00003024 /* 32 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003025 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003026 stl_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003027 l = 4;
aurel326c2934d2009-02-18 21:37:17 +00003028 } else if (l >= 2 && ((addr1 & 1) == 0)) {
bellard13eb76e2004-01-24 15:23:36 +00003029 /* 16 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003030 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003031 stw_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003032 l = 2;
3033 } else {
bellard1c213d12005-09-03 10:49:04 +00003034 /* 8 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003035 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003036 stb_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003037 l = 1;
3038 }
3039 } else {
3040 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003041 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard13eb76e2004-01-24 15:23:36 +00003042 (addr & ~TARGET_PAGE_MASK);
3043 memcpy(buf, ptr, l);
3044 }
3045 }
3046 len -= l;
3047 buf += l;
3048 addr += l;
3049 }
3050}
bellard8df1cd02005-01-28 22:37:22 +00003051
bellardd0ecd2a2006-04-23 17:14:48 +00003052/* used for ROM loading : can write in RAM and ROM */
ths5fafdf22007-09-16 21:08:06 +00003053void cpu_physical_memory_write_rom(target_phys_addr_t addr,
bellardd0ecd2a2006-04-23 17:14:48 +00003054 const uint8_t *buf, int len)
3055{
3056 int l;
3057 uint8_t *ptr;
3058 target_phys_addr_t page;
3059 unsigned long pd;
3060 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00003061
bellardd0ecd2a2006-04-23 17:14:48 +00003062 while (len > 0) {
3063 page = addr & TARGET_PAGE_MASK;
3064 l = (page + TARGET_PAGE_SIZE) - addr;
3065 if (l > len)
3066 l = len;
3067 p = phys_page_find(page >> TARGET_PAGE_BITS);
3068 if (!p) {
3069 pd = IO_MEM_UNASSIGNED;
3070 } else {
3071 pd = p->phys_offset;
3072 }
ths3b46e622007-09-17 08:09:54 +00003073
bellardd0ecd2a2006-04-23 17:14:48 +00003074 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
bellard2a4188a2006-06-25 21:54:59 +00003075 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3076 !(pd & IO_MEM_ROMD)) {
bellardd0ecd2a2006-04-23 17:14:48 +00003077 /* do nothing */
3078 } else {
3079 unsigned long addr1;
3080 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3081 /* ROM/RAM case */
3082 ptr = phys_ram_base + addr1;
3083 memcpy(ptr, buf, l);
3084 }
3085 len -= l;
3086 buf += l;
3087 addr += l;
3088 }
3089}
3090
aliguori6d16c2f2009-01-22 16:59:11 +00003091typedef struct {
3092 void *buffer;
3093 target_phys_addr_t addr;
3094 target_phys_addr_t len;
3095} BounceBuffer;
3096
3097static BounceBuffer bounce;
3098
aliguoriba223c22009-01-22 16:59:16 +00003099typedef struct MapClient {
3100 void *opaque;
3101 void (*callback)(void *opaque);
3102 LIST_ENTRY(MapClient) link;
3103} MapClient;
3104
3105static LIST_HEAD(map_client_list, MapClient) map_client_list
3106 = LIST_HEAD_INITIALIZER(map_client_list);
3107
3108void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
3109{
3110 MapClient *client = qemu_malloc(sizeof(*client));
3111
3112 client->opaque = opaque;
3113 client->callback = callback;
3114 LIST_INSERT_HEAD(&map_client_list, client, link);
3115 return client;
3116}
3117
3118void cpu_unregister_map_client(void *_client)
3119{
3120 MapClient *client = (MapClient *)_client;
3121
3122 LIST_REMOVE(client, link);
3123}
3124
3125static void cpu_notify_map_clients(void)
3126{
3127 MapClient *client;
3128
3129 while (!LIST_EMPTY(&map_client_list)) {
3130 client = LIST_FIRST(&map_client_list);
3131 client->callback(client->opaque);
3132 LIST_REMOVE(client, link);
3133 }
3134}
3135
aliguori6d16c2f2009-01-22 16:59:11 +00003136/* Map a physical memory region into a host virtual address.
3137 * May map a subset of the requested range, given by and returned in *plen.
3138 * May return NULL if resources needed to perform the mapping are exhausted.
3139 * Use only for reads OR writes - not for read-modify-write operations.
aliguoriba223c22009-01-22 16:59:16 +00003140 * Use cpu_register_map_client() to know when retrying the map operation is
3141 * likely to succeed.
aliguori6d16c2f2009-01-22 16:59:11 +00003142 */
3143void *cpu_physical_memory_map(target_phys_addr_t addr,
3144 target_phys_addr_t *plen,
3145 int is_write)
3146{
3147 target_phys_addr_t len = *plen;
3148 target_phys_addr_t done = 0;
3149 int l;
3150 uint8_t *ret = NULL;
3151 uint8_t *ptr;
3152 target_phys_addr_t page;
3153 unsigned long pd;
3154 PhysPageDesc *p;
3155 unsigned long addr1;
3156
3157 while (len > 0) {
3158 page = addr & TARGET_PAGE_MASK;
3159 l = (page + TARGET_PAGE_SIZE) - addr;
3160 if (l > len)
3161 l = len;
3162 p = phys_page_find(page >> TARGET_PAGE_BITS);
3163 if (!p) {
3164 pd = IO_MEM_UNASSIGNED;
3165 } else {
3166 pd = p->phys_offset;
3167 }
3168
3169 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3170 if (done || bounce.buffer) {
3171 break;
3172 }
3173 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
3174 bounce.addr = addr;
3175 bounce.len = l;
3176 if (!is_write) {
3177 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3178 }
3179 ptr = bounce.buffer;
3180 } else {
3181 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3182 ptr = phys_ram_base + addr1;
3183 }
3184 if (!done) {
3185 ret = ptr;
3186 } else if (ret + done != ptr) {
3187 break;
3188 }
3189
3190 len -= l;
3191 addr += l;
3192 done += l;
3193 }
3194 *plen = done;
3195 return ret;
3196}
3197
3198/* Unmaps a memory region previously mapped by cpu_physical_memory_map().
3199 * Will also mark the memory as dirty if is_write == 1. access_len gives
3200 * the amount of memory that was actually read or written by the caller.
3201 */
3202void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
3203 int is_write, target_phys_addr_t access_len)
3204{
3205 if (buffer != bounce.buffer) {
3206 if (is_write) {
3207 unsigned long addr1 = (uint8_t *)buffer - phys_ram_base;
3208 while (access_len) {
3209 unsigned l;
3210 l = TARGET_PAGE_SIZE;
3211 if (l > access_len)
3212 l = access_len;
3213 if (!cpu_physical_memory_is_dirty(addr1)) {
3214 /* invalidate code */
3215 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3216 /* set dirty bit */
3217 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3218 (0xff & ~CODE_DIRTY_FLAG);
3219 }
3220 addr1 += l;
3221 access_len -= l;
3222 }
3223 }
3224 return;
3225 }
3226 if (is_write) {
3227 cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3228 }
3229 qemu_free(bounce.buffer);
3230 bounce.buffer = NULL;
aliguoriba223c22009-01-22 16:59:16 +00003231 cpu_notify_map_clients();
aliguori6d16c2f2009-01-22 16:59:11 +00003232}
bellardd0ecd2a2006-04-23 17:14:48 +00003233
bellard8df1cd02005-01-28 22:37:22 +00003234/* warning: addr must be aligned */
3235uint32_t ldl_phys(target_phys_addr_t addr)
3236{
3237 int io_index;
3238 uint8_t *ptr;
3239 uint32_t val;
3240 unsigned long pd;
3241 PhysPageDesc *p;
3242
3243 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3244 if (!p) {
3245 pd = IO_MEM_UNASSIGNED;
3246 } else {
3247 pd = p->phys_offset;
3248 }
ths3b46e622007-09-17 08:09:54 +00003249
ths5fafdf22007-09-16 21:08:06 +00003250 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00003251 !(pd & IO_MEM_ROMD)) {
bellard8df1cd02005-01-28 22:37:22 +00003252 /* I/O case */
3253 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003254 if (p)
3255 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003256 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3257 } else {
3258 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003259 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00003260 (addr & ~TARGET_PAGE_MASK);
3261 val = ldl_p(ptr);
3262 }
3263 return val;
3264}
3265
bellard84b7b8e2005-11-28 21:19:04 +00003266/* warning: addr must be aligned */
3267uint64_t ldq_phys(target_phys_addr_t addr)
3268{
3269 int io_index;
3270 uint8_t *ptr;
3271 uint64_t val;
3272 unsigned long pd;
3273 PhysPageDesc *p;
3274
3275 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3276 if (!p) {
3277 pd = IO_MEM_UNASSIGNED;
3278 } else {
3279 pd = p->phys_offset;
3280 }
ths3b46e622007-09-17 08:09:54 +00003281
bellard2a4188a2006-06-25 21:54:59 +00003282 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3283 !(pd & IO_MEM_ROMD)) {
bellard84b7b8e2005-11-28 21:19:04 +00003284 /* I/O case */
3285 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003286 if (p)
3287 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard84b7b8e2005-11-28 21:19:04 +00003288#ifdef TARGET_WORDS_BIGENDIAN
3289 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3290 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3291#else
3292 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3293 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3294#endif
3295 } else {
3296 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003297 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard84b7b8e2005-11-28 21:19:04 +00003298 (addr & ~TARGET_PAGE_MASK);
3299 val = ldq_p(ptr);
3300 }
3301 return val;
3302}
3303
bellardaab33092005-10-30 20:48:42 +00003304/* XXX: optimize */
3305uint32_t ldub_phys(target_phys_addr_t addr)
3306{
3307 uint8_t val;
3308 cpu_physical_memory_read(addr, &val, 1);
3309 return val;
3310}
3311
3312/* XXX: optimize */
3313uint32_t lduw_phys(target_phys_addr_t addr)
3314{
3315 uint16_t val;
3316 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3317 return tswap16(val);
3318}
3319
bellard8df1cd02005-01-28 22:37:22 +00003320/* warning: addr must be aligned. The ram page is not masked as dirty
3321 and the code inside is not invalidated. It is useful if the dirty
3322 bits are used to track modified PTEs */
3323void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3324{
3325 int io_index;
3326 uint8_t *ptr;
3327 unsigned long pd;
3328 PhysPageDesc *p;
3329
3330 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3331 if (!p) {
3332 pd = IO_MEM_UNASSIGNED;
3333 } else {
3334 pd = p->phys_offset;
3335 }
ths3b46e622007-09-17 08:09:54 +00003336
bellard3a7d9292005-08-21 09:26:42 +00003337 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003338 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003339 if (p)
3340 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003341 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3342 } else {
aliguori74576192008-10-06 14:02:03 +00003343 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3344 ptr = phys_ram_base + addr1;
bellard8df1cd02005-01-28 22:37:22 +00003345 stl_p(ptr, val);
aliguori74576192008-10-06 14:02:03 +00003346
3347 if (unlikely(in_migration)) {
3348 if (!cpu_physical_memory_is_dirty(addr1)) {
3349 /* invalidate code */
3350 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3351 /* set dirty bit */
3352 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3353 (0xff & ~CODE_DIRTY_FLAG);
3354 }
3355 }
bellard8df1cd02005-01-28 22:37:22 +00003356 }
3357}
3358
j_mayerbc98a7e2007-04-04 07:55:12 +00003359void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3360{
3361 int io_index;
3362 uint8_t *ptr;
3363 unsigned long pd;
3364 PhysPageDesc *p;
3365
3366 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3367 if (!p) {
3368 pd = IO_MEM_UNASSIGNED;
3369 } else {
3370 pd = p->phys_offset;
3371 }
ths3b46e622007-09-17 08:09:54 +00003372
j_mayerbc98a7e2007-04-04 07:55:12 +00003373 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3374 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003375 if (p)
3376 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
j_mayerbc98a7e2007-04-04 07:55:12 +00003377#ifdef TARGET_WORDS_BIGENDIAN
3378 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3379 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3380#else
3381 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3382 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3383#endif
3384 } else {
ths5fafdf22007-09-16 21:08:06 +00003385 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
j_mayerbc98a7e2007-04-04 07:55:12 +00003386 (addr & ~TARGET_PAGE_MASK);
3387 stq_p(ptr, val);
3388 }
3389}
3390
bellard8df1cd02005-01-28 22:37:22 +00003391/* warning: addr must be aligned */
bellard8df1cd02005-01-28 22:37:22 +00003392void stl_phys(target_phys_addr_t addr, uint32_t val)
3393{
3394 int io_index;
3395 uint8_t *ptr;
3396 unsigned long pd;
3397 PhysPageDesc *p;
3398
3399 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3400 if (!p) {
3401 pd = IO_MEM_UNASSIGNED;
3402 } else {
3403 pd = p->phys_offset;
3404 }
ths3b46e622007-09-17 08:09:54 +00003405
bellard3a7d9292005-08-21 09:26:42 +00003406 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003407 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003408 if (p)
3409 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003410 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3411 } else {
3412 unsigned long addr1;
3413 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3414 /* RAM case */
3415 ptr = phys_ram_base + addr1;
3416 stl_p(ptr, val);
bellard3a7d9292005-08-21 09:26:42 +00003417 if (!cpu_physical_memory_is_dirty(addr1)) {
3418 /* invalidate code */
3419 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3420 /* set dirty bit */
bellardf23db162005-08-21 19:12:28 +00003421 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3422 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00003423 }
bellard8df1cd02005-01-28 22:37:22 +00003424 }
3425}
3426
bellardaab33092005-10-30 20:48:42 +00003427/* XXX: optimize */
3428void stb_phys(target_phys_addr_t addr, uint32_t val)
3429{
3430 uint8_t v = val;
3431 cpu_physical_memory_write(addr, &v, 1);
3432}
3433
3434/* XXX: optimize */
3435void stw_phys(target_phys_addr_t addr, uint32_t val)
3436{
3437 uint16_t v = tswap16(val);
3438 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3439}
3440
3441/* XXX: optimize */
3442void stq_phys(target_phys_addr_t addr, uint64_t val)
3443{
3444 val = tswap64(val);
3445 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3446}
3447
bellard13eb76e2004-01-24 15:23:36 +00003448#endif
3449
3450/* virtual memory access for debug */
ths5fafdf22007-09-16 21:08:06 +00003451int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
bellardb448f2f2004-02-25 23:24:04 +00003452 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00003453{
3454 int l;
j_mayer9b3c35e2007-04-07 11:21:28 +00003455 target_phys_addr_t phys_addr;
3456 target_ulong page;
bellard13eb76e2004-01-24 15:23:36 +00003457
3458 while (len > 0) {
3459 page = addr & TARGET_PAGE_MASK;
3460 phys_addr = cpu_get_phys_page_debug(env, page);
3461 /* if no physical page mapped, return an error */
3462 if (phys_addr == -1)
3463 return -1;
3464 l = (page + TARGET_PAGE_SIZE) - addr;
3465 if (l > len)
3466 l = len;
ths5fafdf22007-09-16 21:08:06 +00003467 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
bellardb448f2f2004-02-25 23:24:04 +00003468 buf, l, is_write);
bellard13eb76e2004-01-24 15:23:36 +00003469 len -= l;
3470 buf += l;
3471 addr += l;
3472 }
3473 return 0;
3474}
3475
pbrook2e70f6e2008-06-29 01:03:05 +00003476/* in deterministic execution mode, instructions doing device I/Os
3477 must be at the end of the TB */
3478void cpu_io_recompile(CPUState *env, void *retaddr)
3479{
3480 TranslationBlock *tb;
3481 uint32_t n, cflags;
3482 target_ulong pc, cs_base;
3483 uint64_t flags;
3484
3485 tb = tb_find_pc((unsigned long)retaddr);
3486 if (!tb) {
3487 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3488 retaddr);
3489 }
3490 n = env->icount_decr.u16.low + tb->icount;
3491 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3492 /* Calculate how many instructions had been executed before the fault
thsbf20dc02008-06-30 17:22:19 +00003493 occurred. */
pbrook2e70f6e2008-06-29 01:03:05 +00003494 n = n - env->icount_decr.u16.low;
3495 /* Generate a new TB ending on the I/O insn. */
3496 n++;
3497 /* On MIPS and SH, delay slot instructions can only be restarted if
3498 they were already the first instruction in the TB. If this is not
thsbf20dc02008-06-30 17:22:19 +00003499 the first instruction in a TB then re-execute the preceding
pbrook2e70f6e2008-06-29 01:03:05 +00003500 branch. */
3501#if defined(TARGET_MIPS)
3502 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3503 env->active_tc.PC -= 4;
3504 env->icount_decr.u16.low++;
3505 env->hflags &= ~MIPS_HFLAG_BMASK;
3506 }
3507#elif defined(TARGET_SH4)
3508 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3509 && n > 1) {
3510 env->pc -= 2;
3511 env->icount_decr.u16.low++;
3512 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3513 }
3514#endif
3515 /* This should never happen. */
3516 if (n > CF_COUNT_MASK)
3517 cpu_abort(env, "TB too big during recompile");
3518
3519 cflags = n | CF_LAST_IO;
3520 pc = tb->pc;
3521 cs_base = tb->cs_base;
3522 flags = tb->flags;
3523 tb_phys_invalidate(tb, -1);
3524 /* FIXME: In theory this could raise an exception. In practice
3525 we have already translated the block once so it's probably ok. */
3526 tb_gen_code(env, pc, cs_base, flags, cflags);
thsbf20dc02008-06-30 17:22:19 +00003527 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
pbrook2e70f6e2008-06-29 01:03:05 +00003528 the first in the TB) then we end up generating a whole new TB and
3529 repeating the fault, which is horribly inefficient.
3530 Better would be to execute just this insn uncached, or generate a
3531 second new TB. */
3532 cpu_resume_from_signal(env, NULL);
3533}
3534
bellarde3db7222005-01-26 22:00:47 +00003535void dump_exec_info(FILE *f,
3536 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3537{
3538 int i, target_code_size, max_target_code_size;
3539 int direct_jmp_count, direct_jmp2_count, cross_page;
3540 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +00003541
bellarde3db7222005-01-26 22:00:47 +00003542 target_code_size = 0;
3543 max_target_code_size = 0;
3544 cross_page = 0;
3545 direct_jmp_count = 0;
3546 direct_jmp2_count = 0;
3547 for(i = 0; i < nb_tbs; i++) {
3548 tb = &tbs[i];
3549 target_code_size += tb->size;
3550 if (tb->size > max_target_code_size)
3551 max_target_code_size = tb->size;
3552 if (tb->page_addr[1] != -1)
3553 cross_page++;
3554 if (tb->tb_next_offset[0] != 0xffff) {
3555 direct_jmp_count++;
3556 if (tb->tb_next_offset[1] != 0xffff) {
3557 direct_jmp2_count++;
3558 }
3559 }
3560 }
3561 /* XXX: avoid using doubles ? */
bellard57fec1f2008-02-01 10:50:11 +00003562 cpu_fprintf(f, "Translation buffer state:\n");
bellard26a5f132008-05-28 12:30:31 +00003563 cpu_fprintf(f, "gen code size %ld/%ld\n",
3564 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3565 cpu_fprintf(f, "TB count %d/%d\n",
3566 nb_tbs, code_gen_max_blocks);
ths5fafdf22007-09-16 21:08:06 +00003567 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
bellarde3db7222005-01-26 22:00:47 +00003568 nb_tbs ? target_code_size / nb_tbs : 0,
3569 max_target_code_size);
ths5fafdf22007-09-16 21:08:06 +00003570 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
bellarde3db7222005-01-26 22:00:47 +00003571 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3572 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
ths5fafdf22007-09-16 21:08:06 +00003573 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3574 cross_page,
bellarde3db7222005-01-26 22:00:47 +00003575 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3576 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
ths5fafdf22007-09-16 21:08:06 +00003577 direct_jmp_count,
bellarde3db7222005-01-26 22:00:47 +00003578 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3579 direct_jmp2_count,
3580 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
bellard57fec1f2008-02-01 10:50:11 +00003581 cpu_fprintf(f, "\nStatistics:\n");
bellarde3db7222005-01-26 22:00:47 +00003582 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3583 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3584 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
bellardb67d9a52008-05-23 09:57:34 +00003585 tcg_dump_info(f, cpu_fprintf);
bellarde3db7222005-01-26 22:00:47 +00003586}
3587
ths5fafdf22007-09-16 21:08:06 +00003588#if !defined(CONFIG_USER_ONLY)
bellard61382a52003-10-27 21:22:23 +00003589
3590#define MMUSUFFIX _cmmu
3591#define GETPC() NULL
3592#define env cpu_single_env
bellardb769d8f2004-10-03 15:07:13 +00003593#define SOFTMMU_CODE_ACCESS
bellard61382a52003-10-27 21:22:23 +00003594
3595#define SHIFT 0
3596#include "softmmu_template.h"
3597
3598#define SHIFT 1
3599#include "softmmu_template.h"
3600
3601#define SHIFT 2
3602#include "softmmu_template.h"
3603
3604#define SHIFT 3
3605#include "softmmu_template.h"
3606
3607#undef env
3608
3609#endif