blob: cef31955ab18b65f2217af934636a12f762e249b [file] [log] [blame]
Jiang Liu74afab72014-10-27 16:12:00 +08001/*
2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
Jiang Liub5dc8e62015-04-13 14:11:24 +08006 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
Jiang Liu74afab72014-10-27 16:12:00 +08008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/compiler.h>
Jiang Liu74afab72014-10-27 16:12:00 +080016#include <linux/slab.h>
Jiang Liud746d1e2015-04-14 10:30:09 +080017#include <asm/irqdomain.h>
Jiang Liu74afab72014-10-27 16:12:00 +080018#include <asm/hw_irq.h>
19#include <asm/apic.h>
20#include <asm/i8259.h>
21#include <asm/desc.h>
22#include <asm/irq_remapping.h>
23
Jiang Liu7f3262e2015-04-14 10:30:03 +080024struct apic_chip_data {
25 struct irq_cfg cfg;
26 cpumask_var_t domain;
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
29};
30
Jiang Liub5dc8e62015-04-13 14:11:24 +080031struct irq_domain *x86_vector_domain;
Jake Oshinsc8f3e512015-12-10 17:52:59 +000032EXPORT_SYMBOL_GPL(x86_vector_domain);
Jiang Liu74afab72014-10-27 16:12:00 +080033static DEFINE_RAW_SPINLOCK(vector_lock);
Jiang Liu8a580f72015-12-31 16:30:46 +000034static cpumask_var_t vector_cpumask, searched_cpumask;
Jiang Liub5dc8e62015-04-13 14:11:24 +080035static struct irq_chip lapic_controller;
Jiang Liu13315322015-04-13 14:11:56 +080036#ifdef CONFIG_X86_IO_APIC
Jiang Liu7f3262e2015-04-14 10:30:03 +080037static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
Jiang Liu13315322015-04-13 14:11:56 +080038#endif
Jiang Liu74afab72014-10-27 16:12:00 +080039
40void lock_vector_lock(void)
41{
42 /* Used to the online set of cpus does not change
43 * during assign_irq_vector.
44 */
45 raw_spin_lock(&vector_lock);
46}
47
48void unlock_vector_lock(void)
49{
50 raw_spin_unlock(&vector_lock);
51}
52
Jiang Liu7f3262e2015-04-14 10:30:03 +080053static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +080054{
Jiang Liub5dc8e62015-04-13 14:11:24 +080055 if (!irq_data)
56 return NULL;
57
58 while (irq_data->parent_data)
59 irq_data = irq_data->parent_data;
60
Jiang Liu74afab72014-10-27 16:12:00 +080061 return irq_data->chip_data;
62}
63
Jiang Liu7f3262e2015-04-14 10:30:03 +080064struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +080065{
Jiang Liu7f3262e2015-04-14 10:30:03 +080066 struct apic_chip_data *data = apic_chip_data(irq_data);
Jiang Liu74afab72014-10-27 16:12:00 +080067
Jiang Liu7f3262e2015-04-14 10:30:03 +080068 return data ? &data->cfg : NULL;
69}
Jake Oshinsc8f3e512015-12-10 17:52:59 +000070EXPORT_SYMBOL_GPL(irqd_cfg);
Jiang Liu7f3262e2015-04-14 10:30:03 +080071
72struct irq_cfg *irq_cfg(unsigned int irq)
73{
74 return irqd_cfg(irq_get_irq_data(irq));
75}
76
77static struct apic_chip_data *alloc_apic_chip_data(int node)
78{
79 struct apic_chip_data *data;
80
81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!data)
Jiang Liu74afab72014-10-27 16:12:00 +080083 return NULL;
Jiang Liu7f3262e2015-04-14 10:30:03 +080084 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
85 goto out_data;
86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
Jiang Liu74afab72014-10-27 16:12:00 +080087 goto out_domain;
Jiang Liu7f3262e2015-04-14 10:30:03 +080088 return data;
Jiang Liu74afab72014-10-27 16:12:00 +080089out_domain:
Jiang Liu7f3262e2015-04-14 10:30:03 +080090 free_cpumask_var(data->domain);
91out_data:
92 kfree(data);
Jiang Liu74afab72014-10-27 16:12:00 +080093 return NULL;
94}
95
Jiang Liu7f3262e2015-04-14 10:30:03 +080096static void free_apic_chip_data(struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +080097{
Jiang Liu7f3262e2015-04-14 10:30:03 +080098 if (data) {
99 free_cpumask_var(data->domain);
100 free_cpumask_var(data->old_domain);
101 kfree(data);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800102 }
Jiang Liu74afab72014-10-27 16:12:00 +0800103}
104
Jiang Liu7f3262e2015-04-14 10:30:03 +0800105static int __assign_irq_vector(int irq, struct apic_chip_data *d,
106 const struct cpumask *mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800107{
108 /*
109 * NOTE! The local APIC isn't very good at handling
110 * multiple interrupts at the same interrupt level.
111 * As the interrupt level is determined by taking the
112 * vector number and shifting that right by 4, we
113 * want to spread these out a bit so that they don't
114 * all fall in the same interrupt level.
115 *
116 * Also, we've got to be careful not to trash gate
117 * 0x80, because int 0x80 is hm, kind of importantish. ;)
118 */
119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
120 static int current_offset = VECTOR_OFFSET_START % 16;
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000121 int cpu;
Jiang Liu74afab72014-10-27 16:12:00 +0800122
Jiang Liu7f3262e2015-04-14 10:30:03 +0800123 if (d->move_in_progress)
Jiang Liu74afab72014-10-27 16:12:00 +0800124 return -EBUSY;
125
Jiang Liu74afab72014-10-27 16:12:00 +0800126 /* Only try and allocate irqs on cpus that are present */
Jiang Liu7f3262e2015-04-14 10:30:03 +0800127 cpumask_clear(d->old_domain);
Jiang Liu8a580f72015-12-31 16:30:46 +0000128 cpumask_clear(searched_cpumask);
Jiang Liu74afab72014-10-27 16:12:00 +0800129 cpu = cpumask_first_and(mask, cpu_online_mask);
130 while (cpu < nr_cpu_ids) {
131 int new_cpu, vector, offset;
132
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800133 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800134
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800135 if (cpumask_subset(vector_cpumask, d->domain)) {
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800136 if (cpumask_equal(vector_cpumask, d->domain))
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000137 goto success;
Jiang Liu74afab72014-10-27 16:12:00 +0800138 /*
139 * New cpumask using the vector is a proper subset of
140 * the current in use mask. So cleanup the vector
141 * allocation for the members that are not used anymore.
142 */
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800143 cpumask_andnot(d->old_domain, d->domain,
144 vector_cpumask);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800145 d->move_in_progress =
146 cpumask_intersects(d->old_domain, cpu_online_mask);
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800147 cpumask_and(d->domain, d->domain, vector_cpumask);
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000148 goto success;
Jiang Liu74afab72014-10-27 16:12:00 +0800149 }
150
151 vector = current_vector;
152 offset = current_offset;
153next:
154 vector += 16;
155 if (vector >= first_system_vector) {
156 offset = (offset + 1) % 16;
157 vector = FIRST_EXTERNAL_VECTOR + offset;
158 }
159
Thomas Gleixner95ffeb42015-12-31 16:30:47 +0000160 /* If the search wrapped around, try the next cpu */
161 if (unlikely(current_vector == vector))
162 goto next_cpu;
Jiang Liu74afab72014-10-27 16:12:00 +0800163
164 if (test_bit(vector, used_vectors))
165 goto next;
166
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800167 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000168 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
Jiang Liu74afab72014-10-27 16:12:00 +0800169 goto next;
170 }
171 /* Found one! */
172 current_vector = vector;
173 current_offset = offset;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800174 if (d->cfg.vector) {
175 cpumask_copy(d->old_domain, d->domain);
176 d->move_in_progress =
177 cpumask_intersects(d->old_domain, cpu_online_mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800178 }
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800179 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask)
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000180 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800181 d->cfg.vector = vector;
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800182 cpumask_copy(d->domain, vector_cpumask);
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000183 goto success;
Thomas Gleixner95ffeb42015-12-31 16:30:47 +0000184
185next_cpu:
186 /*
187 * We exclude the current @vector_cpumask from the requested
188 * @mask and try again with the next online cpu in the
189 * result. We cannot modify @mask, so we use @vector_cpumask
190 * as a temporary buffer here as it will be reassigned when
191 * calling apic->vector_allocation_domain() above.
192 */
193 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
194 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
195 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
196 continue;
Jiang Liu74afab72014-10-27 16:12:00 +0800197 }
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000198 return -ENOSPC;
Jiang Liu74afab72014-10-27 16:12:00 +0800199
Thomas Gleixner433cbd52015-12-31 16:30:46 +0000200success:
201 /* cache destination APIC IDs into cfg->dest_apicid */
202 return apic->cpu_mask_to_apicid_and(mask, d->domain, &d->cfg.dest_apicid);
Jiang Liu74afab72014-10-27 16:12:00 +0800203}
204
Jiang Liu7f3262e2015-04-14 10:30:03 +0800205static int assign_irq_vector(int irq, struct apic_chip_data *data,
Jiang Liuf9705102015-04-14 10:30:00 +0800206 const struct cpumask *mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800207{
208 int err;
209 unsigned long flags;
210
211 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800212 err = __assign_irq_vector(irq, data, mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800213 raw_spin_unlock_irqrestore(&vector_lock, flags);
214 return err;
215}
216
Jiang Liu486ca532015-05-07 10:53:56 +0800217static int assign_irq_vector_policy(int irq, int node,
218 struct apic_chip_data *data,
219 struct irq_alloc_info *info)
220{
221 if (info && info->mask)
222 return assign_irq_vector(irq, data, info->mask);
223 if (node != NUMA_NO_NODE &&
224 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
225 return 0;
226 return assign_irq_vector(irq, data, apic->target_cpus());
227}
228
Jiang Liu7f3262e2015-04-14 10:30:03 +0800229static void clear_irq_vector(int irq, struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +0800230{
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000231 struct irq_desc *desc;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000232 int cpu, vector;
Jiang Liu74afab72014-10-27 16:12:00 +0800233
Jiang Liu7f3262e2015-04-14 10:30:03 +0800234 BUG_ON(!data->cfg.vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800235
Jiang Liu7f3262e2015-04-14 10:30:03 +0800236 vector = data->cfg.vector;
237 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000238 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800239
Jiang Liu7f3262e2015-04-14 10:30:03 +0800240 data->cfg.vector = 0;
241 cpumask_clear(data->domain);
Jiang Liu74afab72014-10-27 16:12:00 +0800242
Jiang Liu111abeb2015-12-31 16:30:44 +0000243 if (likely(!data->move_in_progress))
Jiang Liu74afab72014-10-27 16:12:00 +0800244 return;
Jiang Liu74afab72014-10-27 16:12:00 +0800245
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000246 desc = irq_to_desc(irq);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800247 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
Jiang Liu74afab72014-10-27 16:12:00 +0800248 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
249 vector++) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000250 if (per_cpu(vector_irq, cpu)[vector] != desc)
Jiang Liu74afab72014-10-27 16:12:00 +0800251 continue;
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000252 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800253 break;
254 }
255 }
Jiang Liu7f3262e2015-04-14 10:30:03 +0800256 data->move_in_progress = 0;
Jiang Liu74afab72014-10-27 16:12:00 +0800257}
258
Jiang Liub5dc8e62015-04-13 14:11:24 +0800259void init_irq_alloc_info(struct irq_alloc_info *info,
260 const struct cpumask *mask)
261{
262 memset(info, 0, sizeof(*info));
263 info->mask = mask;
264}
265
266void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
267{
268 if (src)
269 *dst = *src;
270 else
271 memset(dst, 0, sizeof(*dst));
272}
273
Jiang Liub5dc8e62015-04-13 14:11:24 +0800274static void x86_vector_free_irqs(struct irq_domain *domain,
275 unsigned int virq, unsigned int nr_irqs)
276{
Jiang Liu111abeb2015-12-31 16:30:44 +0000277 struct apic_chip_data *apic_data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800278 struct irq_data *irq_data;
Jiang Liu111abeb2015-12-31 16:30:44 +0000279 unsigned long flags;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800280 int i;
281
282 for (i = 0; i < nr_irqs; i++) {
283 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
284 if (irq_data && irq_data->chip_data) {
Jiang Liu111abeb2015-12-31 16:30:44 +0000285 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800286 clear_irq_vector(virq + i, irq_data->chip_data);
Jiang Liu111abeb2015-12-31 16:30:44 +0000287 apic_data = irq_data->chip_data;
288 irq_domain_reset_irq_data(irq_data);
289 raw_spin_unlock_irqrestore(&vector_lock, flags);
290 free_apic_chip_data(apic_data);
Jiang Liu13315322015-04-13 14:11:56 +0800291#ifdef CONFIG_X86_IO_APIC
292 if (virq + i < nr_legacy_irqs())
Jiang Liu7f3262e2015-04-14 10:30:03 +0800293 legacy_irq_data[virq + i] = NULL;
Jiang Liu13315322015-04-13 14:11:56 +0800294#endif
Jiang Liub5dc8e62015-04-13 14:11:24 +0800295 }
296 }
297}
298
299static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
300 unsigned int nr_irqs, void *arg)
301{
302 struct irq_alloc_info *info = arg;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800303 struct apic_chip_data *data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800304 struct irq_data *irq_data;
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800305 int i, err, node;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800306
307 if (disable_apic)
308 return -ENXIO;
309
310 /* Currently vector allocator can't guarantee contiguous allocations */
311 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
312 return -ENOSYS;
313
Jiang Liub5dc8e62015-04-13 14:11:24 +0800314 for (i = 0; i < nr_irqs; i++) {
315 irq_data = irq_domain_get_irq_data(domain, virq + i);
316 BUG_ON(!irq_data);
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800317 node = irq_data_get_node(irq_data);
Jiang Liu13315322015-04-13 14:11:56 +0800318#ifdef CONFIG_X86_IO_APIC
Jiang Liu7f3262e2015-04-14 10:30:03 +0800319 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
320 data = legacy_irq_data[virq + i];
Jiang Liu13315322015-04-13 14:11:56 +0800321 else
322#endif
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800323 data = alloc_apic_chip_data(node);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800324 if (!data) {
Jiang Liub5dc8e62015-04-13 14:11:24 +0800325 err = -ENOMEM;
326 goto error;
327 }
328
329 irq_data->chip = &lapic_controller;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800330 irq_data->chip_data = data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800331 irq_data->hwirq = virq + i;
Linus Torvalds43af9872015-09-01 15:20:51 -0700332 err = assign_irq_vector_policy(virq + i, node, data, info);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800333 if (err)
334 goto error;
335 }
336
337 return 0;
338
339error:
340 x86_vector_free_irqs(domain, virq, i + 1);
341 return err;
342}
343
Thomas Gleixnereb18cf52015-05-05 11:10:11 +0200344static const struct irq_domain_ops x86_vector_domain_ops = {
345 .alloc = x86_vector_alloc_irqs,
346 .free = x86_vector_free_irqs,
Jiang Liub5dc8e62015-04-13 14:11:24 +0800347};
348
Jiang Liu11d686e2014-10-27 16:12:05 +0800349int __init arch_probe_nr_irqs(void)
350{
351 int nr;
352
353 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
354 nr_irqs = NR_VECTORS * nr_cpu_ids;
355
356 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
357#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
358 /*
359 * for MSI and HT dyn irq
360 */
361 if (gsi_top <= NR_IRQS_LEGACY)
362 nr += 8 * nr_cpu_ids;
363 else
364 nr += gsi_top * 16;
365#endif
366 if (nr < nr_irqs)
367 nr_irqs = nr;
368
Vitaly Kuznetsov8c058b02015-11-03 10:40:14 +0100369 /*
370 * We don't know if PIC is present at this point so we need to do
371 * probe() to get the right number of legacy IRQs.
372 */
373 return legacy_pic->probe();
Jiang Liu11d686e2014-10-27 16:12:05 +0800374}
375
Jiang Liu13315322015-04-13 14:11:56 +0800376#ifdef CONFIG_X86_IO_APIC
377static void init_legacy_irqs(void)
378{
379 int i, node = cpu_to_node(0);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800380 struct apic_chip_data *data;
Jiang Liu13315322015-04-13 14:11:56 +0800381
382 /*
383 * For legacy IRQ's, start with assigning irq0 to irq15 to
Ingo Molnar191a66352015-05-11 16:05:09 +0200384 * ISA_IRQ_VECTOR(i) for all cpu's.
Jiang Liu13315322015-04-13 14:11:56 +0800385 */
386 for (i = 0; i < nr_legacy_irqs(); i++) {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800387 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
388 BUG_ON(!data);
Ingo Molnar191a66352015-05-11 16:05:09 +0200389
390 data->cfg.vector = ISA_IRQ_VECTOR(i);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800391 cpumask_setall(data->domain);
392 irq_set_chip_data(i, data);
Jiang Liu13315322015-04-13 14:11:56 +0800393 }
394}
395#else
396static void init_legacy_irqs(void) { }
397#endif
398
Jiang Liu11d686e2014-10-27 16:12:05 +0800399int __init arch_early_irq_init(void)
400{
Jiang Liu13315322015-04-13 14:11:56 +0800401 init_legacy_irqs();
402
Jiang Liub5dc8e62015-04-13 14:11:24 +0800403 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
404 NULL);
405 BUG_ON(x86_vector_domain == NULL);
406 irq_set_default_host(x86_vector_domain);
407
Jiang Liu52f518a2015-04-13 14:11:35 +0800408 arch_init_msi_domain(x86_vector_domain);
Jiang Liu49e07d82015-04-13 14:11:43 +0800409 arch_init_htirq_domain(x86_vector_domain);
Jiang Liu52f518a2015-04-13 14:11:35 +0800410
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800411 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
Jiang Liu8a580f72015-12-31 16:30:46 +0000412 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800413
Jiang Liu11d686e2014-10-27 16:12:05 +0800414 return arch_early_ioapic_init();
415}
416
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000417/* Initialize vector_irq on a new cpu */
Jiang Liu74afab72014-10-27 16:12:00 +0800418static void __setup_vector_irq(int cpu)
419{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800420 struct apic_chip_data *data;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000421 struct irq_desc *desc;
422 int irq, vector;
Jiang Liu74afab72014-10-27 16:12:00 +0800423
Jiang Liu74afab72014-10-27 16:12:00 +0800424 /* Mark the inuse vectors */
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000425 for_each_irq_desc(irq, desc) {
426 struct irq_data *idata = irq_desc_get_irq_data(desc);
Jiang Liu74afab72014-10-27 16:12:00 +0800427
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000428 data = apic_chip_data(idata);
429 if (!data || !cpumask_test_cpu(cpu, data->domain))
Jiang Liu74afab72014-10-27 16:12:00 +0800430 continue;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800431 vector = data->cfg.vector;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000432 per_cpu(vector_irq, cpu)[vector] = desc;
Jiang Liu74afab72014-10-27 16:12:00 +0800433 }
434 /* Mark the free vectors */
435 for (vector = 0; vector < NR_VECTORS; ++vector) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000436 desc = per_cpu(vector_irq, cpu)[vector];
437 if (IS_ERR_OR_NULL(desc))
Jiang Liu74afab72014-10-27 16:12:00 +0800438 continue;
439
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000440 data = apic_chip_data(irq_desc_get_irq_data(desc));
Jiang Liu7f3262e2015-04-14 10:30:03 +0800441 if (!cpumask_test_cpu(cpu, data->domain))
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000442 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800443 }
Jiang Liu74afab72014-10-27 16:12:00 +0800444}
445
446/*
Thomas Gleixner5a3f75e2015-07-05 17:12:32 +0000447 * Setup the vector to irq mappings. Must be called with vector_lock held.
Jiang Liu74afab72014-10-27 16:12:00 +0800448 */
449void setup_vector_irq(int cpu)
450{
451 int irq;
452
Thomas Gleixner5a3f75e2015-07-05 17:12:32 +0000453 lockdep_assert_held(&vector_lock);
Jiang Liu74afab72014-10-27 16:12:00 +0800454 /*
455 * On most of the platforms, legacy PIC delivers the interrupts on the
456 * boot cpu. But there are certain platforms where PIC interrupts are
457 * delivered to multiple cpu's. If the legacy IRQ is handled by the
458 * legacy PIC, for the new cpu that is coming online, setup the static
459 * legacy vector to irq mapping:
460 */
461 for (irq = 0; irq < nr_legacy_irqs(); irq++)
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000462 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
Jiang Liu74afab72014-10-27 16:12:00 +0800463
464 __setup_vector_irq(cpu);
465}
466
Jiang Liu7f3262e2015-04-14 10:30:03 +0800467static int apic_retrigger_irq(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +0800468{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800469 struct apic_chip_data *data = apic_chip_data(irq_data);
Jiang Liu74afab72014-10-27 16:12:00 +0800470 unsigned long flags;
471 int cpu;
472
473 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800474 cpu = cpumask_first_and(data->domain, cpu_online_mask);
475 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800476 raw_spin_unlock_irqrestore(&vector_lock, flags);
477
478 return 1;
479}
480
481void apic_ack_edge(struct irq_data *data)
482{
Jiang Liua9786092014-10-27 16:12:07 +0800483 irq_complete_move(irqd_cfg(data));
Jiang Liu74afab72014-10-27 16:12:00 +0800484 irq_move_irq(data);
485 ack_APIC_irq();
486}
487
Jiang Liu68f9f442015-04-14 10:30:01 +0800488static int apic_set_affinity(struct irq_data *irq_data,
489 const struct cpumask *dest, bool force)
Jiang Liub5dc8e62015-04-13 14:11:24 +0800490{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800491 struct apic_chip_data *data = irq_data->chip_data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800492 int err, irq = irq_data->irq;
493
494 if (!config_enabled(CONFIG_SMP))
495 return -EPERM;
496
497 if (!cpumask_intersects(dest, cpu_online_mask))
498 return -EINVAL;
499
Jiang Liu7f3262e2015-04-14 10:30:03 +0800500 err = assign_irq_vector(irq, data, dest);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800501 if (err) {
Jiang Liuc149e4c2015-06-03 11:46:22 +0800502 if (assign_irq_vector(irq, data,
Jiang Liu9df872f2015-06-03 11:47:50 +0800503 irq_data_get_affinity_mask(irq_data)))
Jiang Liub5dc8e62015-04-13 14:11:24 +0800504 pr_err("Failed to recover vector for irq %d\n", irq);
505 return err;
506 }
507
508 return IRQ_SET_MASK_OK;
509}
510
511static struct irq_chip lapic_controller = {
512 .irq_ack = apic_ack_edge,
Jiang Liu68f9f442015-04-14 10:30:01 +0800513 .irq_set_affinity = apic_set_affinity,
Jiang Liub5dc8e62015-04-13 14:11:24 +0800514 .irq_retrigger = apic_retrigger_irq,
515};
516
Jiang Liu74afab72014-10-27 16:12:00 +0800517#ifdef CONFIG_SMP
Jiang Liu7f3262e2015-04-14 10:30:03 +0800518static void __send_cleanup_vector(struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +0800519{
520 cpumask_var_t cleanup_mask;
521
522 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
523 unsigned int i;
524
Jiang Liu7f3262e2015-04-14 10:30:03 +0800525 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800526 apic->send_IPI_mask(cpumask_of(i),
527 IRQ_MOVE_CLEANUP_VECTOR);
528 } else {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800529 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800530 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
531 free_cpumask_var(cleanup_mask);
532 }
Jiang Liu7f3262e2015-04-14 10:30:03 +0800533 data->move_in_progress = 0;
Jiang Liu74afab72014-10-27 16:12:00 +0800534}
535
Jiang Liuc6c20022015-04-14 10:30:02 +0800536void send_cleanup_vector(struct irq_cfg *cfg)
537{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800538 struct apic_chip_data *data;
539
540 data = container_of(cfg, struct apic_chip_data, cfg);
541 if (data->move_in_progress)
542 __send_cleanup_vector(data);
Jiang Liuc6c20022015-04-14 10:30:02 +0800543}
544
Jiang Liu74afab72014-10-27 16:12:00 +0800545asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
546{
547 unsigned vector, me;
548
Thomas Gleixner6af7faf2015-05-15 15:48:25 +0200549 entering_ack_irq();
Jiang Liu74afab72014-10-27 16:12:00 +0800550
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000551 /* Prevent vectors vanishing under us */
552 raw_spin_lock(&vector_lock);
553
Jiang Liu74afab72014-10-27 16:12:00 +0800554 me = smp_processor_id();
555 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800556 struct apic_chip_data *data;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000557 struct irq_desc *desc;
558 unsigned int irr;
Jiang Liu74afab72014-10-27 16:12:00 +0800559
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000560 retry:
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000561 desc = __this_cpu_read(vector_irq[vector]);
562 if (IS_ERR_OR_NULL(desc))
Jiang Liu74afab72014-10-27 16:12:00 +0800563 continue;
564
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000565 if (!raw_spin_trylock(&desc->lock)) {
566 raw_spin_unlock(&vector_lock);
567 cpu_relax();
568 raw_spin_lock(&vector_lock);
569 goto retry;
570 }
Jiang Liu74afab72014-10-27 16:12:00 +0800571
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000572 data = apic_chip_data(irq_desc_get_irq_data(desc));
Jiang Liu7f3262e2015-04-14 10:30:03 +0800573 if (!data)
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000574 goto unlock;
Jiang Liu74afab72014-10-27 16:12:00 +0800575
576 /*
577 * Check if the irq migration is in progress. If so, we
578 * haven't received the cleanup request yet for this irq.
579 */
Jiang Liu7f3262e2015-04-14 10:30:03 +0800580 if (data->move_in_progress)
Jiang Liu74afab72014-10-27 16:12:00 +0800581 goto unlock;
582
Jiang Liu7f3262e2015-04-14 10:30:03 +0800583 if (vector == data->cfg.vector &&
584 cpumask_test_cpu(me, data->domain))
Jiang Liu74afab72014-10-27 16:12:00 +0800585 goto unlock;
586
587 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
588 /*
589 * Check if the vector that needs to be cleanedup is
590 * registered at the cpu's IRR. If so, then this is not
591 * the best time to clean it up. Lets clean it up in the
592 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
593 * to myself.
594 */
595 if (irr & (1 << (vector % 32))) {
596 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
597 goto unlock;
598 }
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000599 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
Jiang Liu74afab72014-10-27 16:12:00 +0800600unlock:
601 raw_spin_unlock(&desc->lock);
602 }
603
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000604 raw_spin_unlock(&vector_lock);
605
Thomas Gleixner6af7faf2015-05-15 15:48:25 +0200606 exiting_irq();
Jiang Liu74afab72014-10-27 16:12:00 +0800607}
608
609static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
610{
611 unsigned me;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800612 struct apic_chip_data *data;
Jiang Liu74afab72014-10-27 16:12:00 +0800613
Jiang Liu7f3262e2015-04-14 10:30:03 +0800614 data = container_of(cfg, struct apic_chip_data, cfg);
615 if (likely(!data->move_in_progress))
Jiang Liu74afab72014-10-27 16:12:00 +0800616 return;
617
618 me = smp_processor_id();
Jiang Liu7f3262e2015-04-14 10:30:03 +0800619 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
620 __send_cleanup_vector(data);
Jiang Liu74afab72014-10-27 16:12:00 +0800621}
622
623void irq_complete_move(struct irq_cfg *cfg)
624{
625 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
626}
627
628void irq_force_complete_move(int irq)
629{
630 struct irq_cfg *cfg = irq_cfg(irq);
631
Jiang Liu7f3262e2015-04-14 10:30:03 +0800632 if (cfg)
633 __irq_complete_move(cfg, cfg->vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800634}
Jiang Liu74afab72014-10-27 16:12:00 +0800635#endif
636
Jiang Liu74afab72014-10-27 16:12:00 +0800637static void __init print_APIC_field(int base)
638{
639 int i;
640
641 printk(KERN_DEBUG);
642
643 for (i = 0; i < 8; i++)
644 pr_cont("%08x", apic_read(base + i*0x10));
645
646 pr_cont("\n");
647}
648
649static void __init print_local_APIC(void *dummy)
650{
651 unsigned int i, v, ver, maxlvt;
652 u64 icr;
653
Jiang Liu849d3562014-10-27 16:12:01 +0800654 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
655 smp_processor_id(), hard_smp_processor_id());
Jiang Liu74afab72014-10-27 16:12:00 +0800656 v = apic_read(APIC_ID);
Jiang Liu849d3562014-10-27 16:12:01 +0800657 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
Jiang Liu74afab72014-10-27 16:12:00 +0800658 v = apic_read(APIC_LVR);
Jiang Liu849d3562014-10-27 16:12:01 +0800659 pr_info("... APIC VERSION: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800660 ver = GET_APIC_VERSION(v);
661 maxlvt = lapic_get_maxlvt();
662
663 v = apic_read(APIC_TASKPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800664 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
Jiang Liu74afab72014-10-27 16:12:00 +0800665
666 /* !82489DX */
667 if (APIC_INTEGRATED(ver)) {
668 if (!APIC_XAPIC(ver)) {
669 v = apic_read(APIC_ARBPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800670 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
671 v, v & APIC_ARBPRI_MASK);
Jiang Liu74afab72014-10-27 16:12:00 +0800672 }
673 v = apic_read(APIC_PROCPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800674 pr_debug("... APIC PROCPRI: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800675 }
676
677 /*
678 * Remote read supported only in the 82489DX and local APIC for
679 * Pentium processors.
680 */
681 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
682 v = apic_read(APIC_RRR);
Jiang Liu849d3562014-10-27 16:12:01 +0800683 pr_debug("... APIC RRR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800684 }
685
686 v = apic_read(APIC_LDR);
Jiang Liu849d3562014-10-27 16:12:01 +0800687 pr_debug("... APIC LDR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800688 if (!x2apic_enabled()) {
689 v = apic_read(APIC_DFR);
Jiang Liu849d3562014-10-27 16:12:01 +0800690 pr_debug("... APIC DFR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800691 }
692 v = apic_read(APIC_SPIV);
Jiang Liu849d3562014-10-27 16:12:01 +0800693 pr_debug("... APIC SPIV: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800694
Jiang Liu849d3562014-10-27 16:12:01 +0800695 pr_debug("... APIC ISR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800696 print_APIC_field(APIC_ISR);
Jiang Liu849d3562014-10-27 16:12:01 +0800697 pr_debug("... APIC TMR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800698 print_APIC_field(APIC_TMR);
Jiang Liu849d3562014-10-27 16:12:01 +0800699 pr_debug("... APIC IRR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800700 print_APIC_field(APIC_IRR);
701
702 /* !82489DX */
703 if (APIC_INTEGRATED(ver)) {
704 /* Due to the Pentium erratum 3AP. */
705 if (maxlvt > 3)
706 apic_write(APIC_ESR, 0);
707
708 v = apic_read(APIC_ESR);
Jiang Liu849d3562014-10-27 16:12:01 +0800709 pr_debug("... APIC ESR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800710 }
711
712 icr = apic_icr_read();
Jiang Liu849d3562014-10-27 16:12:01 +0800713 pr_debug("... APIC ICR: %08x\n", (u32)icr);
714 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
Jiang Liu74afab72014-10-27 16:12:00 +0800715
716 v = apic_read(APIC_LVTT);
Jiang Liu849d3562014-10-27 16:12:01 +0800717 pr_debug("... APIC LVTT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800718
719 if (maxlvt > 3) {
720 /* PC is LVT#4. */
721 v = apic_read(APIC_LVTPC);
Jiang Liu849d3562014-10-27 16:12:01 +0800722 pr_debug("... APIC LVTPC: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800723 }
724 v = apic_read(APIC_LVT0);
Jiang Liu849d3562014-10-27 16:12:01 +0800725 pr_debug("... APIC LVT0: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800726 v = apic_read(APIC_LVT1);
Jiang Liu849d3562014-10-27 16:12:01 +0800727 pr_debug("... APIC LVT1: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800728
729 if (maxlvt > 2) {
730 /* ERR is LVT#3. */
731 v = apic_read(APIC_LVTERR);
Jiang Liu849d3562014-10-27 16:12:01 +0800732 pr_debug("... APIC LVTERR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800733 }
734
735 v = apic_read(APIC_TMICT);
Jiang Liu849d3562014-10-27 16:12:01 +0800736 pr_debug("... APIC TMICT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800737 v = apic_read(APIC_TMCCT);
Jiang Liu849d3562014-10-27 16:12:01 +0800738 pr_debug("... APIC TMCCT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800739 v = apic_read(APIC_TDCR);
Jiang Liu849d3562014-10-27 16:12:01 +0800740 pr_debug("... APIC TDCR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800741
742 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
743 v = apic_read(APIC_EFEAT);
744 maxlvt = (v >> 16) & 0xff;
Jiang Liu849d3562014-10-27 16:12:01 +0800745 pr_debug("... APIC EFEAT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800746 v = apic_read(APIC_ECTRL);
Jiang Liu849d3562014-10-27 16:12:01 +0800747 pr_debug("... APIC ECTRL: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800748 for (i = 0; i < maxlvt; i++) {
749 v = apic_read(APIC_EILVTn(i));
Jiang Liu849d3562014-10-27 16:12:01 +0800750 pr_debug("... APIC EILVT%d: %08x\n", i, v);
Jiang Liu74afab72014-10-27 16:12:00 +0800751 }
752 }
753 pr_cont("\n");
754}
755
756static void __init print_local_APICs(int maxcpu)
757{
758 int cpu;
759
760 if (!maxcpu)
761 return;
762
763 preempt_disable();
764 for_each_online_cpu(cpu) {
765 if (cpu >= maxcpu)
766 break;
767 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
768 }
769 preempt_enable();
770}
771
772static void __init print_PIC(void)
773{
774 unsigned int v;
775 unsigned long flags;
776
777 if (!nr_legacy_irqs())
778 return;
779
Jiang Liu849d3562014-10-27 16:12:01 +0800780 pr_debug("\nprinting PIC contents\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800781
782 raw_spin_lock_irqsave(&i8259A_lock, flags);
783
784 v = inb(0xa1) << 8 | inb(0x21);
Jiang Liu849d3562014-10-27 16:12:01 +0800785 pr_debug("... PIC IMR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800786
787 v = inb(0xa0) << 8 | inb(0x20);
Jiang Liu849d3562014-10-27 16:12:01 +0800788 pr_debug("... PIC IRR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800789
790 outb(0x0b, 0xa0);
791 outb(0x0b, 0x20);
792 v = inb(0xa0) << 8 | inb(0x20);
793 outb(0x0a, 0xa0);
794 outb(0x0a, 0x20);
795
796 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
797
Jiang Liu849d3562014-10-27 16:12:01 +0800798 pr_debug("... PIC ISR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800799
800 v = inb(0x4d1) << 8 | inb(0x4d0);
Jiang Liu849d3562014-10-27 16:12:01 +0800801 pr_debug("... PIC ELCR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800802}
803
804static int show_lapic __initdata = 1;
805static __init int setup_show_lapic(char *arg)
806{
807 int num = -1;
808
809 if (strcmp(arg, "all") == 0) {
810 show_lapic = CONFIG_NR_CPUS;
811 } else {
812 get_option(&arg, &num);
813 if (num >= 0)
814 show_lapic = num;
815 }
816
817 return 1;
818}
819__setup("show_lapic=", setup_show_lapic);
820
821static int __init print_ICs(void)
822{
823 if (apic_verbosity == APIC_QUIET)
824 return 0;
825
826 print_PIC();
827
828 /* don't print out if apic is not there */
829 if (!cpu_has_apic && !apic_from_smp_config())
830 return 0;
831
832 print_local_APICs(show_lapic);
833 print_IO_APICs();
834
835 return 0;
836}
837
838late_initcall(print_ICs);