blob: 200b5a5d6b795f0b894ae5c8294c9017a34dbb0a [file] [log] [blame]
Jiang Liu74afab72014-10-27 16:12:00 +08001/*
2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
Jiang Liub5dc8e62015-04-13 14:11:24 +08006 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
Jiang Liu74afab72014-10-27 16:12:00 +08008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/compiler.h>
Jiang Liu74afab72014-10-27 16:12:00 +080016#include <linux/slab.h>
Jiang Liud746d1e2015-04-14 10:30:09 +080017#include <asm/irqdomain.h>
Jiang Liu74afab72014-10-27 16:12:00 +080018#include <asm/hw_irq.h>
19#include <asm/apic.h>
20#include <asm/i8259.h>
21#include <asm/desc.h>
22#include <asm/irq_remapping.h>
23
Jiang Liu7f3262e2015-04-14 10:30:03 +080024struct apic_chip_data {
25 struct irq_cfg cfg;
26 cpumask_var_t domain;
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
29};
30
Jiang Liub5dc8e62015-04-13 14:11:24 +080031struct irq_domain *x86_vector_domain;
Jiang Liu74afab72014-10-27 16:12:00 +080032static DEFINE_RAW_SPINLOCK(vector_lock);
Jiang Liuf7fa7ae2015-04-14 10:30:10 +080033static cpumask_var_t vector_cpumask;
Jiang Liub5dc8e62015-04-13 14:11:24 +080034static struct irq_chip lapic_controller;
Jiang Liu13315322015-04-13 14:11:56 +080035#ifdef CONFIG_X86_IO_APIC
Jiang Liu7f3262e2015-04-14 10:30:03 +080036static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
Jiang Liu13315322015-04-13 14:11:56 +080037#endif
Jiang Liu74afab72014-10-27 16:12:00 +080038
39void lock_vector_lock(void)
40{
41 /* Used to the online set of cpus does not change
42 * during assign_irq_vector.
43 */
44 raw_spin_lock(&vector_lock);
45}
46
47void unlock_vector_lock(void)
48{
49 raw_spin_unlock(&vector_lock);
50}
51
Jiang Liu7f3262e2015-04-14 10:30:03 +080052static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +080053{
Jiang Liub5dc8e62015-04-13 14:11:24 +080054 if (!irq_data)
55 return NULL;
56
57 while (irq_data->parent_data)
58 irq_data = irq_data->parent_data;
59
Jiang Liu74afab72014-10-27 16:12:00 +080060 return irq_data->chip_data;
61}
62
Jiang Liu7f3262e2015-04-14 10:30:03 +080063struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +080064{
Jiang Liu7f3262e2015-04-14 10:30:03 +080065 struct apic_chip_data *data = apic_chip_data(irq_data);
Jiang Liu74afab72014-10-27 16:12:00 +080066
Jiang Liu7f3262e2015-04-14 10:30:03 +080067 return data ? &data->cfg : NULL;
68}
69
70struct irq_cfg *irq_cfg(unsigned int irq)
71{
72 return irqd_cfg(irq_get_irq_data(irq));
73}
74
75static struct apic_chip_data *alloc_apic_chip_data(int node)
76{
77 struct apic_chip_data *data;
78
79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
80 if (!data)
Jiang Liu74afab72014-10-27 16:12:00 +080081 return NULL;
Jiang Liu7f3262e2015-04-14 10:30:03 +080082 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
83 goto out_data;
84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
Jiang Liu74afab72014-10-27 16:12:00 +080085 goto out_domain;
Jiang Liu7f3262e2015-04-14 10:30:03 +080086 return data;
Jiang Liu74afab72014-10-27 16:12:00 +080087out_domain:
Jiang Liu7f3262e2015-04-14 10:30:03 +080088 free_cpumask_var(data->domain);
89out_data:
90 kfree(data);
Jiang Liu74afab72014-10-27 16:12:00 +080091 return NULL;
92}
93
Jiang Liu7f3262e2015-04-14 10:30:03 +080094static void free_apic_chip_data(struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +080095{
Jiang Liu7f3262e2015-04-14 10:30:03 +080096 if (data) {
97 free_cpumask_var(data->domain);
98 free_cpumask_var(data->old_domain);
99 kfree(data);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800100 }
Jiang Liu74afab72014-10-27 16:12:00 +0800101}
102
Jiang Liu7f3262e2015-04-14 10:30:03 +0800103static int __assign_irq_vector(int irq, struct apic_chip_data *d,
104 const struct cpumask *mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800105{
106 /*
107 * NOTE! The local APIC isn't very good at handling
108 * multiple interrupts at the same interrupt level.
109 * As the interrupt level is determined by taking the
110 * vector number and shifting that right by 4, we
111 * want to spread these out a bit so that they don't
112 * all fall in the same interrupt level.
113 *
114 * Also, we've got to be careful not to trash gate
115 * 0x80, because int 0x80 is hm, kind of importantish. ;)
116 */
117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
118 static int current_offset = VECTOR_OFFSET_START % 16;
119 int cpu, err;
Jiang Liu74afab72014-10-27 16:12:00 +0800120
Jiang Liu7f3262e2015-04-14 10:30:03 +0800121 if (d->move_in_progress)
Jiang Liu74afab72014-10-27 16:12:00 +0800122 return -EBUSY;
123
Jiang Liu74afab72014-10-27 16:12:00 +0800124 /* Only try and allocate irqs on cpus that are present */
125 err = -ENOSPC;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800126 cpumask_clear(d->old_domain);
Jiang Liu74afab72014-10-27 16:12:00 +0800127 cpu = cpumask_first_and(mask, cpu_online_mask);
128 while (cpu < nr_cpu_ids) {
129 int new_cpu, vector, offset;
130
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800131 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800132
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800133 if (cpumask_subset(vector_cpumask, d->domain)) {
Jiang Liu74afab72014-10-27 16:12:00 +0800134 err = 0;
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800135 if (cpumask_equal(vector_cpumask, d->domain))
Jiang Liu74afab72014-10-27 16:12:00 +0800136 break;
137 /*
138 * New cpumask using the vector is a proper subset of
139 * the current in use mask. So cleanup the vector
140 * allocation for the members that are not used anymore.
141 */
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800142 cpumask_andnot(d->old_domain, d->domain,
143 vector_cpumask);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800144 d->move_in_progress =
145 cpumask_intersects(d->old_domain, cpu_online_mask);
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800146 cpumask_and(d->domain, d->domain, vector_cpumask);
Jiang Liu74afab72014-10-27 16:12:00 +0800147 break;
148 }
149
150 vector = current_vector;
151 offset = current_offset;
152next:
153 vector += 16;
154 if (vector >= first_system_vector) {
155 offset = (offset + 1) % 16;
156 vector = FIRST_EXTERNAL_VECTOR + offset;
157 }
158
159 if (unlikely(current_vector == vector)) {
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800160 cpumask_or(d->old_domain, d->old_domain,
161 vector_cpumask);
162 cpumask_andnot(vector_cpumask, mask, d->old_domain);
163 cpu = cpumask_first_and(vector_cpumask,
164 cpu_online_mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800165 continue;
166 }
167
168 if (test_bit(vector, used_vectors))
169 goto next;
170
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800171 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000172 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
Jiang Liu74afab72014-10-27 16:12:00 +0800173 goto next;
174 }
175 /* Found one! */
176 current_vector = vector;
177 current_offset = offset;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800178 if (d->cfg.vector) {
179 cpumask_copy(d->old_domain, d->domain);
180 d->move_in_progress =
181 cpumask_intersects(d->old_domain, cpu_online_mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800182 }
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800183 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask)
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000184 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800185 d->cfg.vector = vector;
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800186 cpumask_copy(d->domain, vector_cpumask);
Jiang Liu74afab72014-10-27 16:12:00 +0800187 err = 0;
188 break;
189 }
Jiang Liu74afab72014-10-27 16:12:00 +0800190
Jiang Liu5f0052f2015-04-13 14:11:23 +0800191 if (!err) {
192 /* cache destination APIC IDs into cfg->dest_apicid */
Jiang Liu7f3262e2015-04-14 10:30:03 +0800193 err = apic->cpu_mask_to_apicid_and(mask, d->domain,
194 &d->cfg.dest_apicid);
Jiang Liu5f0052f2015-04-13 14:11:23 +0800195 }
196
Jiang Liu74afab72014-10-27 16:12:00 +0800197 return err;
198}
199
Jiang Liu7f3262e2015-04-14 10:30:03 +0800200static int assign_irq_vector(int irq, struct apic_chip_data *data,
Jiang Liuf9705102015-04-14 10:30:00 +0800201 const struct cpumask *mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800202{
203 int err;
204 unsigned long flags;
205
206 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800207 err = __assign_irq_vector(irq, data, mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800208 raw_spin_unlock_irqrestore(&vector_lock, flags);
209 return err;
210}
211
Jiang Liu486ca532015-05-07 10:53:56 +0800212static int assign_irq_vector_policy(int irq, int node,
213 struct apic_chip_data *data,
214 struct irq_alloc_info *info)
215{
216 if (info && info->mask)
217 return assign_irq_vector(irq, data, info->mask);
218 if (node != NUMA_NO_NODE &&
219 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
220 return 0;
221 return assign_irq_vector(irq, data, apic->target_cpus());
222}
223
Jiang Liu7f3262e2015-04-14 10:30:03 +0800224static void clear_irq_vector(int irq, struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +0800225{
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000226 struct irq_desc *desc;
Jiang Liu74afab72014-10-27 16:12:00 +0800227 unsigned long flags;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000228 int cpu, vector;
Jiang Liu74afab72014-10-27 16:12:00 +0800229
230 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800231 BUG_ON(!data->cfg.vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800232
Jiang Liu7f3262e2015-04-14 10:30:03 +0800233 vector = data->cfg.vector;
234 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000235 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800236
Jiang Liu7f3262e2015-04-14 10:30:03 +0800237 data->cfg.vector = 0;
238 cpumask_clear(data->domain);
Jiang Liu74afab72014-10-27 16:12:00 +0800239
Jiang Liu7f3262e2015-04-14 10:30:03 +0800240 if (likely(!data->move_in_progress)) {
Jiang Liu74afab72014-10-27 16:12:00 +0800241 raw_spin_unlock_irqrestore(&vector_lock, flags);
242 return;
243 }
244
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000245 desc = irq_to_desc(irq);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800246 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
Jiang Liu74afab72014-10-27 16:12:00 +0800247 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
248 vector++) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000249 if (per_cpu(vector_irq, cpu)[vector] != desc)
Jiang Liu74afab72014-10-27 16:12:00 +0800250 continue;
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000251 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800252 break;
253 }
254 }
Jiang Liu7f3262e2015-04-14 10:30:03 +0800255 data->move_in_progress = 0;
Jiang Liu74afab72014-10-27 16:12:00 +0800256 raw_spin_unlock_irqrestore(&vector_lock, flags);
257}
258
Jiang Liub5dc8e62015-04-13 14:11:24 +0800259void init_irq_alloc_info(struct irq_alloc_info *info,
260 const struct cpumask *mask)
261{
262 memset(info, 0, sizeof(*info));
263 info->mask = mask;
264}
265
266void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
267{
268 if (src)
269 *dst = *src;
270 else
271 memset(dst, 0, sizeof(*dst));
272}
273
Jiang Liub5dc8e62015-04-13 14:11:24 +0800274static void x86_vector_free_irqs(struct irq_domain *domain,
275 unsigned int virq, unsigned int nr_irqs)
276{
277 struct irq_data *irq_data;
278 int i;
279
280 for (i = 0; i < nr_irqs; i++) {
281 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
282 if (irq_data && irq_data->chip_data) {
Jiang Liub5dc8e62015-04-13 14:11:24 +0800283 clear_irq_vector(virq + i, irq_data->chip_data);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800284 free_apic_chip_data(irq_data->chip_data);
Jiang Liu13315322015-04-13 14:11:56 +0800285#ifdef CONFIG_X86_IO_APIC
286 if (virq + i < nr_legacy_irqs())
Jiang Liu7f3262e2015-04-14 10:30:03 +0800287 legacy_irq_data[virq + i] = NULL;
Jiang Liu13315322015-04-13 14:11:56 +0800288#endif
Jiang Liub5dc8e62015-04-13 14:11:24 +0800289 irq_domain_reset_irq_data(irq_data);
290 }
291 }
292}
293
294static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
295 unsigned int nr_irqs, void *arg)
296{
297 struct irq_alloc_info *info = arg;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800298 struct apic_chip_data *data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800299 struct irq_data *irq_data;
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800300 int i, err, node;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800301
302 if (disable_apic)
303 return -ENXIO;
304
305 /* Currently vector allocator can't guarantee contiguous allocations */
306 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
307 return -ENOSYS;
308
Jiang Liub5dc8e62015-04-13 14:11:24 +0800309 for (i = 0; i < nr_irqs; i++) {
310 irq_data = irq_domain_get_irq_data(domain, virq + i);
311 BUG_ON(!irq_data);
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800312 node = irq_data_get_node(irq_data);
Jiang Liu13315322015-04-13 14:11:56 +0800313#ifdef CONFIG_X86_IO_APIC
Jiang Liu7f3262e2015-04-14 10:30:03 +0800314 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
315 data = legacy_irq_data[virq + i];
Jiang Liu13315322015-04-13 14:11:56 +0800316 else
317#endif
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800318 data = alloc_apic_chip_data(node);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800319 if (!data) {
Jiang Liub5dc8e62015-04-13 14:11:24 +0800320 err = -ENOMEM;
321 goto error;
322 }
323
324 irq_data->chip = &lapic_controller;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800325 irq_data->chip_data = data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800326 irq_data->hwirq = virq + i;
Jiang Liu5f2dbbc2015-06-01 16:05:14 +0800327 err = assign_irq_vector_policy(virq, node, data, info);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800328 if (err)
329 goto error;
330 }
331
332 return 0;
333
334error:
335 x86_vector_free_irqs(domain, virq, i + 1);
336 return err;
337}
338
Thomas Gleixnereb18cf52015-05-05 11:10:11 +0200339static const struct irq_domain_ops x86_vector_domain_ops = {
340 .alloc = x86_vector_alloc_irqs,
341 .free = x86_vector_free_irqs,
Jiang Liub5dc8e62015-04-13 14:11:24 +0800342};
343
Jiang Liu11d686e2014-10-27 16:12:05 +0800344int __init arch_probe_nr_irqs(void)
345{
346 int nr;
347
348 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
349 nr_irqs = NR_VECTORS * nr_cpu_ids;
350
351 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
352#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
353 /*
354 * for MSI and HT dyn irq
355 */
356 if (gsi_top <= NR_IRQS_LEGACY)
357 nr += 8 * nr_cpu_ids;
358 else
359 nr += gsi_top * 16;
360#endif
361 if (nr < nr_irqs)
362 nr_irqs = nr;
363
364 return nr_legacy_irqs();
365}
366
Jiang Liu13315322015-04-13 14:11:56 +0800367#ifdef CONFIG_X86_IO_APIC
368static void init_legacy_irqs(void)
369{
370 int i, node = cpu_to_node(0);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800371 struct apic_chip_data *data;
Jiang Liu13315322015-04-13 14:11:56 +0800372
373 /*
374 * For legacy IRQ's, start with assigning irq0 to irq15 to
Ingo Molnar191a66352015-05-11 16:05:09 +0200375 * ISA_IRQ_VECTOR(i) for all cpu's.
Jiang Liu13315322015-04-13 14:11:56 +0800376 */
377 for (i = 0; i < nr_legacy_irqs(); i++) {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800378 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
379 BUG_ON(!data);
Ingo Molnar191a66352015-05-11 16:05:09 +0200380
381 data->cfg.vector = ISA_IRQ_VECTOR(i);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800382 cpumask_setall(data->domain);
383 irq_set_chip_data(i, data);
Jiang Liu13315322015-04-13 14:11:56 +0800384 }
385}
386#else
387static void init_legacy_irqs(void) { }
388#endif
389
Jiang Liu11d686e2014-10-27 16:12:05 +0800390int __init arch_early_irq_init(void)
391{
Jiang Liu13315322015-04-13 14:11:56 +0800392 init_legacy_irqs();
393
Jiang Liub5dc8e62015-04-13 14:11:24 +0800394 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
395 NULL);
396 BUG_ON(x86_vector_domain == NULL);
397 irq_set_default_host(x86_vector_domain);
398
Jiang Liu52f518a2015-04-13 14:11:35 +0800399 arch_init_msi_domain(x86_vector_domain);
Jiang Liu49e07d82015-04-13 14:11:43 +0800400 arch_init_htirq_domain(x86_vector_domain);
Jiang Liu52f518a2015-04-13 14:11:35 +0800401
Jiang Liuf7fa7ae2015-04-14 10:30:10 +0800402 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
403
Jiang Liu11d686e2014-10-27 16:12:05 +0800404 return arch_early_ioapic_init();
405}
406
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000407/* Initialize vector_irq on a new cpu */
Jiang Liu74afab72014-10-27 16:12:00 +0800408static void __setup_vector_irq(int cpu)
409{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800410 struct apic_chip_data *data;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000411 struct irq_desc *desc;
412 int irq, vector;
Jiang Liu74afab72014-10-27 16:12:00 +0800413
Jiang Liu74afab72014-10-27 16:12:00 +0800414 /* Mark the inuse vectors */
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000415 for_each_irq_desc(irq, desc) {
416 struct irq_data *idata = irq_desc_get_irq_data(desc);
Jiang Liu74afab72014-10-27 16:12:00 +0800417
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000418 data = apic_chip_data(idata);
419 if (!data || !cpumask_test_cpu(cpu, data->domain))
Jiang Liu74afab72014-10-27 16:12:00 +0800420 continue;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800421 vector = data->cfg.vector;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000422 per_cpu(vector_irq, cpu)[vector] = desc;
Jiang Liu74afab72014-10-27 16:12:00 +0800423 }
424 /* Mark the free vectors */
425 for (vector = 0; vector < NR_VECTORS; ++vector) {
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000426 desc = per_cpu(vector_irq, cpu)[vector];
427 if (IS_ERR_OR_NULL(desc))
Jiang Liu74afab72014-10-27 16:12:00 +0800428 continue;
429
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000430 data = apic_chip_data(irq_desc_get_irq_data(desc));
Jiang Liu7f3262e2015-04-14 10:30:03 +0800431 if (!cpumask_test_cpu(cpu, data->domain))
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000432 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
Jiang Liu74afab72014-10-27 16:12:00 +0800433 }
Jiang Liu74afab72014-10-27 16:12:00 +0800434}
435
436/*
Thomas Gleixner5a3f75e2015-07-05 17:12:32 +0000437 * Setup the vector to irq mappings. Must be called with vector_lock held.
Jiang Liu74afab72014-10-27 16:12:00 +0800438 */
439void setup_vector_irq(int cpu)
440{
441 int irq;
442
Thomas Gleixner5a3f75e2015-07-05 17:12:32 +0000443 lockdep_assert_held(&vector_lock);
Jiang Liu74afab72014-10-27 16:12:00 +0800444 /*
445 * On most of the platforms, legacy PIC delivers the interrupts on the
446 * boot cpu. But there are certain platforms where PIC interrupts are
447 * delivered to multiple cpu's. If the legacy IRQ is handled by the
448 * legacy PIC, for the new cpu that is coming online, setup the static
449 * legacy vector to irq mapping:
450 */
451 for (irq = 0; irq < nr_legacy_irqs(); irq++)
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000452 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
Jiang Liu74afab72014-10-27 16:12:00 +0800453
454 __setup_vector_irq(cpu);
455}
456
Jiang Liu7f3262e2015-04-14 10:30:03 +0800457static int apic_retrigger_irq(struct irq_data *irq_data)
Jiang Liu74afab72014-10-27 16:12:00 +0800458{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800459 struct apic_chip_data *data = apic_chip_data(irq_data);
Jiang Liu74afab72014-10-27 16:12:00 +0800460 unsigned long flags;
461 int cpu;
462
463 raw_spin_lock_irqsave(&vector_lock, flags);
Jiang Liu7f3262e2015-04-14 10:30:03 +0800464 cpu = cpumask_first_and(data->domain, cpu_online_mask);
465 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800466 raw_spin_unlock_irqrestore(&vector_lock, flags);
467
468 return 1;
469}
470
471void apic_ack_edge(struct irq_data *data)
472{
Jiang Liua9786092014-10-27 16:12:07 +0800473 irq_complete_move(irqd_cfg(data));
Jiang Liu74afab72014-10-27 16:12:00 +0800474 irq_move_irq(data);
475 ack_APIC_irq();
476}
477
Jiang Liu68f9f442015-04-14 10:30:01 +0800478static int apic_set_affinity(struct irq_data *irq_data,
479 const struct cpumask *dest, bool force)
Jiang Liub5dc8e62015-04-13 14:11:24 +0800480{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800481 struct apic_chip_data *data = irq_data->chip_data;
Jiang Liub5dc8e62015-04-13 14:11:24 +0800482 int err, irq = irq_data->irq;
483
484 if (!config_enabled(CONFIG_SMP))
485 return -EPERM;
486
487 if (!cpumask_intersects(dest, cpu_online_mask))
488 return -EINVAL;
489
Jiang Liu7f3262e2015-04-14 10:30:03 +0800490 err = assign_irq_vector(irq, data, dest);
Jiang Liub5dc8e62015-04-13 14:11:24 +0800491 if (err) {
492 struct irq_data *top = irq_get_irq_data(irq);
493
Jiang Liuc149e4c2015-06-03 11:46:22 +0800494 if (assign_irq_vector(irq, data,
495 irq_data_get_affinity_mask(top)))
Jiang Liub5dc8e62015-04-13 14:11:24 +0800496 pr_err("Failed to recover vector for irq %d\n", irq);
497 return err;
498 }
499
500 return IRQ_SET_MASK_OK;
501}
502
503static struct irq_chip lapic_controller = {
504 .irq_ack = apic_ack_edge,
Jiang Liu68f9f442015-04-14 10:30:01 +0800505 .irq_set_affinity = apic_set_affinity,
Jiang Liub5dc8e62015-04-13 14:11:24 +0800506 .irq_retrigger = apic_retrigger_irq,
507};
508
Jiang Liu74afab72014-10-27 16:12:00 +0800509#ifdef CONFIG_SMP
Jiang Liu7f3262e2015-04-14 10:30:03 +0800510static void __send_cleanup_vector(struct apic_chip_data *data)
Jiang Liu74afab72014-10-27 16:12:00 +0800511{
512 cpumask_var_t cleanup_mask;
513
514 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
515 unsigned int i;
516
Jiang Liu7f3262e2015-04-14 10:30:03 +0800517 for_each_cpu_and(i, data->old_domain, cpu_online_mask)
Jiang Liu74afab72014-10-27 16:12:00 +0800518 apic->send_IPI_mask(cpumask_of(i),
519 IRQ_MOVE_CLEANUP_VECTOR);
520 } else {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800521 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
Jiang Liu74afab72014-10-27 16:12:00 +0800522 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
523 free_cpumask_var(cleanup_mask);
524 }
Jiang Liu7f3262e2015-04-14 10:30:03 +0800525 data->move_in_progress = 0;
Jiang Liu74afab72014-10-27 16:12:00 +0800526}
527
Jiang Liuc6c20022015-04-14 10:30:02 +0800528void send_cleanup_vector(struct irq_cfg *cfg)
529{
Jiang Liu7f3262e2015-04-14 10:30:03 +0800530 struct apic_chip_data *data;
531
532 data = container_of(cfg, struct apic_chip_data, cfg);
533 if (data->move_in_progress)
534 __send_cleanup_vector(data);
Jiang Liuc6c20022015-04-14 10:30:02 +0800535}
536
Jiang Liu74afab72014-10-27 16:12:00 +0800537asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
538{
539 unsigned vector, me;
540
Thomas Gleixner6af7faf2015-05-15 15:48:25 +0200541 entering_ack_irq();
Jiang Liu74afab72014-10-27 16:12:00 +0800542
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000543 /* Prevent vectors vanishing under us */
544 raw_spin_lock(&vector_lock);
545
Jiang Liu74afab72014-10-27 16:12:00 +0800546 me = smp_processor_id();
547 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
Jiang Liu7f3262e2015-04-14 10:30:03 +0800548 struct apic_chip_data *data;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000549 struct irq_desc *desc;
550 unsigned int irr;
Jiang Liu74afab72014-10-27 16:12:00 +0800551
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000552 retry:
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000553 desc = __this_cpu_read(vector_irq[vector]);
554 if (IS_ERR_OR_NULL(desc))
Jiang Liu74afab72014-10-27 16:12:00 +0800555 continue;
556
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000557 if (!raw_spin_trylock(&desc->lock)) {
558 raw_spin_unlock(&vector_lock);
559 cpu_relax();
560 raw_spin_lock(&vector_lock);
561 goto retry;
562 }
563
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000564 data = apic_chip_data(irq_desc_get_irq_data(desc));
Jiang Liu7f3262e2015-04-14 10:30:03 +0800565 if (!data)
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000566 goto unlock;
Thomas Gleixnera782a7e2015-08-02 20:38:27 +0000567
Jiang Liu74afab72014-10-27 16:12:00 +0800568 /*
569 * Check if the irq migration is in progress. If so, we
570 * haven't received the cleanup request yet for this irq.
571 */
Jiang Liu7f3262e2015-04-14 10:30:03 +0800572 if (data->move_in_progress)
Jiang Liu74afab72014-10-27 16:12:00 +0800573 goto unlock;
574
Jiang Liu7f3262e2015-04-14 10:30:03 +0800575 if (vector == data->cfg.vector &&
576 cpumask_test_cpu(me, data->domain))
Jiang Liu74afab72014-10-27 16:12:00 +0800577 goto unlock;
578
579 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
580 /*
581 * Check if the vector that needs to be cleanedup is
582 * registered at the cpu's IRR. If so, then this is not
583 * the best time to clean it up. Lets clean it up in the
584 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
585 * to myself.
586 */
587 if (irr & (1 << (vector % 32))) {
588 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
589 goto unlock;
590 }
Thomas Gleixner7276c6a2015-08-02 20:38:25 +0000591 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
Jiang Liu74afab72014-10-27 16:12:00 +0800592unlock:
593 raw_spin_unlock(&desc->lock);
594 }
595
Thomas Gleixnerdf54c492015-08-02 20:38:23 +0000596 raw_spin_unlock(&vector_lock);
597
Thomas Gleixner6af7faf2015-05-15 15:48:25 +0200598 exiting_irq();
Jiang Liu74afab72014-10-27 16:12:00 +0800599}
600
601static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
602{
603 unsigned me;
Jiang Liu7f3262e2015-04-14 10:30:03 +0800604 struct apic_chip_data *data;
Jiang Liu74afab72014-10-27 16:12:00 +0800605
Jiang Liu7f3262e2015-04-14 10:30:03 +0800606 data = container_of(cfg, struct apic_chip_data, cfg);
607 if (likely(!data->move_in_progress))
Jiang Liu74afab72014-10-27 16:12:00 +0800608 return;
609
610 me = smp_processor_id();
Jiang Liu7f3262e2015-04-14 10:30:03 +0800611 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
612 __send_cleanup_vector(data);
Jiang Liu74afab72014-10-27 16:12:00 +0800613}
614
615void irq_complete_move(struct irq_cfg *cfg)
616{
617 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
618}
619
620void irq_force_complete_move(int irq)
621{
622 struct irq_cfg *cfg = irq_cfg(irq);
623
Jiang Liu7f3262e2015-04-14 10:30:03 +0800624 if (cfg)
625 __irq_complete_move(cfg, cfg->vector);
Jiang Liu74afab72014-10-27 16:12:00 +0800626}
Jiang Liu74afab72014-10-27 16:12:00 +0800627#endif
628
Jiang Liu74afab72014-10-27 16:12:00 +0800629static void __init print_APIC_field(int base)
630{
631 int i;
632
633 printk(KERN_DEBUG);
634
635 for (i = 0; i < 8; i++)
636 pr_cont("%08x", apic_read(base + i*0x10));
637
638 pr_cont("\n");
639}
640
641static void __init print_local_APIC(void *dummy)
642{
643 unsigned int i, v, ver, maxlvt;
644 u64 icr;
645
Jiang Liu849d3562014-10-27 16:12:01 +0800646 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
647 smp_processor_id(), hard_smp_processor_id());
Jiang Liu74afab72014-10-27 16:12:00 +0800648 v = apic_read(APIC_ID);
Jiang Liu849d3562014-10-27 16:12:01 +0800649 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
Jiang Liu74afab72014-10-27 16:12:00 +0800650 v = apic_read(APIC_LVR);
Jiang Liu849d3562014-10-27 16:12:01 +0800651 pr_info("... APIC VERSION: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800652 ver = GET_APIC_VERSION(v);
653 maxlvt = lapic_get_maxlvt();
654
655 v = apic_read(APIC_TASKPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800656 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
Jiang Liu74afab72014-10-27 16:12:00 +0800657
658 /* !82489DX */
659 if (APIC_INTEGRATED(ver)) {
660 if (!APIC_XAPIC(ver)) {
661 v = apic_read(APIC_ARBPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800662 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
663 v, v & APIC_ARBPRI_MASK);
Jiang Liu74afab72014-10-27 16:12:00 +0800664 }
665 v = apic_read(APIC_PROCPRI);
Jiang Liu849d3562014-10-27 16:12:01 +0800666 pr_debug("... APIC PROCPRI: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800667 }
668
669 /*
670 * Remote read supported only in the 82489DX and local APIC for
671 * Pentium processors.
672 */
673 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
674 v = apic_read(APIC_RRR);
Jiang Liu849d3562014-10-27 16:12:01 +0800675 pr_debug("... APIC RRR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800676 }
677
678 v = apic_read(APIC_LDR);
Jiang Liu849d3562014-10-27 16:12:01 +0800679 pr_debug("... APIC LDR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800680 if (!x2apic_enabled()) {
681 v = apic_read(APIC_DFR);
Jiang Liu849d3562014-10-27 16:12:01 +0800682 pr_debug("... APIC DFR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800683 }
684 v = apic_read(APIC_SPIV);
Jiang Liu849d3562014-10-27 16:12:01 +0800685 pr_debug("... APIC SPIV: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800686
Jiang Liu849d3562014-10-27 16:12:01 +0800687 pr_debug("... APIC ISR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800688 print_APIC_field(APIC_ISR);
Jiang Liu849d3562014-10-27 16:12:01 +0800689 pr_debug("... APIC TMR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800690 print_APIC_field(APIC_TMR);
Jiang Liu849d3562014-10-27 16:12:01 +0800691 pr_debug("... APIC IRR field:\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800692 print_APIC_field(APIC_IRR);
693
694 /* !82489DX */
695 if (APIC_INTEGRATED(ver)) {
696 /* Due to the Pentium erratum 3AP. */
697 if (maxlvt > 3)
698 apic_write(APIC_ESR, 0);
699
700 v = apic_read(APIC_ESR);
Jiang Liu849d3562014-10-27 16:12:01 +0800701 pr_debug("... APIC ESR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800702 }
703
704 icr = apic_icr_read();
Jiang Liu849d3562014-10-27 16:12:01 +0800705 pr_debug("... APIC ICR: %08x\n", (u32)icr);
706 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
Jiang Liu74afab72014-10-27 16:12:00 +0800707
708 v = apic_read(APIC_LVTT);
Jiang Liu849d3562014-10-27 16:12:01 +0800709 pr_debug("... APIC LVTT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800710
711 if (maxlvt > 3) {
712 /* PC is LVT#4. */
713 v = apic_read(APIC_LVTPC);
Jiang Liu849d3562014-10-27 16:12:01 +0800714 pr_debug("... APIC LVTPC: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800715 }
716 v = apic_read(APIC_LVT0);
Jiang Liu849d3562014-10-27 16:12:01 +0800717 pr_debug("... APIC LVT0: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800718 v = apic_read(APIC_LVT1);
Jiang Liu849d3562014-10-27 16:12:01 +0800719 pr_debug("... APIC LVT1: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800720
721 if (maxlvt > 2) {
722 /* ERR is LVT#3. */
723 v = apic_read(APIC_LVTERR);
Jiang Liu849d3562014-10-27 16:12:01 +0800724 pr_debug("... APIC LVTERR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800725 }
726
727 v = apic_read(APIC_TMICT);
Jiang Liu849d3562014-10-27 16:12:01 +0800728 pr_debug("... APIC TMICT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800729 v = apic_read(APIC_TMCCT);
Jiang Liu849d3562014-10-27 16:12:01 +0800730 pr_debug("... APIC TMCCT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800731 v = apic_read(APIC_TDCR);
Jiang Liu849d3562014-10-27 16:12:01 +0800732 pr_debug("... APIC TDCR: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800733
734 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
735 v = apic_read(APIC_EFEAT);
736 maxlvt = (v >> 16) & 0xff;
Jiang Liu849d3562014-10-27 16:12:01 +0800737 pr_debug("... APIC EFEAT: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800738 v = apic_read(APIC_ECTRL);
Jiang Liu849d3562014-10-27 16:12:01 +0800739 pr_debug("... APIC ECTRL: %08x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800740 for (i = 0; i < maxlvt; i++) {
741 v = apic_read(APIC_EILVTn(i));
Jiang Liu849d3562014-10-27 16:12:01 +0800742 pr_debug("... APIC EILVT%d: %08x\n", i, v);
Jiang Liu74afab72014-10-27 16:12:00 +0800743 }
744 }
745 pr_cont("\n");
746}
747
748static void __init print_local_APICs(int maxcpu)
749{
750 int cpu;
751
752 if (!maxcpu)
753 return;
754
755 preempt_disable();
756 for_each_online_cpu(cpu) {
757 if (cpu >= maxcpu)
758 break;
759 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
760 }
761 preempt_enable();
762}
763
764static void __init print_PIC(void)
765{
766 unsigned int v;
767 unsigned long flags;
768
769 if (!nr_legacy_irqs())
770 return;
771
Jiang Liu849d3562014-10-27 16:12:01 +0800772 pr_debug("\nprinting PIC contents\n");
Jiang Liu74afab72014-10-27 16:12:00 +0800773
774 raw_spin_lock_irqsave(&i8259A_lock, flags);
775
776 v = inb(0xa1) << 8 | inb(0x21);
Jiang Liu849d3562014-10-27 16:12:01 +0800777 pr_debug("... PIC IMR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800778
779 v = inb(0xa0) << 8 | inb(0x20);
Jiang Liu849d3562014-10-27 16:12:01 +0800780 pr_debug("... PIC IRR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800781
782 outb(0x0b, 0xa0);
783 outb(0x0b, 0x20);
784 v = inb(0xa0) << 8 | inb(0x20);
785 outb(0x0a, 0xa0);
786 outb(0x0a, 0x20);
787
788 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
789
Jiang Liu849d3562014-10-27 16:12:01 +0800790 pr_debug("... PIC ISR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800791
792 v = inb(0x4d1) << 8 | inb(0x4d0);
Jiang Liu849d3562014-10-27 16:12:01 +0800793 pr_debug("... PIC ELCR: %04x\n", v);
Jiang Liu74afab72014-10-27 16:12:00 +0800794}
795
796static int show_lapic __initdata = 1;
797static __init int setup_show_lapic(char *arg)
798{
799 int num = -1;
800
801 if (strcmp(arg, "all") == 0) {
802 show_lapic = CONFIG_NR_CPUS;
803 } else {
804 get_option(&arg, &num);
805 if (num >= 0)
806 show_lapic = num;
807 }
808
809 return 1;
810}
811__setup("show_lapic=", setup_show_lapic);
812
813static int __init print_ICs(void)
814{
815 if (apic_verbosity == APIC_QUIET)
816 return 0;
817
818 print_PIC();
819
820 /* don't print out if apic is not there */
821 if (!cpu_has_apic && !apic_from_smp_config())
822 return 0;
823
824 print_local_APICs(show_lapic);
825 print_IO_APICs();
826
827 return 0;
828}
829
830late_initcall(print_ICs);