Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014, 2015 Red Hat. |
Dave Airlie | 3263d93 | 2015-04-20 11:02:39 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 9 | * the Software is furnished to do so, subject to the following conditions: |
Dave Airlie | 3263d93 | 2015-04-20 11:02:39 +1000 | [diff] [blame] | 10 | * |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
Dave Airlie | 3263d93 | 2015-04-20 11:02:39 +1000 | [diff] [blame] | 14 | * |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 23 | #ifndef VIRGL_PROTOCOL_H |
| 24 | #define VIRGL_PROTOCOL_H |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 25 | |
Gert Wollny | d5efa76 | 2018-11-06 12:42:11 +0100 | [diff] [blame] | 26 | #include <stdint.h> |
| 27 | |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 28 | #define VIRGL_QUERY_STATE_NEW 0 |
| 29 | #define VIRGL_QUERY_STATE_DONE 1 |
| 30 | #define VIRGL_QUERY_STATE_WAIT_HOST 2 |
| 31 | |
| 32 | struct virgl_host_query_state { |
| 33 | uint32_t query_state; |
| 34 | uint32_t result_size; |
| 35 | uint64_t result; |
| 36 | }; |
| 37 | |
Rohan Garg | f390c4d | 2021-02-25 18:13:40 +0100 | [diff] [blame] | 38 | struct virgl_memory_info |
| 39 | { |
| 40 | uint32_t total_device_memory; /**< size of device memory, e.g. VRAM */ |
| 41 | uint32_t avail_device_memory; /**< free device memory at the moment */ |
| 42 | uint32_t total_staging_memory; /**< size of staging memory, e.g. GART */ |
| 43 | uint32_t avail_staging_memory; /**< free staging memory at the moment */ |
| 44 | uint32_t device_memory_evicted; /**< size of memory evicted (monotonic counter) */ |
| 45 | uint32_t nr_device_memory_evictions; /**< # of evictions (monotonic counter) */ |
| 46 | }; |
| 47 | |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 48 | enum virgl_object_type { |
| 49 | VIRGL_OBJECT_NULL, |
| 50 | VIRGL_OBJECT_BLEND, |
| 51 | VIRGL_OBJECT_RASTERIZER, |
| 52 | VIRGL_OBJECT_DSA, |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 53 | VIRGL_OBJECT_SHADER, |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 54 | VIRGL_OBJECT_VERTEX_ELEMENTS, |
| 55 | VIRGL_OBJECT_SAMPLER_VIEW, |
| 56 | VIRGL_OBJECT_SAMPLER_STATE, |
| 57 | VIRGL_OBJECT_SURFACE, |
| 58 | VIRGL_OBJECT_QUERY, |
| 59 | VIRGL_OBJECT_STREAMOUT_TARGET, |
Italo Nicola | 4405172 | 2021-04-28 09:21:09 +0000 | [diff] [blame^] | 60 | VIRGL_OBJECT_MSAA_SURFACE, |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 61 | VIRGL_MAX_OBJECTS, |
| 62 | }; |
| 63 | |
| 64 | /* context cmds to be encoded in the command stream */ |
| 65 | enum virgl_context_cmd { |
| 66 | VIRGL_CCMD_NOP = 0, |
| 67 | VIRGL_CCMD_CREATE_OBJECT = 1, |
| 68 | VIRGL_CCMD_BIND_OBJECT, |
| 69 | VIRGL_CCMD_DESTROY_OBJECT, |
| 70 | VIRGL_CCMD_SET_VIEWPORT_STATE, |
| 71 | VIRGL_CCMD_SET_FRAMEBUFFER_STATE, |
| 72 | VIRGL_CCMD_SET_VERTEX_BUFFERS, |
| 73 | VIRGL_CCMD_CLEAR, |
| 74 | VIRGL_CCMD_DRAW_VBO, |
| 75 | VIRGL_CCMD_RESOURCE_INLINE_WRITE, |
| 76 | VIRGL_CCMD_SET_SAMPLER_VIEWS, |
| 77 | VIRGL_CCMD_SET_INDEX_BUFFER, |
| 78 | VIRGL_CCMD_SET_CONSTANT_BUFFER, |
| 79 | VIRGL_CCMD_SET_STENCIL_REF, |
| 80 | VIRGL_CCMD_SET_BLEND_COLOR, |
| 81 | VIRGL_CCMD_SET_SCISSOR_STATE, |
| 82 | VIRGL_CCMD_BLIT, |
| 83 | VIRGL_CCMD_RESOURCE_COPY_REGION, |
| 84 | VIRGL_CCMD_BIND_SAMPLER_STATES, |
| 85 | VIRGL_CCMD_BEGIN_QUERY, |
| 86 | VIRGL_CCMD_END_QUERY, |
| 87 | VIRGL_CCMD_GET_QUERY_RESULT, |
| 88 | VIRGL_CCMD_SET_POLYGON_STIPPLE, |
| 89 | VIRGL_CCMD_SET_CLIP_STATE, |
| 90 | VIRGL_CCMD_SET_SAMPLE_MASK, |
| 91 | VIRGL_CCMD_SET_STREAMOUT_TARGETS, |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 92 | VIRGL_CCMD_SET_RENDER_CONDITION, |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 93 | VIRGL_CCMD_SET_UNIFORM_BUFFER, |
| 94 | |
| 95 | VIRGL_CCMD_SET_SUB_CTX, |
| 96 | VIRGL_CCMD_CREATE_SUB_CTX, |
| 97 | VIRGL_CCMD_DESTROY_SUB_CTX, |
Dave Airlie | 85602b3 | 2015-10-23 14:35:46 +1000 | [diff] [blame] | 98 | VIRGL_CCMD_BIND_SHADER, |
Dave Airlie | 0555483 | 2017-08-11 10:50:37 +1000 | [diff] [blame] | 99 | VIRGL_CCMD_SET_TESS_STATE, |
Erik Faye-Lund | d24ac12 | 2018-07-10 10:43:38 +0200 | [diff] [blame] | 100 | VIRGL_CCMD_SET_MIN_SAMPLES, |
Dave Airlie | 083d97f | 2018-07-17 17:44:43 +1000 | [diff] [blame] | 101 | VIRGL_CCMD_SET_SHADER_BUFFERS, |
Dave Airlie | 950de33 | 2018-07-20 08:41:30 +1000 | [diff] [blame] | 102 | VIRGL_CCMD_SET_SHADER_IMAGES, |
Dave Airlie | 8289e3f | 2018-07-18 13:11:39 +1000 | [diff] [blame] | 103 | VIRGL_CCMD_MEMORY_BARRIER, |
Dave Airlie | 38207b5 | 2018-07-30 15:22:51 +1000 | [diff] [blame] | 104 | VIRGL_CCMD_LAUNCH_GRID, |
Dave Airlie | b4965e2 | 2018-07-19 10:32:23 +1000 | [diff] [blame] | 105 | VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACH, |
Dave Airlie | aaed5a6 | 2018-08-03 13:57:08 +1000 | [diff] [blame] | 106 | VIRGL_CCMD_TEXTURE_BARRIER, |
Tomeu Vizoso | cd8c1b6 | 2018-07-19 15:41:41 +0200 | [diff] [blame] | 107 | VIRGL_CCMD_SET_ATOMIC_BUFFERS, |
Gert Wollny | d5efa76 | 2018-11-06 12:42:11 +0100 | [diff] [blame] | 108 | VIRGL_CCMD_SET_DEBUG_FLAGS, |
Dave Airlie | 3a069fc | 2018-05-21 16:37:44 +1000 | [diff] [blame] | 109 | VIRGL_CCMD_GET_QUERY_RESULT_QBO, |
Gurchetan Singh | 5a6c940 | 2018-12-03 10:42:01 -0800 | [diff] [blame] | 110 | VIRGL_CCMD_TRANSFER3D, |
| 111 | VIRGL_CCMD_END_TRANSFERS, |
Alexandros Frantzis | 1e2f540 | 2019-05-14 17:37:57 +0300 | [diff] [blame] | 112 | VIRGL_CCMD_COPY_TRANSFER3D, |
Gert Wollny | 267d486 | 2019-05-27 15:05:43 +0200 | [diff] [blame] | 113 | VIRGL_CCMD_SET_TWEAKS, |
Elie Tournier | 66b5e91 | 2020-03-20 13:47:47 +0000 | [diff] [blame] | 114 | VIRGL_CCMD_CLEAR_TEXTURE, |
Gurchetan Singh | 0c28415 | 2019-08-30 14:52:41 -0700 | [diff] [blame] | 115 | VIRGL_CCMD_PIPE_RESOURCE_CREATE, |
Chia-I Wu | f5a45fe | 2020-12-24 18:00:08 -0800 | [diff] [blame] | 116 | VIRGL_CCMD_PIPE_RESOURCE_SET_TYPE, |
Rohan Garg | f390c4d | 2021-02-25 18:13:40 +0100 | [diff] [blame] | 117 | VIRGL_CCMD_GET_MEMORY_INFO, |
Gert Wollny | fd0769a | 2021-03-04 15:41:49 +0100 | [diff] [blame] | 118 | VIRGL_CCMD_SEND_STRING_MARKER, |
Gert Wollny | d5efa76 | 2018-11-06 12:42:11 +0100 | [diff] [blame] | 119 | VIRGL_MAX_COMMANDS |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 120 | }; |
| 121 | |
Dave Airlie | 7e85c2f | 2015-03-20 14:13:19 +1000 | [diff] [blame] | 122 | /* |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 123 | 8-bit cmd headers |
| 124 | 8-bit object type |
| 125 | 16-bit length |
| 126 | */ |
| 127 | |
| 128 | #define VIRGL_CMD0(cmd, obj, len) ((cmd) | ((obj) << 8) | ((len) << 16)) |
Chia-I Wu | 7f23cf4 | 2020-07-02 11:53:04 -0700 | [diff] [blame] | 129 | #define VIRGL_CMD0_MAX_DWORDS (((1ULL << 16) - 1) / 4) * 4 |
Dave Airlie | a3a2c64 | 2014-03-31 14:07:58 +1000 | [diff] [blame] | 130 | |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 131 | /* hw specification */ |
| 132 | #define VIRGL_MAX_COLOR_BUFS 8 |
| 133 | #define VIRGL_MAX_CLIP_PLANES 8 |
| 134 | |
| 135 | #define VIRGL_OBJ_CREATE_HEADER 0 |
| 136 | #define VIRGL_OBJ_CREATE_HANDLE 1 |
| 137 | |
| 138 | #define VIRGL_OBJ_BIND_HEADER 0 |
| 139 | #define VIRGL_OBJ_BIND_HANDLE 1 |
| 140 | |
| 141 | #define VIRGL_OBJ_DESTROY_HANDLE 1 |
| 142 | |
| 143 | /* some of these defines are a specification - not used in the code */ |
| 144 | /* bit offsets for blend state object */ |
| 145 | #define VIRGL_OBJ_BLEND_SIZE (VIRGL_MAX_COLOR_BUFS + 3) |
| 146 | #define VIRGL_OBJ_BLEND_HANDLE 1 |
| 147 | #define VIRGL_OBJ_BLEND_S0 2 |
| 148 | #define VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(x) ((x) & 0x1 << 0) |
| 149 | #define VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(x) (((x) & 0x1) << 1) |
| 150 | #define VIRGL_OBJ_BLEND_S0_DITHER(x) (((x) & 0x1) << 2) |
| 151 | #define VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(x) (((x) & 0x1) << 3) |
| 152 | #define VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(x) (((x) & 0x1) << 4) |
| 153 | #define VIRGL_OBJ_BLEND_S1 3 |
| 154 | #define VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(x) (((x) & 0xf) << 0) |
| 155 | /* repeated once per number of cbufs */ |
| 156 | |
| 157 | #define VIRGL_OBJ_BLEND_S2(cbuf) (4 + (cbuf)) |
| 158 | #define VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(x) (((x) & 0x1) << 0) |
| 159 | #define VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(x) (((x) & 0x7) << 1) |
| 160 | #define VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(x) (((x) & 0x1f) << 4) |
| 161 | #define VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(x) (((x) & 0x1f) << 9) |
| 162 | #define VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(x) (((x) & 0x7) << 14) |
| 163 | #define VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(x) (((x) & 0x1f) << 17) |
| 164 | #define VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(x) (((x) & 0x1f) << 22) |
| 165 | #define VIRGL_OBJ_BLEND_S2_RT_COLORMASK(x) (((x) & 0xf) << 27) |
| 166 | |
| 167 | /* bit offsets for DSA state */ |
| 168 | #define VIRGL_OBJ_DSA_SIZE 5 |
| 169 | #define VIRGL_OBJ_DSA_HANDLE 1 |
| 170 | #define VIRGL_OBJ_DSA_S0 2 |
| 171 | #define VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(x) (((x) & 0x1) << 0) |
| 172 | #define VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(x) (((x) & 0x1) << 1) |
| 173 | #define VIRGL_OBJ_DSA_S0_DEPTH_FUNC(x) (((x) & 0x7) << 2) |
| 174 | #define VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(x) (((x) & 0x1) << 8) |
| 175 | #define VIRGL_OBJ_DSA_S0_ALPHA_FUNC(x) (((x) & 0x7) << 9) |
| 176 | #define VIRGL_OBJ_DSA_S1 3 |
| 177 | #define VIRGL_OBJ_DSA_S2 4 |
| 178 | #define VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(x) (((x) & 0x1) << 0) |
| 179 | #define VIRGL_OBJ_DSA_S1_STENCIL_FUNC(x) (((x) & 0x7) << 1) |
| 180 | #define VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(x) (((x) & 0x7) << 4) |
| 181 | #define VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(x) (((x) & 0x7) << 7) |
| 182 | #define VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(x) (((x) & 0x7) << 10) |
| 183 | #define VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(x) (((x) & 0xff) << 13) |
| 184 | #define VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(x) (((x) & 0xff) << 21) |
| 185 | #define VIRGL_OBJ_DSA_ALPHA_REF 5 |
| 186 | |
| 187 | /* offsets for rasterizer state */ |
| 188 | #define VIRGL_OBJ_RS_SIZE 9 |
| 189 | #define VIRGL_OBJ_RS_HANDLE 1 |
| 190 | #define VIRGL_OBJ_RS_S0 2 |
| 191 | #define VIRGL_OBJ_RS_S0_FLATSHADE(x) (((x) & 0x1) << 0) |
| 192 | #define VIRGL_OBJ_RS_S0_DEPTH_CLIP(x) (((x) & 0x1) << 1) |
| 193 | #define VIRGL_OBJ_RS_S0_CLIP_HALFZ(x) (((x) & 0x1) << 2) |
| 194 | #define VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(x) (((x) & 0x1) << 3) |
| 195 | #define VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(x) (((x) & 0x1) << 4) |
| 196 | #define VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(x) (((x) & 0x1) << 5) |
| 197 | #define VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(x) (((x) & 0x1) << 6) |
| 198 | #define VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(x) (((x) & 0x1) << 7) |
| 199 | #define VIRGL_OBJ_RS_S0_CULL_FACE(x) (((x) & 0x3) << 8) |
| 200 | #define VIRGL_OBJ_RS_S0_FILL_FRONT(x) (((x) & 0x3) << 10) |
| 201 | #define VIRGL_OBJ_RS_S0_FILL_BACK(x) (((x) & 0x3) << 12) |
| 202 | #define VIRGL_OBJ_RS_S0_SCISSOR(x) (((x) & 0x1) << 14) |
| 203 | #define VIRGL_OBJ_RS_S0_FRONT_CCW(x) (((x) & 0x1) << 15) |
| 204 | #define VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(x) (((x) & 0x1) << 16) |
| 205 | #define VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(x) (((x) & 0x1) << 17) |
| 206 | #define VIRGL_OBJ_RS_S0_OFFSET_LINE(x) (((x) & 0x1) << 18) |
| 207 | #define VIRGL_OBJ_RS_S0_OFFSET_POINT(x) (((x) & 0x1) << 19) |
| 208 | #define VIRGL_OBJ_RS_S0_OFFSET_TRI(x) (((x) & 0x1) << 20) |
| 209 | #define VIRGL_OBJ_RS_S0_POLY_SMOOTH(x) (((x) & 0x1) << 21) |
| 210 | #define VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(x) (((x) & 0x1) << 22) |
| 211 | #define VIRGL_OBJ_RS_S0_POINT_SMOOTH(x) (((x) & 0x1) << 23) |
| 212 | #define VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(x) (((x) & 0x1) << 24) |
| 213 | #define VIRGL_OBJ_RS_S0_MULTISAMPLE(x) (((x) & 0x1) << 25) |
| 214 | #define VIRGL_OBJ_RS_S0_LINE_SMOOTH(x) (((x) & 0x1) << 26) |
| 215 | #define VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 27) |
| 216 | #define VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28) |
| 217 | #define VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29) |
| 218 | #define VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30) |
Dave Airlie | 6f67669 | 2017-08-05 13:52:02 +1000 | [diff] [blame] | 219 | #define VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 220 | |
| 221 | #define VIRGL_OBJ_RS_POINT_SIZE 3 |
| 222 | #define VIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4 |
| 223 | #define VIRGL_OBJ_RS_S3 5 |
| 224 | |
| 225 | #define VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(x) (((x) & 0xffff) << 0) |
| 226 | #define VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(x) (((x) & 0xff) << 16) |
| 227 | #define VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(x) (((x) & 0xff) << 24) |
| 228 | #define VIRGL_OBJ_RS_LINE_WIDTH 6 |
| 229 | #define VIRGL_OBJ_RS_OFFSET_UNITS 7 |
| 230 | #define VIRGL_OBJ_RS_OFFSET_SCALE 8 |
| 231 | #define VIRGL_OBJ_RS_OFFSET_CLAMP 9 |
| 232 | |
| 233 | #define VIRGL_OBJ_CLEAR_SIZE 8 |
| 234 | #define VIRGL_OBJ_CLEAR_BUFFERS 1 |
| 235 | #define VIRGL_OBJ_CLEAR_COLOR_0 2 /* color is 4 * u32/f32/i32 */ |
| 236 | #define VIRGL_OBJ_CLEAR_COLOR_1 3 |
| 237 | #define VIRGL_OBJ_CLEAR_COLOR_2 4 |
| 238 | #define VIRGL_OBJ_CLEAR_COLOR_3 5 |
| 239 | #define VIRGL_OBJ_CLEAR_DEPTH_0 6 /* depth is a double precision float */ |
| 240 | #define VIRGL_OBJ_CLEAR_DEPTH_1 7 |
| 241 | #define VIRGL_OBJ_CLEAR_STENCIL 8 |
| 242 | |
| 243 | /* shader object */ |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 244 | #define VIRGL_OBJ_SHADER_HDR_SIZE(nso) (5 + ((nso) ? (2 * nso) + 4 : 0)) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 245 | #define VIRGL_OBJ_SHADER_HANDLE 1 |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 246 | #define VIRGL_OBJ_SHADER_TYPE 2 |
| 247 | #define VIRGL_OBJ_SHADER_OFFSET 3 |
| 248 | #define VIRGL_OBJ_SHADER_OFFSET_VAL(x) (((x) & 0x7fffffff) << 0) |
| 249 | /* start contains full length in VAL - also implies continuations */ |
| 250 | /* continuation contains offset in VAL */ |
Po-Hsien Wang | f500a29 | 2018-11-28 14:24:29 -0800 | [diff] [blame] | 251 | #define VIRGL_OBJ_SHADER_OFFSET_CONT (0x1u << 31) |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 252 | #define VIRGL_OBJ_SHADER_NUM_TOKENS 4 |
| 253 | #define VIRGL_OBJ_SHADER_SO_NUM_OUTPUTS 5 |
| 254 | #define VIRGL_OBJ_SHADER_SO_STRIDE(x) (6 + (x)) |
| 255 | #define VIRGL_OBJ_SHADER_SO_OUTPUT0(x) (10 + (x * 2)) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 256 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(x) (((x) & 0xff) << 0) |
| 257 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(x) (((x) & 0x3) << 8) |
| 258 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(x) (((x) & 0x7) << 10) |
Dave Airlie | ac97277 | 2015-03-11 17:09:03 +1000 | [diff] [blame] | 259 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(x) (((x) & 0x7) << 13) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 260 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(x) (((x) & 0xffff) << 16) |
Dave Airlie | 81b741a | 2015-10-21 14:15:50 +1000 | [diff] [blame] | 261 | #define VIRGL_OBJ_SHADER_SO_OUTPUT0_SO(x) (11 + (x * 2)) |
| 262 | #define VIRGL_OBJ_SHADER_SO_OUTPUT_STREAM(x) (((x) & 0x03) << 0) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 263 | |
| 264 | /* viewport state */ |
Dave Airlie | 0ff22a0 | 2015-03-10 14:59:44 +1000 | [diff] [blame] | 265 | #define VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports) ((6 * num_viewports) + 1) |
| 266 | #define VIRGL_SET_VIEWPORT_START_SLOT 1 |
| 267 | #define VIRGL_SET_VIEWPORT_STATE_SCALE_0(x) (2 + (x * 6)) |
| 268 | #define VIRGL_SET_VIEWPORT_STATE_SCALE_1(x) (3 + (x * 6)) |
| 269 | #define VIRGL_SET_VIEWPORT_STATE_SCALE_2(x) (4 + (x * 6)) |
| 270 | #define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_0(x) (5 + (x * 6)) |
| 271 | #define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_1(x) (6 + (x * 6)) |
| 272 | #define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_2(x) (7 + (x * 6)) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 273 | |
| 274 | /* framebuffer state */ |
| 275 | #define VIRGL_SET_FRAMEBUFFER_STATE_SIZE(nr_cbufs) (nr_cbufs + 2) |
| 276 | #define VIRGL_SET_FRAMEBUFFER_STATE_NR_CBUFS 1 |
| 277 | #define VIRGL_SET_FRAMEBUFFER_STATE_NR_ZSURF_HANDLE 2 |
| 278 | #define VIRGL_SET_FRAMEBUFFER_STATE_CBUF_HANDLE(x) ((x) + 3) |
| 279 | |
| 280 | /* vertex elements object */ |
| 281 | #define VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements) (((num_elements) * 4) + 1) |
| 282 | #define VIRGL_OBJ_VERTEX_ELEMENTS_HANDLE 1 |
| 283 | #define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_OFFSET(x) (((x) * 4) + 2) /* repeated per VE */ |
| 284 | #define VIRGL_OBJ_VERTEX_ELEMENTS_V0_INSTANCE_DIVISOR(x) (((x) * 4) + 3) |
| 285 | #define VIRGL_OBJ_VERTEX_ELEMENTS_V0_VERTEX_BUFFER_INDEX(x) (((x) * 4) + 4) |
| 286 | #define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_FORMAT(x) (((x) * 4) + 5) |
| 287 | |
| 288 | /* vertex buffers */ |
| 289 | #define VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers) ((num_buffers) * 3) |
| 290 | #define VIRGL_SET_VERTEX_BUFFER_STRIDE(x) (((x) * 3) + 1) |
| 291 | #define VIRGL_SET_VERTEX_BUFFER_OFFSET(x) (((x) * 3) + 2) |
| 292 | #define VIRGL_SET_VERTEX_BUFFER_HANDLE(x) (((x) * 3) + 3) |
| 293 | |
| 294 | /* index buffer */ |
| 295 | #define VIRGL_SET_INDEX_BUFFER_SIZE(ib) (((ib) ? 2 : 0) + 1) |
| 296 | #define VIRGL_SET_INDEX_BUFFER_HANDLE 1 |
| 297 | #define VIRGL_SET_INDEX_BUFFER_INDEX_SIZE 2 /* only if sending an IB handle */ |
| 298 | #define VIRGL_SET_INDEX_BUFFER_OFFSET 3 /* only if sending an IB handle */ |
| 299 | |
| 300 | /* constant buffer */ |
| 301 | #define VIRGL_SET_CONSTANT_BUFFER_SHADER_TYPE 1 |
| 302 | #define VIRGL_SET_CONSTANT_BUFFER_INDEX 2 |
| 303 | #define VIRGL_SET_CONSTANT_BUFFER_DATA_START 3 |
| 304 | |
| 305 | #define VIRGL_SET_UNIFORM_BUFFER_SIZE 5 |
| 306 | #define VIRGL_SET_UNIFORM_BUFFER_SHADER_TYPE 1 |
| 307 | #define VIRGL_SET_UNIFORM_BUFFER_INDEX 2 |
| 308 | #define VIRGL_SET_UNIFORM_BUFFER_OFFSET 3 |
| 309 | #define VIRGL_SET_UNIFORM_BUFFER_LENGTH 4 |
| 310 | #define VIRGL_SET_UNIFORM_BUFFER_RES_HANDLE 5 |
| 311 | |
| 312 | /* draw VBO */ |
Dave Airlie | 9259bc7 | 2015-03-19 10:16:16 +1000 | [diff] [blame] | 313 | #define VIRGL_DRAW_VBO_SIZE 12 |
Dave Airlie | 9485f7e | 2017-08-05 13:39:25 +1000 | [diff] [blame] | 314 | #define VIRGL_DRAW_VBO_SIZE_TESS 14 |
| 315 | #define VIRGL_DRAW_VBO_SIZE_INDIRECT 20 |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 316 | #define VIRGL_DRAW_VBO_START 1 |
| 317 | #define VIRGL_DRAW_VBO_COUNT 2 |
| 318 | #define VIRGL_DRAW_VBO_MODE 3 |
| 319 | #define VIRGL_DRAW_VBO_INDEXED 4 |
| 320 | #define VIRGL_DRAW_VBO_INSTANCE_COUNT 5 |
| 321 | #define VIRGL_DRAW_VBO_INDEX_BIAS 6 |
| 322 | #define VIRGL_DRAW_VBO_START_INSTANCE 7 |
| 323 | #define VIRGL_DRAW_VBO_PRIMITIVE_RESTART 8 |
| 324 | #define VIRGL_DRAW_VBO_RESTART_INDEX 9 |
| 325 | #define VIRGL_DRAW_VBO_MIN_INDEX 10 |
| 326 | #define VIRGL_DRAW_VBO_MAX_INDEX 11 |
Dave Airlie | 9259bc7 | 2015-03-19 10:16:16 +1000 | [diff] [blame] | 327 | #define VIRGL_DRAW_VBO_COUNT_FROM_SO 12 |
Dave Airlie | 9485f7e | 2017-08-05 13:39:25 +1000 | [diff] [blame] | 328 | /* tess packet */ |
| 329 | #define VIRGL_DRAW_VBO_VERTICES_PER_PATCH 13 |
| 330 | #define VIRGL_DRAW_VBO_DRAWID 14 |
| 331 | /* indirect packet */ |
| 332 | #define VIRGL_DRAW_VBO_INDIRECT_HANDLE 15 |
| 333 | #define VIRGL_DRAW_VBO_INDIRECT_OFFSET 16 |
| 334 | #define VIRGL_DRAW_VBO_INDIRECT_STRIDE 17 |
| 335 | #define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18 |
| 336 | #define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19 |
| 337 | #define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20 |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 338 | |
| 339 | /* create surface */ |
| 340 | #define VIRGL_OBJ_SURFACE_SIZE 5 |
| 341 | #define VIRGL_OBJ_SURFACE_HANDLE 1 |
| 342 | #define VIRGL_OBJ_SURFACE_RES_HANDLE 2 |
| 343 | #define VIRGL_OBJ_SURFACE_FORMAT 3 |
| 344 | #define VIRGL_OBJ_SURFACE_BUFFER_FIRST_ELEMENT 4 |
| 345 | #define VIRGL_OBJ_SURFACE_BUFFER_LAST_ELEMENT 5 |
| 346 | #define VIRGL_OBJ_SURFACE_TEXTURE_LEVEL 4 |
| 347 | #define VIRGL_OBJ_SURFACE_TEXTURE_LAYERS 5 |
| 348 | |
Italo Nicola | 4405172 | 2021-04-28 09:21:09 +0000 | [diff] [blame^] | 349 | /* create surface with implicit MSAA support (for EXT_multisample_render_to_texture) */ |
| 350 | #define VIRGL_OBJ_MSAA_SURFACE_SIZE (VIRGL_OBJ_SURFACE_SIZE + 1) |
| 351 | #define VIRGL_OBJ_SURFACE_SAMPLE_COUNT 6 |
| 352 | |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 353 | /* create streamout target */ |
| 354 | #define VIRGL_OBJ_STREAMOUT_SIZE 4 |
| 355 | #define VIRGL_OBJ_STREAMOUT_HANDLE 1 |
| 356 | #define VIRGL_OBJ_STREAMOUT_RES_HANDLE 2 |
| 357 | #define VIRGL_OBJ_STREAMOUT_BUFFER_OFFSET 3 |
| 358 | #define VIRGL_OBJ_STREAMOUT_BUFFER_SIZE 4 |
| 359 | |
| 360 | /* sampler state */ |
| 361 | #define VIRGL_OBJ_SAMPLER_STATE_SIZE 9 |
| 362 | #define VIRGL_OBJ_SAMPLER_STATE_HANDLE 1 |
| 363 | #define VIRGL_OBJ_SAMPLER_STATE_S0 2 |
| 364 | #define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(x) (((x) & 0x7) << 0) |
| 365 | #define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(x) (((x) & 0x7) << 3) |
| 366 | #define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(x) (((x) & 0x7) << 6) |
| 367 | #define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(x) (((x) & 0x3) << 9) |
| 368 | #define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(x) (((x) & 0x3) << 11) |
| 369 | #define VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13) |
| 370 | #define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15) |
| 371 | #define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16) |
Stéphane Marchesin | a6a51a2 | 2018-03-16 19:15:06 -0700 | [diff] [blame] | 372 | #define VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 373 | |
| 374 | #define VIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3 |
| 375 | #define VIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4 |
| 376 | #define VIRGL_OBJ_SAMPLER_STATE_MAX_LOD 5 |
| 377 | #define VIRGL_OBJ_SAMPLER_STATE_BORDER_COLOR(x) ((x) + 6) /* 6 - 9 */ |
| 378 | |
| 379 | |
| 380 | /* sampler view */ |
| 381 | #define VIRGL_OBJ_SAMPLER_VIEW_SIZE 6 |
| 382 | #define VIRGL_OBJ_SAMPLER_VIEW_HANDLE 1 |
| 383 | #define VIRGL_OBJ_SAMPLER_VIEW_RES_HANDLE 2 |
| 384 | #define VIRGL_OBJ_SAMPLER_VIEW_FORMAT 3 |
| 385 | #define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_FIRST_ELEMENT 4 |
| 386 | #define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_LAST_ELEMENT 5 |
| 387 | #define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LAYER 4 |
| 388 | #define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LEVEL 5 |
| 389 | #define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE 6 |
| 390 | #define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(x) (((x) & 0x7) << 0) |
| 391 | #define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(x) (((x) & 0x7) << 3) |
| 392 | #define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(x) (((x) & 0x7) << 6) |
| 393 | #define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(x) (((x) & 0x7) << 9) |
| 394 | |
| 395 | /* set sampler views */ |
| 396 | #define VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views) ((num_views) + 2) |
| 397 | #define VIRGL_SET_SAMPLER_VIEWS_SHADER_TYPE 1 |
| 398 | #define VIRGL_SET_SAMPLER_VIEWS_START_SLOT 2 |
| 399 | #define VIRGL_SET_SAMPLER_VIEWS_V0_HANDLE 3 |
| 400 | |
| 401 | /* bind sampler states */ |
| 402 | #define VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2) |
| 403 | #define VIRGL_BIND_SAMPLER_STATES_SHADER_TYPE 1 |
| 404 | #define VIRGL_BIND_SAMPLER_STATES_START_SLOT 2 |
| 405 | #define VIRGL_BIND_SAMPLER_STATES_S0_HANDLE 3 |
| 406 | |
| 407 | /* set stencil reference */ |
| 408 | #define VIRGL_SET_STENCIL_REF_SIZE 1 |
| 409 | #define VIRGL_SET_STENCIL_REF 1 |
| 410 | #define VIRGL_STENCIL_REF_VAL(f, s) ((f & 0xff) | (((s & 0xff) << 8))) |
| 411 | |
| 412 | /* set blend color */ |
| 413 | #define VIRGL_SET_BLEND_COLOR_SIZE 4 |
| 414 | #define VIRGL_SET_BLEND_COLOR(x) ((x) + 1) |
| 415 | |
| 416 | /* set scissor state */ |
Dave Airlie | 0ff22a0 | 2015-03-10 14:59:44 +1000 | [diff] [blame] | 417 | #define VIRGL_SET_SCISSOR_STATE_SIZE(x) (1 + 2 * x) |
| 418 | #define VIRGL_SET_SCISSOR_START_SLOT 1 |
| 419 | #define VIRGL_SET_SCISSOR_MINX_MINY(x) (2 + (x * 2)) |
Marc-André Lureau | 19fae10 | 2015-03-10 13:40:47 +0100 | [diff] [blame] | 420 | #define VIRGL_SET_SCISSOR_MAXX_MAXY(x) (3 + (x * 2)) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 421 | |
| 422 | /* resource copy region */ |
| 423 | #define VIRGL_CMD_RESOURCE_COPY_REGION_SIZE 13 |
| 424 | #define VIRGL_CMD_RCR_DST_RES_HANDLE 1 |
| 425 | #define VIRGL_CMD_RCR_DST_LEVEL 2 |
| 426 | #define VIRGL_CMD_RCR_DST_X 3 |
| 427 | #define VIRGL_CMD_RCR_DST_Y 4 |
| 428 | #define VIRGL_CMD_RCR_DST_Z 5 |
| 429 | #define VIRGL_CMD_RCR_SRC_RES_HANDLE 6 |
| 430 | #define VIRGL_CMD_RCR_SRC_LEVEL 7 |
| 431 | #define VIRGL_CMD_RCR_SRC_X 8 |
| 432 | #define VIRGL_CMD_RCR_SRC_Y 9 |
| 433 | #define VIRGL_CMD_RCR_SRC_Z 10 |
| 434 | #define VIRGL_CMD_RCR_SRC_W 11 |
| 435 | #define VIRGL_CMD_RCR_SRC_H 12 |
| 436 | #define VIRGL_CMD_RCR_SRC_D 13 |
| 437 | |
| 438 | /* blit */ |
| 439 | #define VIRGL_CMD_BLIT_SIZE 21 |
| 440 | #define VIRGL_CMD_BLIT_S0 1 |
| 441 | #define VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0) |
| 442 | #define VIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8) |
| 443 | #define VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10) |
Dave Airlie | 12c89d5 | 2016-03-01 15:47:34 +1000 | [diff] [blame] | 444 | #define VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11) |
| 445 | #define VIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 446 | #define VIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2 |
| 447 | #define VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3 |
| 448 | #define VIRGL_CMD_BLIT_DST_RES_HANDLE 4 |
| 449 | #define VIRGL_CMD_BLIT_DST_LEVEL 5 |
| 450 | #define VIRGL_CMD_BLIT_DST_FORMAT 6 |
| 451 | #define VIRGL_CMD_BLIT_DST_X 7 |
| 452 | #define VIRGL_CMD_BLIT_DST_Y 8 |
| 453 | #define VIRGL_CMD_BLIT_DST_Z 9 |
| 454 | #define VIRGL_CMD_BLIT_DST_W 10 |
| 455 | #define VIRGL_CMD_BLIT_DST_H 11 |
| 456 | #define VIRGL_CMD_BLIT_DST_D 12 |
| 457 | #define VIRGL_CMD_BLIT_SRC_RES_HANDLE 13 |
| 458 | #define VIRGL_CMD_BLIT_SRC_LEVEL 14 |
| 459 | #define VIRGL_CMD_BLIT_SRC_FORMAT 15 |
| 460 | #define VIRGL_CMD_BLIT_SRC_X 16 |
| 461 | #define VIRGL_CMD_BLIT_SRC_Y 17 |
| 462 | #define VIRGL_CMD_BLIT_SRC_Z 18 |
| 463 | #define VIRGL_CMD_BLIT_SRC_W 19 |
| 464 | #define VIRGL_CMD_BLIT_SRC_H 20 |
| 465 | #define VIRGL_CMD_BLIT_SRC_D 21 |
| 466 | |
| 467 | /* query object */ |
| 468 | #define VIRGL_OBJ_QUERY_SIZE 4 |
| 469 | #define VIRGL_OBJ_QUERY_HANDLE 1 |
Dave Airlie | fd81164 | 2015-10-23 11:04:01 +1000 | [diff] [blame] | 470 | #define VIRGL_OBJ_QUERY_TYPE_INDEX 2 |
| 471 | #define VIRGL_OBJ_QUERY_TYPE(x) (x & 0xffff) |
| 472 | #define VIRGL_OBJ_QUERY_INDEX(x) ((x & 0xffff) << 16) |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 473 | #define VIRGL_OBJ_QUERY_OFFSET 3 |
| 474 | #define VIRGL_OBJ_QUERY_RES_HANDLE 4 |
| 475 | |
| 476 | #define VIRGL_QUERY_BEGIN_HANDLE 1 |
| 477 | |
| 478 | #define VIRGL_QUERY_END_HANDLE 1 |
| 479 | |
Chia-I Wu | 7f23cf4 | 2020-07-02 11:53:04 -0700 | [diff] [blame] | 480 | #define VIRGL_QUERY_RESULT_SIZE 2 |
Dave Airlie | 03e3116 | 2015-02-03 13:11:42 +1000 | [diff] [blame] | 481 | #define VIRGL_QUERY_RESULT_HANDLE 1 |
| 482 | #define VIRGL_QUERY_RESULT_WAIT 2 |
| 483 | |
| 484 | /* render condition */ |
| 485 | #define VIRGL_RENDER_CONDITION_SIZE 3 |
| 486 | #define VIRGL_RENDER_CONDITION_HANDLE 1 |
| 487 | #define VIRGL_RENDER_CONDITION_CONDITION 2 |
| 488 | #define VIRGL_RENDER_CONDITION_MODE 3 |
| 489 | |
| 490 | /* resource inline write */ |
| 491 | #define VIRGL_RESOURCE_IW_RES_HANDLE 1 |
| 492 | #define VIRGL_RESOURCE_IW_LEVEL 2 |
| 493 | #define VIRGL_RESOURCE_IW_USAGE 3 |
| 494 | #define VIRGL_RESOURCE_IW_STRIDE 4 |
| 495 | #define VIRGL_RESOURCE_IW_LAYER_STRIDE 5 |
| 496 | #define VIRGL_RESOURCE_IW_X 6 |
| 497 | #define VIRGL_RESOURCE_IW_Y 7 |
| 498 | #define VIRGL_RESOURCE_IW_Z 8 |
| 499 | #define VIRGL_RESOURCE_IW_W 9 |
| 500 | #define VIRGL_RESOURCE_IW_H 10 |
| 501 | #define VIRGL_RESOURCE_IW_D 11 |
| 502 | #define VIRGL_RESOURCE_IW_DATA_START 12 |
| 503 | |
| 504 | /* set streamout targets */ |
| 505 | #define VIRGL_SET_STREAMOUT_TARGETS_APPEND_BITMASK 1 |
| 506 | #define VIRGL_SET_STREAMOUT_TARGETS_H0 2 |
| 507 | |
| 508 | /* set sample mask */ |
| 509 | #define VIRGL_SET_SAMPLE_MASK_SIZE 1 |
| 510 | #define VIRGL_SET_SAMPLE_MASK_MASK 1 |
| 511 | |
| 512 | /* set clip state */ |
| 513 | #define VIRGL_SET_CLIP_STATE_SIZE 32 |
| 514 | #define VIRGL_SET_CLIP_STATE_C0 1 |
| 515 | |
| 516 | /* polygon stipple */ |
| 517 | #define VIRGL_POLYGON_STIPPLE_SIZE 32 |
| 518 | #define VIRGL_POLYGON_STIPPLE_P0 1 |
Dave Airlie | 85602b3 | 2015-10-23 14:35:46 +1000 | [diff] [blame] | 519 | |
| 520 | #define VIRGL_BIND_SHADER_SIZE 2 |
| 521 | #define VIRGL_BIND_SHADER_HANDLE 1 |
| 522 | #define VIRGL_BIND_SHADER_TYPE 2 |
| 523 | |
Dave Airlie | 0555483 | 2017-08-11 10:50:37 +1000 | [diff] [blame] | 524 | /* tess state */ |
| 525 | #define VIRGL_TESS_STATE_SIZE 6 |
| 526 | |
Erik Faye-Lund | d24ac12 | 2018-07-10 10:43:38 +0200 | [diff] [blame] | 527 | /* set min samples */ |
| 528 | #define VIRGL_SET_MIN_SAMPLES_SIZE 1 |
| 529 | #define VIRGL_SET_MIN_SAMPLES_MASK 1 |
| 530 | |
Dave Airlie | 083d97f | 2018-07-17 17:44:43 +1000 | [diff] [blame] | 531 | /* set shader buffers */ |
| 532 | #define VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE 3 |
| 533 | #define VIRGL_SET_SHADER_BUFFER_SIZE(x) (VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE * (x)) + 2 |
| 534 | #define VIRGL_SET_SHADER_BUFFER_SHADER_TYPE 1 |
| 535 | #define VIRGL_SET_SHADER_BUFFER_START_SLOT 2 |
Dave Airlie | 519a091 | 2018-07-24 05:51:19 +1000 | [diff] [blame] | 536 | #define VIRGL_SET_SHADER_BUFFER_OFFSET(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 3) |
| 537 | #define VIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4) |
| 538 | #define VIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5) |
Dave Airlie | 083d97f | 2018-07-17 17:44:43 +1000 | [diff] [blame] | 539 | |
Dave Airlie | 950de33 | 2018-07-20 08:41:30 +1000 | [diff] [blame] | 540 | /* set shader images */ |
| 541 | #define VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5 |
| 542 | #define VIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2 |
| 543 | #define VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1 |
| 544 | #define VIRGL_SET_SHADER_IMAGE_START_SLOT 2 |
| 545 | #define VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3) |
| 546 | #define VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4) |
| 547 | #define VIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5) |
| 548 | #define VIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6) |
| 549 | #define VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7) |
| 550 | |
Dave Airlie | 8289e3f | 2018-07-18 13:11:39 +1000 | [diff] [blame] | 551 | /* memory barrier */ |
| 552 | #define VIRGL_MEMORY_BARRIER_SIZE 1 |
| 553 | #define VIRGL_MEMORY_BARRIER_FLAGS 1 |
| 554 | |
Dave Airlie | 38207b5 | 2018-07-30 15:22:51 +1000 | [diff] [blame] | 555 | /* launch grid */ |
| 556 | #define VIRGL_LAUNCH_GRID_SIZE 8 |
| 557 | #define VIRGL_LAUNCH_BLOCK_X 1 |
| 558 | #define VIRGL_LAUNCH_BLOCK_Y 2 |
| 559 | #define VIRGL_LAUNCH_BLOCK_Z 3 |
| 560 | #define VIRGL_LAUNCH_GRID_X 4 |
| 561 | #define VIRGL_LAUNCH_GRID_Y 5 |
| 562 | #define VIRGL_LAUNCH_GRID_Z 6 |
| 563 | #define VIRGL_LAUNCH_INDIRECT_HANDLE 7 |
| 564 | #define VIRGL_LAUNCH_INDIRECT_OFFSET 8 |
Dave Airlie | b4965e2 | 2018-07-19 10:32:23 +1000 | [diff] [blame] | 565 | |
| 566 | /* framebuffer state no attachment */ |
| 567 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE 2 |
| 568 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH_HEIGHT 1 |
| 569 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH(x) (x & 0xffff) |
| 570 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_HEIGHT(x) ((x >> 16) & 0xffff) |
| 571 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS_SAMPLES 2 |
| 572 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS(x) (x & 0xffff) |
| 573 | #define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SAMPLES(x) ((x >> 16) & 0xff) |
| 574 | |
Dave Airlie | aaed5a6 | 2018-08-03 13:57:08 +1000 | [diff] [blame] | 575 | /* texture barrier */ |
| 576 | #define VIRGL_TEXTURE_BARRIER_SIZE 1 |
| 577 | #define VIRGL_TEXTURE_BARRIER_FLAGS 1 |
| 578 | |
Tomeu Vizoso | cd8c1b6 | 2018-07-19 15:41:41 +0200 | [diff] [blame] | 579 | /* hw atomics */ |
| 580 | #define VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE 3 |
| 581 | #define VIRGL_SET_ATOMIC_BUFFER_SIZE(x) (VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE * (x)) + 1 |
| 582 | #define VIRGL_SET_ATOMIC_BUFFER_START_SLOT 1 |
| 583 | #define VIRGL_SET_ATOMIC_BUFFER_OFFSET(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 2) |
| 584 | #define VIRGL_SET_ATOMIC_BUFFER_LENGTH(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 3) |
| 585 | #define VIRGL_SET_ATOMIC_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 4) |
| 586 | |
Gert Wollny | d5efa76 | 2018-11-06 12:42:11 +0100 | [diff] [blame] | 587 | /* set debug flags */ |
| 588 | #define VIRGL_SET_DEBUG_FLAGS_MIN_SIZE 2 |
| 589 | #define VIRGL_SET_DEBUG_FLAGSTRING_OFFSET 1 |
| 590 | |
Dave Airlie | 3a069fc | 2018-05-21 16:37:44 +1000 | [diff] [blame] | 591 | /* query buffer object */ |
| 592 | #define VIRGL_QUERY_RESULT_QBO_SIZE 6 |
| 593 | #define VIRGL_QUERY_RESULT_QBO_HANDLE 1 |
| 594 | #define VIRGL_QUERY_RESULT_QBO_QBO_HANDLE 2 |
| 595 | #define VIRGL_QUERY_RESULT_QBO_WAIT 3 |
| 596 | #define VIRGL_QUERY_RESULT_QBO_RESULT_TYPE 4 |
| 597 | #define VIRGL_QUERY_RESULT_QBO_OFFSET 5 |
| 598 | #define VIRGL_QUERY_RESULT_QBO_INDEX 6 |
| 599 | |
Gurchetan Singh | 5a6c940 | 2018-12-03 10:42:01 -0800 | [diff] [blame] | 600 | #define VIRGL_TRANSFER_TO_HOST 1 |
| 601 | #define VIRGL_TRANSFER_FROM_HOST 2 |
| 602 | |
| 603 | /* Transfer */ |
| 604 | #define VIRGL_TRANSFER3D_SIZE 13 |
| 605 | /* The first 11 dwords are the same as VIRGL_RESOURCE_IW_* */ |
| 606 | #define VIRGL_TRANSFER3D_DATA_OFFSET 12 |
| 607 | #define VIRGL_TRANSFER3D_DIRECTION 13 |
| 608 | |
Alexandros Frantzis | 1e2f540 | 2019-05-14 17:37:57 +0300 | [diff] [blame] | 609 | /* Copy transfer */ |
| 610 | #define VIRGL_COPY_TRANSFER3D_SIZE 14 |
| 611 | /* The first 11 dwords are the same as VIRGL_RESOURCE_IW_* */ |
| 612 | #define VIRGL_COPY_TRANSFER3D_SRC_RES_HANDLE 12 |
| 613 | #define VIRGL_COPY_TRANSFER3D_SRC_RES_OFFSET 13 |
| 614 | #define VIRGL_COPY_TRANSFER3D_SYNCHRONIZED 14 |
| 615 | |
Gert Wollny | 267d486 | 2019-05-27 15:05:43 +0200 | [diff] [blame] | 616 | /* set tweak flags */ |
| 617 | #define VIRGL_SET_TWEAKS_SIZE 2 |
| 618 | #define VIRGL_SET_TWEAKS_ID 1 |
| 619 | #define VIRGL_SET_TWEAKS_VALUE 2 |
| 620 | |
Gert Wollny | 0f251aa | 2019-05-27 15:02:14 +0200 | [diff] [blame] | 621 | enum vrend_tweak_type { |
Gert Wollny | 8aee663 | 2019-05-27 15:28:51 +0200 | [diff] [blame] | 622 | virgl_tweak_gles_brga_emulate, |
Gert Wollny | 4ea1510 | 2019-05-27 15:31:47 +0200 | [diff] [blame] | 623 | virgl_tweak_gles_brga_apply_dest_swizzle, |
Gert Wollny | 33c4a18 | 2019-05-27 15:36:36 +0200 | [diff] [blame] | 624 | virgl_tweak_gles_tf3_samples_passes_multiplier, |
Gert Wollny | 0f251aa | 2019-05-27 15:02:14 +0200 | [diff] [blame] | 625 | virgl_tweak_undefined |
| 626 | }; |
| 627 | |
Elie Tournier | 66b5e91 | 2020-03-20 13:47:47 +0000 | [diff] [blame] | 628 | /* Clear texture */ |
| 629 | #define VIRGL_CLEAR_TEXTURE_SIZE 12 |
| 630 | #define VIRGL_TEXTURE_HANDLE 1 |
| 631 | #define VIRGL_TEXTURE_LEVEL 2 |
| 632 | #define VIRGL_TEXTURE_SRC_X 3 |
| 633 | #define VIRGL_TEXTURE_SRC_Y 4 |
| 634 | #define VIRGL_TEXTURE_SRC_Z 5 |
| 635 | #define VIRGL_TEXTURE_SRC_W 6 |
| 636 | #define VIRGL_TEXTURE_SRC_H 7 |
| 637 | #define VIRGL_TEXTURE_SRC_D 8 |
| 638 | #define VIRGL_TEXTURE_ARRAY_A 9 |
| 639 | #define VIRGL_TEXTURE_ARRAY_B 10 |
| 640 | #define VIRGL_TEXTURE_ARRAY_C 11 |
| 641 | #define VIRGL_TEXTURE_ARRAY_D 12 |
| 642 | |
Gurchetan Singh | 0c28415 | 2019-08-30 14:52:41 -0700 | [diff] [blame] | 643 | /* virgl create */ |
| 644 | #define VIRGL_PIPE_RES_CREATE_SIZE 11 |
| 645 | #define VIRGL_PIPE_RES_CREATE_TARGET 1 |
| 646 | #define VIRGL_PIPE_RES_CREATE_FORMAT 2 |
| 647 | #define VIRGL_PIPE_RES_CREATE_BIND 3 |
| 648 | #define VIRGL_PIPE_RES_CREATE_WIDTH 4 |
| 649 | #define VIRGL_PIPE_RES_CREATE_HEIGHT 5 |
| 650 | #define VIRGL_PIPE_RES_CREATE_DEPTH 6 |
| 651 | #define VIRGL_PIPE_RES_CREATE_ARRAY_SIZE 7 |
| 652 | #define VIRGL_PIPE_RES_CREATE_LAST_LEVEL 8 |
| 653 | #define VIRGL_PIPE_RES_CREATE_NR_SAMPLES 9 |
| 654 | #define VIRGL_PIPE_RES_CREATE_FLAGS 10 |
| 655 | #define VIRGL_PIPE_RES_CREATE_BLOB_ID 11 |
| 656 | |
Chia-I Wu | f5a45fe | 2020-12-24 18:00:08 -0800 | [diff] [blame] | 657 | /* VIRGL_CCMD_PIPE_RESOURCE_SET_TYPE */ |
| 658 | #define VIRGL_PIPE_RES_SET_TYPE_SIZE(nplanes) (8 + (nplanes) * 2) |
| 659 | #define VIRGL_PIPE_RES_SET_TYPE_RES_HANDLE 1 |
| 660 | #define VIRGL_PIPE_RES_SET_TYPE_FORMAT 2 |
| 661 | #define VIRGL_PIPE_RES_SET_TYPE_BIND 3 |
| 662 | #define VIRGL_PIPE_RES_SET_TYPE_WIDTH 4 |
| 663 | #define VIRGL_PIPE_RES_SET_TYPE_HEIGHT 5 |
| 664 | #define VIRGL_PIPE_RES_SET_TYPE_USAGE 6 |
| 665 | #define VIRGL_PIPE_RES_SET_TYPE_MODIFIER_LO 7 |
| 666 | #define VIRGL_PIPE_RES_SET_TYPE_MODIFIER_HI 8 |
| 667 | #define VIRGL_PIPE_RES_SET_TYPE_PLANE_STRIDE(plane) (9 + (plane) * 2) |
| 668 | #define VIRGL_PIPE_RES_SET_TYPE_PLANE_OFFSET(plane) (10 + (plane) * 2) |
| 669 | |
Gert Wollny | fd0769a | 2021-03-04 15:41:49 +0100 | [diff] [blame] | 670 | /* send string marker */ |
| 671 | #define VIRGL_SEND_STRING_MARKER_MIN_SIZE 2 |
| 672 | #define VIRGL_SEND_STRING_MARKER_STRING_SIZE 1 |
| 673 | #define VIRGL_SEND_STRING_MARKER_OFFSET 2 |
| 674 | |
Elie Tournier | 66b5e91 | 2020-03-20 13:47:47 +0000 | [diff] [blame] | 675 | #endif |