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bellard7d132992003-03-06 23:23:54 +00001/*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
bellard7d132992003-03-06 23:23:54 +000019 */
bellarde4533c72003-06-15 19:51:39 +000020#include "config.h"
bellard93ac68b2003-09-30 20:57:29 +000021#include "exec.h"
bellard956034d2003-04-29 20:40:53 +000022#include "disas.h"
bellard7d132992003-03-06 23:23:54 +000023
bellardfbf9eeb2004-04-25 21:21:33 +000024#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
bellard36bdbe52003-11-19 22:12:02 +000038int tb_invalidated_flag;
39
bellarddc990652003-03-19 00:00:28 +000040//#define DEBUG_EXEC
bellard9de5e442003-03-23 16:49:39 +000041//#define DEBUG_SIGNAL
bellard7d132992003-03-06 23:23:54 +000042
bellard93ac68b2003-09-30 20:57:29 +000043#if defined(TARGET_ARM) || defined(TARGET_SPARC)
bellarde4533c72003-06-15 19:51:39 +000044/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
50
bellardfbf9eeb2004-04-25 21:21:33 +000051/* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54void cpu_resume_from_signal(CPUState *env1, void *puc)
55{
56#if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58#endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64#if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69#endif
70 longjmp(env->jmp_env, 1);
71}
72
bellard7d132992003-03-06 23:23:54 +000073/* main execution loop */
74
bellarde4533c72003-06-15 19:51:39 +000075int cpu_exec(CPUState *env1)
bellard7d132992003-03-06 23:23:54 +000076{
bellarde4533c72003-06-15 19:51:39 +000077 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
bellard04369ff2003-03-20 22:33:23 +000079#ifdef reg_EAX
80 int saved_EAX;
81#endif
82#ifdef reg_ECX
83 int saved_ECX;
84#endif
85#ifdef reg_EDX
86 int saved_EDX;
87#endif
88#ifdef reg_EBX
89 int saved_EBX;
90#endif
91#ifdef reg_ESP
92 int saved_ESP;
93#endif
94#ifdef reg_EBP
95 int saved_EBP;
96#endif
97#ifdef reg_ESI
98 int saved_ESI;
99#endif
100#ifdef reg_EDI
101 int saved_EDI;
102#endif
bellard8c6939c2003-06-09 15:28:00 +0000103#ifdef __sparc__
104 int saved_i7, tmp_T0;
105#endif
bellard68a79312003-06-30 13:12:32 +0000106 int code_gen_size, ret, interrupt_request;
bellard7d132992003-03-06 23:23:54 +0000107 void (*gen_func)(void);
bellard9de5e442003-03-23 16:49:39 +0000108 TranslationBlock *tb, **ptb;
bellardc27004e2005-01-03 23:35:10 +0000109 target_ulong cs_base, pc;
110 uint8_t *tc_ptr;
bellard6dbad632003-03-16 18:05:05 +0000111 unsigned int flags;
bellard8c6939c2003-06-09 15:28:00 +0000112
bellard7d132992003-03-06 23:23:54 +0000113 /* first we save global registers */
bellardc27004e2005-01-03 23:35:10 +0000114 saved_env = env;
115 env = env1;
bellard7d132992003-03-06 23:23:54 +0000116 saved_T0 = T0;
117 saved_T1 = T1;
bellarde4533c72003-06-15 19:51:39 +0000118 saved_T2 = T2;
bellarde4533c72003-06-15 19:51:39 +0000119#ifdef __sparc__
120 /* we also save i7 because longjmp may not restore it */
121 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
122#endif
123
124#if defined(TARGET_I386)
bellard04369ff2003-03-20 22:33:23 +0000125#ifdef reg_EAX
126 saved_EAX = EAX;
bellard04369ff2003-03-20 22:33:23 +0000127#endif
128#ifdef reg_ECX
129 saved_ECX = ECX;
bellard04369ff2003-03-20 22:33:23 +0000130#endif
131#ifdef reg_EDX
132 saved_EDX = EDX;
bellard04369ff2003-03-20 22:33:23 +0000133#endif
134#ifdef reg_EBX
135 saved_EBX = EBX;
bellard04369ff2003-03-20 22:33:23 +0000136#endif
137#ifdef reg_ESP
138 saved_ESP = ESP;
bellard04369ff2003-03-20 22:33:23 +0000139#endif
140#ifdef reg_EBP
141 saved_EBP = EBP;
bellard04369ff2003-03-20 22:33:23 +0000142#endif
143#ifdef reg_ESI
144 saved_ESI = ESI;
bellard04369ff2003-03-20 22:33:23 +0000145#endif
146#ifdef reg_EDI
147 saved_EDI = EDI;
bellard04369ff2003-03-20 22:33:23 +0000148#endif
bellard0d1a29f2004-10-12 22:01:28 +0000149
150 env_to_regs();
bellard9de5e442003-03-23 16:49:39 +0000151 /* put eflags in CPU temporary format */
bellardfc2b4c42003-03-29 16:52:44 +0000152 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
153 DF = 1 - (2 * ((env->eflags >> 10) & 1));
bellard9de5e442003-03-23 16:49:39 +0000154 CC_OP = CC_OP_EFLAGS;
bellardfc2b4c42003-03-29 16:52:44 +0000155 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000156#elif defined(TARGET_ARM)
157 {
158 unsigned int psr;
159 psr = env->cpsr;
160 env->CF = (psr >> 29) & 1;
161 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
162 env->VF = (psr << 3) & 0x80000000;
bellard99c475a2005-01-31 20:45:13 +0000163 env->QF = (psr >> 27) & 1;
164 env->cpsr = psr & ~CACHED_CPSR_BITS;
bellarde4533c72003-06-15 19:51:39 +0000165 }
bellard93ac68b2003-09-30 20:57:29 +0000166#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000167#elif defined(TARGET_PPC)
bellarde4533c72003-06-15 19:51:39 +0000168#else
169#error unsupported target CPU
170#endif
bellard3fb2ded2003-06-24 13:22:59 +0000171 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000172
bellard7d132992003-03-06 23:23:54 +0000173 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000174 for(;;) {
175 if (setjmp(env->jmp_env) == 0) {
bellardee8b7022004-02-03 23:35:10 +0000176 env->current_tb = NULL;
bellard3fb2ded2003-06-24 13:22:59 +0000177 /* if an exception is pending, we execute it here */
178 if (env->exception_index >= 0) {
179 if (env->exception_index >= EXCP_INTERRUPT) {
180 /* exit request from the cpu execution loop */
181 ret = env->exception_index;
182 break;
183 } else if (env->user_mode_only) {
184 /* if user mode only, we simulate a fake exception
185 which will be hanlded outside the cpu execution
186 loop */
bellard83479e72003-06-25 16:12:37 +0000187#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000188 do_interrupt_user(env->exception_index,
189 env->exception_is_int,
190 env->error_code,
191 env->exception_next_eip);
bellard83479e72003-06-25 16:12:37 +0000192#endif
bellard3fb2ded2003-06-24 13:22:59 +0000193 ret = env->exception_index;
194 break;
195 } else {
bellard83479e72003-06-25 16:12:37 +0000196#if defined(TARGET_I386)
bellard3fb2ded2003-06-24 13:22:59 +0000197 /* simulate a real cpu exception. On i386, it can
198 trigger new exceptions, but we do not handle
199 double or triple faults yet. */
200 do_interrupt(env->exception_index,
201 env->exception_is_int,
202 env->error_code,
bellardd05e66d2003-08-20 21:34:35 +0000203 env->exception_next_eip, 0);
bellardce097762004-01-04 23:53:18 +0000204#elif defined(TARGET_PPC)
205 do_interrupt(env);
bellarde95c8d52004-09-30 22:22:08 +0000206#elif defined(TARGET_SPARC)
207 do_interrupt(env->exception_index,
bellard68016c62005-02-07 23:12:27 +0000208 env->error_code);
bellard83479e72003-06-25 16:12:37 +0000209#endif
bellard3fb2ded2003-06-24 13:22:59 +0000210 }
211 env->exception_index = -1;
bellard9de5e442003-03-23 16:49:39 +0000212 }
bellard3fb2ded2003-06-24 13:22:59 +0000213 T0 = 0; /* force lookup of first TB */
214 for(;;) {
215#ifdef __sparc__
216 /* g1 can be modified by some libc? functions */
217 tmp_T0 = T0;
218#endif
bellard68a79312003-06-30 13:12:32 +0000219 interrupt_request = env->interrupt_request;
bellard2e255c62003-08-21 23:25:21 +0000220 if (__builtin_expect(interrupt_request, 0)) {
bellard68a79312003-06-30 13:12:32 +0000221#if defined(TARGET_I386)
222 /* if hardware interrupt pending, we execute it */
223 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
bellard3f337312003-08-20 23:02:09 +0000224 (env->eflags & IF_MASK) &&
225 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
bellard68a79312003-06-30 13:12:32 +0000226 int intno;
bellardfbf9eeb2004-04-25 21:21:33 +0000227 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellarda541f292004-04-12 20:39:29 +0000228 intno = cpu_get_pic_interrupt(env);
bellardf193c792004-03-21 17:06:25 +0000229 if (loglevel & CPU_LOG_TB_IN_ASM) {
bellard68a79312003-06-30 13:12:32 +0000230 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
231 }
bellardd05e66d2003-08-20 21:34:35 +0000232 do_interrupt(intno, 0, 0, 0, 1);
bellard907a5b22003-06-30 23:18:22 +0000233 /* ensure that no TB jump will be modified as
234 the program flow was changed */
235#ifdef __sparc__
236 tmp_T0 = 0;
237#else
238 T0 = 0;
239#endif
bellard68a79312003-06-30 13:12:32 +0000240 }
bellardce097762004-01-04 23:53:18 +0000241#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000242#if 0
243 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
244 cpu_ppc_reset(env);
245 }
246#endif
247 if (msr_ee != 0) {
bellardce097762004-01-04 23:53:18 +0000248 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
bellard9fddaa02004-05-21 12:59:32 +0000249 /* Raise it */
250 env->exception_index = EXCP_EXTERNAL;
251 env->error_code = 0;
bellardce097762004-01-04 23:53:18 +0000252 do_interrupt(env);
253 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
bellard9fddaa02004-05-21 12:59:32 +0000254 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
255 /* Raise it */
256 env->exception_index = EXCP_DECR;
257 env->error_code = 0;
258 do_interrupt(env);
259 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
260 }
bellardce097762004-01-04 23:53:18 +0000261 }
bellarde95c8d52004-09-30 22:22:08 +0000262#elif defined(TARGET_SPARC)
263 if (interrupt_request & CPU_INTERRUPT_HARD) {
bellard68016c62005-02-07 23:12:27 +0000264 do_interrupt(env->interrupt_index, 0);
bellarde95c8d52004-09-30 22:22:08 +0000265 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
266 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
267 //do_interrupt(0, 0, 0, 0, 0);
268 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
269 }
bellard68a79312003-06-30 13:12:32 +0000270#endif
bellardbf3e8bf2004-02-16 21:58:54 +0000271 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
272 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
273 /* ensure that no TB jump will be modified as
274 the program flow was changed */
275#ifdef __sparc__
276 tmp_T0 = 0;
277#else
278 T0 = 0;
279#endif
280 }
bellard68a79312003-06-30 13:12:32 +0000281 if (interrupt_request & CPU_INTERRUPT_EXIT) {
282 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
283 env->exception_index = EXCP_INTERRUPT;
284 cpu_loop_exit();
285 }
bellard3fb2ded2003-06-24 13:22:59 +0000286 }
287#ifdef DEBUG_EXEC
bellardc27004e2005-01-03 23:35:10 +0000288 if ((loglevel & CPU_LOG_EXEC)) {
bellard3fb2ded2003-06-24 13:22:59 +0000289#if defined(TARGET_I386)
290 /* restore flags in standard format */
291 env->regs[R_EAX] = EAX;
292 env->regs[R_EBX] = EBX;
293 env->regs[R_ECX] = ECX;
294 env->regs[R_EDX] = EDX;
295 env->regs[R_ESI] = ESI;
296 env->regs[R_EDI] = EDI;
297 env->regs[R_EBP] = EBP;
298 env->regs[R_ESP] = ESP;
299 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard7fe48482004-10-09 18:08:01 +0000300 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000301 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellarde4533c72003-06-15 19:51:39 +0000302#elif defined(TARGET_ARM)
bellard1b21b622003-07-09 17:16:27 +0000303 env->cpsr = compute_cpsr();
bellard7fe48482004-10-09 18:08:01 +0000304 cpu_dump_state(env, logfile, fprintf, 0);
bellard99c475a2005-01-31 20:45:13 +0000305 env->cpsr &= ~CACHED_CPSR_BITS;
bellard93ac68b2003-09-30 20:57:29 +0000306#elif defined(TARGET_SPARC)
bellard7fe48482004-10-09 18:08:01 +0000307 cpu_dump_state (env, logfile, fprintf, 0);
bellard67867302003-11-23 17:05:30 +0000308#elif defined(TARGET_PPC)
bellard7fe48482004-10-09 18:08:01 +0000309 cpu_dump_state(env, logfile, fprintf, 0);
bellarde4533c72003-06-15 19:51:39 +0000310#else
311#error unsupported target CPU
312#endif
bellard3fb2ded2003-06-24 13:22:59 +0000313 }
bellard7d132992003-03-06 23:23:54 +0000314#endif
bellard3f337312003-08-20 23:02:09 +0000315 /* we record a subset of the CPU state. It will
316 always be the same before a given translated block
317 is executed. */
bellarde4533c72003-06-15 19:51:39 +0000318#if defined(TARGET_I386)
bellard2e255c62003-08-21 23:25:21 +0000319 flags = env->hflags;
bellard3f337312003-08-20 23:02:09 +0000320 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
bellard3fb2ded2003-06-24 13:22:59 +0000321 cs_base = env->segs[R_CS].base;
322 pc = cs_base + env->eip;
bellarde4533c72003-06-15 19:51:39 +0000323#elif defined(TARGET_ARM)
bellard99c475a2005-01-31 20:45:13 +0000324 flags = env->thumb;
bellard3fb2ded2003-06-24 13:22:59 +0000325 cs_base = 0;
bellardc27004e2005-01-03 23:35:10 +0000326 pc = env->regs[15];
bellard93ac68b2003-09-30 20:57:29 +0000327#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000328 flags = 0;
bellardc27004e2005-01-03 23:35:10 +0000329 cs_base = env->npc;
330 pc = env->pc;
bellard67867302003-11-23 17:05:30 +0000331#elif defined(TARGET_PPC)
332 flags = 0;
333 cs_base = 0;
bellardc27004e2005-01-03 23:35:10 +0000334 pc = env->nip;
bellarde4533c72003-06-15 19:51:39 +0000335#else
336#error unsupported CPU
337#endif
bellardc27004e2005-01-03 23:35:10 +0000338 tb = tb_find(&ptb, pc, cs_base,
bellard3fb2ded2003-06-24 13:22:59 +0000339 flags);
bellardd4e81642003-05-25 16:46:15 +0000340 if (!tb) {
bellard13768472004-01-04 17:43:01 +0000341 TranslationBlock **ptb1;
342 unsigned int h;
343 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
344
345
bellard3fb2ded2003-06-24 13:22:59 +0000346 spin_lock(&tb_lock);
bellard13768472004-01-04 17:43:01 +0000347
348 tb_invalidated_flag = 0;
bellard0d1a29f2004-10-12 22:01:28 +0000349
350 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
bellard13768472004-01-04 17:43:01 +0000351
352 /* find translated block using physical mappings */
bellardc27004e2005-01-03 23:35:10 +0000353 phys_pc = get_phys_addr_code(env, pc);
bellard13768472004-01-04 17:43:01 +0000354 phys_page1 = phys_pc & TARGET_PAGE_MASK;
355 phys_page2 = -1;
356 h = tb_phys_hash_func(phys_pc);
357 ptb1 = &tb_phys_hash[h];
358 for(;;) {
359 tb = *ptb1;
360 if (!tb)
361 goto not_found;
bellardc27004e2005-01-03 23:35:10 +0000362 if (tb->pc == pc &&
bellard13768472004-01-04 17:43:01 +0000363 tb->page_addr[0] == phys_page1 &&
bellardc27004e2005-01-03 23:35:10 +0000364 tb->cs_base == cs_base &&
bellard13768472004-01-04 17:43:01 +0000365 tb->flags == flags) {
366 /* check next page if needed */
bellardb516f852004-01-18 21:50:04 +0000367 if (tb->page_addr[1] != -1) {
bellardc27004e2005-01-03 23:35:10 +0000368 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellardb516f852004-01-18 21:50:04 +0000369 TARGET_PAGE_SIZE;
bellard13768472004-01-04 17:43:01 +0000370 phys_page2 = get_phys_addr_code(env, virt_page2);
371 if (tb->page_addr[1] == phys_page2)
372 goto found;
373 } else {
374 goto found;
375 }
376 }
377 ptb1 = &tb->phys_hash_next;
378 }
379 not_found:
bellard3fb2ded2003-06-24 13:22:59 +0000380 /* if no translated code available, then translate it now */
bellardc27004e2005-01-03 23:35:10 +0000381 tb = tb_alloc(pc);
bellard3fb2ded2003-06-24 13:22:59 +0000382 if (!tb) {
383 /* flush must be done */
bellardb453b702004-01-04 15:45:21 +0000384 tb_flush(env);
bellard3fb2ded2003-06-24 13:22:59 +0000385 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000386 tb = tb_alloc(pc);
bellard3fb2ded2003-06-24 13:22:59 +0000387 /* don't forget to invalidate previous TB info */
bellardc27004e2005-01-03 23:35:10 +0000388 ptb = &tb_hash[tb_hash_func(pc)];
bellard3fb2ded2003-06-24 13:22:59 +0000389 T0 = 0;
390 }
391 tc_ptr = code_gen_ptr;
392 tb->tc_ptr = tc_ptr;
bellardc27004e2005-01-03 23:35:10 +0000393 tb->cs_base = cs_base;
bellard3fb2ded2003-06-24 13:22:59 +0000394 tb->flags = flags;
bellardfacc68b2003-09-17 22:51:18 +0000395 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
bellard13768472004-01-04 17:43:01 +0000396 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
397
398 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000399 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellard13768472004-01-04 17:43:01 +0000400 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000401 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
bellard13768472004-01-04 17:43:01 +0000402 phys_page2 = get_phys_addr_code(env, virt_page2);
403 }
404 tb_link_phys(tb, phys_pc, phys_page2);
405
406 found:
bellard36bdbe52003-11-19 22:12:02 +0000407 if (tb_invalidated_flag) {
408 /* as some TB could have been invalidated because
409 of memory exceptions while generating the code, we
410 must recompute the hash index here */
bellardc27004e2005-01-03 23:35:10 +0000411 ptb = &tb_hash[tb_hash_func(pc)];
bellard36bdbe52003-11-19 22:12:02 +0000412 while (*ptb != NULL)
413 ptb = &(*ptb)->hash_next;
414 T0 = 0;
415 }
bellard13768472004-01-04 17:43:01 +0000416 /* we add the TB in the virtual pc hash table */
bellard3fb2ded2003-06-24 13:22:59 +0000417 *ptb = tb;
418 tb->hash_next = NULL;
419 tb_link(tb);
bellard3fb2ded2003-06-24 13:22:59 +0000420 spin_unlock(&tb_lock);
421 }
bellard9d27abd2003-05-10 13:13:54 +0000422#ifdef DEBUG_EXEC
bellardc1135f62005-01-30 22:41:54 +0000423 if ((loglevel & CPU_LOG_EXEC)) {
bellardc27004e2005-01-03 23:35:10 +0000424 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
425 (long)tb->tc_ptr, tb->pc,
426 lookup_symbol(tb->pc));
bellard3fb2ded2003-06-24 13:22:59 +0000427 }
bellard9d27abd2003-05-10 13:13:54 +0000428#endif
bellard8c6939c2003-06-09 15:28:00 +0000429#ifdef __sparc__
bellard3fb2ded2003-06-24 13:22:59 +0000430 T0 = tmp_T0;
bellard8c6939c2003-06-09 15:28:00 +0000431#endif
bellardfacc68b2003-09-17 22:51:18 +0000432 /* see if we can patch the calling TB. */
bellardc27004e2005-01-03 23:35:10 +0000433 {
434 if (T0 != 0
bellardbf3e8bf2004-02-16 21:58:54 +0000435#if defined(TARGET_I386) && defined(USE_CODE_COPY)
436 && (tb->cflags & CF_CODE_COPY) ==
437 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
438#endif
439 ) {
bellard3fb2ded2003-06-24 13:22:59 +0000440 spin_lock(&tb_lock);
bellardc27004e2005-01-03 23:35:10 +0000441 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
bellard97eb5b12004-02-25 23:19:55 +0000442#if defined(USE_CODE_COPY)
443 /* propagates the FP use info */
444 ((TranslationBlock *)(T0 & ~3))->cflags |=
445 (tb->cflags & CF_FP_USED);
446#endif
bellard3fb2ded2003-06-24 13:22:59 +0000447 spin_unlock(&tb_lock);
448 }
bellardc27004e2005-01-03 23:35:10 +0000449 }
bellard3fb2ded2003-06-24 13:22:59 +0000450 tc_ptr = tb->tc_ptr;
bellard83479e72003-06-25 16:12:37 +0000451 env->current_tb = tb;
bellard3fb2ded2003-06-24 13:22:59 +0000452 /* execute the generated code */
453 gen_func = (void *)tc_ptr;
454#if defined(__sparc__)
455 __asm__ __volatile__("call %0\n\t"
456 "mov %%o7,%%i0"
457 : /* no outputs */
458 : "r" (gen_func)
459 : "i0", "i1", "i2", "i3", "i4", "i5");
460#elif defined(__arm__)
461 asm volatile ("mov pc, %0\n\t"
462 ".global exec_loop\n\t"
463 "exec_loop:\n\t"
464 : /* no outputs */
465 : "r" (gen_func)
466 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bellardbf3e8bf2004-02-16 21:58:54 +0000467#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
468{
469 if (!(tb->cflags & CF_CODE_COPY)) {
bellard97eb5b12004-02-25 23:19:55 +0000470 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
471 save_native_fp_state(env);
472 }
bellardbf3e8bf2004-02-16 21:58:54 +0000473 gen_func();
474 } else {
bellard97eb5b12004-02-25 23:19:55 +0000475 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
476 restore_native_fp_state(env);
477 }
bellardbf3e8bf2004-02-16 21:58:54 +0000478 /* we work with native eflags */
479 CC_SRC = cc_table[CC_OP].compute_all();
480 CC_OP = CC_OP_EFLAGS;
481 asm(".globl exec_loop\n"
482 "\n"
483 "debug1:\n"
484 " pushl %%ebp\n"
485 " fs movl %10, %9\n"
486 " fs movl %11, %%eax\n"
487 " andl $0x400, %%eax\n"
488 " fs orl %8, %%eax\n"
489 " pushl %%eax\n"
490 " popf\n"
491 " fs movl %%esp, %12\n"
492 " fs movl %0, %%eax\n"
493 " fs movl %1, %%ecx\n"
494 " fs movl %2, %%edx\n"
495 " fs movl %3, %%ebx\n"
496 " fs movl %4, %%esp\n"
497 " fs movl %5, %%ebp\n"
498 " fs movl %6, %%esi\n"
499 " fs movl %7, %%edi\n"
500 " fs jmp *%9\n"
501 "exec_loop:\n"
502 " fs movl %%esp, %4\n"
503 " fs movl %12, %%esp\n"
504 " fs movl %%eax, %0\n"
505 " fs movl %%ecx, %1\n"
506 " fs movl %%edx, %2\n"
507 " fs movl %%ebx, %3\n"
508 " fs movl %%ebp, %5\n"
509 " fs movl %%esi, %6\n"
510 " fs movl %%edi, %7\n"
511 " pushf\n"
512 " popl %%eax\n"
513 " movl %%eax, %%ecx\n"
514 " andl $0x400, %%ecx\n"
515 " shrl $9, %%ecx\n"
516 " andl $0x8d5, %%eax\n"
517 " fs movl %%eax, %8\n"
518 " movl $1, %%eax\n"
519 " subl %%ecx, %%eax\n"
520 " fs movl %%eax, %11\n"
521 " fs movl %9, %%ebx\n" /* get T0 value */
522 " popl %%ebp\n"
523 :
524 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
525 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
526 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
527 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
528 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
529 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
530 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
531 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
532 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
533 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
534 "a" (gen_func),
535 "m" (*(uint8_t *)offsetof(CPUState, df)),
536 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
537 : "%ecx", "%edx"
538 );
539 }
540}
bellard3fb2ded2003-06-24 13:22:59 +0000541#else
542 gen_func();
543#endif
bellard83479e72003-06-25 16:12:37 +0000544 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000545 /* reset soft MMU for next block (it can currently
546 only be set by a memory fault) */
547#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
bellard3f337312003-08-20 23:02:09 +0000548 if (env->hflags & HF_SOFTMMU_MASK) {
549 env->hflags &= ~HF_SOFTMMU_MASK;
bellard4cbf74b2003-08-10 21:48:43 +0000550 /* do not allow linking to another block */
551 T0 = 0;
552 }
553#endif
bellard3fb2ded2003-06-24 13:22:59 +0000554 }
555 } else {
bellard0d1a29f2004-10-12 22:01:28 +0000556 env_to_regs();
bellard7d132992003-03-06 23:23:54 +0000557 }
bellard3fb2ded2003-06-24 13:22:59 +0000558 } /* for(;;) */
559
bellard7d132992003-03-06 23:23:54 +0000560
bellarde4533c72003-06-15 19:51:39 +0000561#if defined(TARGET_I386)
bellard97eb5b12004-02-25 23:19:55 +0000562#if defined(USE_CODE_COPY)
563 if (env->native_fp_regs) {
564 save_native_fp_state(env);
565 }
566#endif
bellard9de5e442003-03-23 16:49:39 +0000567 /* restore flags in standard format */
bellardfc2b4c42003-03-29 16:52:44 +0000568 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
bellard9de5e442003-03-23 16:49:39 +0000569
bellard7d132992003-03-06 23:23:54 +0000570 /* restore global registers */
bellard04369ff2003-03-20 22:33:23 +0000571#ifdef reg_EAX
572 EAX = saved_EAX;
573#endif
574#ifdef reg_ECX
575 ECX = saved_ECX;
576#endif
577#ifdef reg_EDX
578 EDX = saved_EDX;
579#endif
580#ifdef reg_EBX
581 EBX = saved_EBX;
582#endif
583#ifdef reg_ESP
584 ESP = saved_ESP;
585#endif
586#ifdef reg_EBP
587 EBP = saved_EBP;
588#endif
589#ifdef reg_ESI
590 ESI = saved_ESI;
591#endif
592#ifdef reg_EDI
593 EDI = saved_EDI;
594#endif
bellarde4533c72003-06-15 19:51:39 +0000595#elif defined(TARGET_ARM)
bellard1b21b622003-07-09 17:16:27 +0000596 env->cpsr = compute_cpsr();
bellard93ac68b2003-09-30 20:57:29 +0000597#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000598#elif defined(TARGET_PPC)
bellarde4533c72003-06-15 19:51:39 +0000599#else
600#error unsupported target CPU
601#endif
bellard8c6939c2003-06-09 15:28:00 +0000602#ifdef __sparc__
603 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
604#endif
bellard7d132992003-03-06 23:23:54 +0000605 T0 = saved_T0;
606 T1 = saved_T1;
bellarde4533c72003-06-15 19:51:39 +0000607 T2 = saved_T2;
bellard7d132992003-03-06 23:23:54 +0000608 env = saved_env;
609 return ret;
610}
bellard6dbad632003-03-16 18:05:05 +0000611
bellardfbf9eeb2004-04-25 21:21:33 +0000612/* must only be called from the generated code as an exception can be
613 generated */
614void tb_invalidate_page_range(target_ulong start, target_ulong end)
615{
bellarddc5d0b32004-06-22 18:43:30 +0000616 /* XXX: cannot enable it yet because it yields to MMU exception
617 where NIP != read address on PowerPC */
618#if 0
bellardfbf9eeb2004-04-25 21:21:33 +0000619 target_ulong phys_addr;
620 phys_addr = get_phys_addr_code(env, start);
621 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
bellarddc5d0b32004-06-22 18:43:30 +0000622#endif
bellardfbf9eeb2004-04-25 21:21:33 +0000623}
624
bellard1a18c712003-10-30 01:07:51 +0000625#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
bellarde4533c72003-06-15 19:51:39 +0000626
bellard6dbad632003-03-16 18:05:05 +0000627void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
628{
629 CPUX86State *saved_env;
630
631 saved_env = env;
632 env = s;
bellarda412ac52003-07-26 18:01:40 +0000633 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
bellarda513fe12003-05-27 23:29:48 +0000634 selector &= 0xffff;
bellard2e255c62003-08-21 23:25:21 +0000635 cpu_x86_load_seg_cache(env, seg_reg, selector,
bellardc27004e2005-01-03 23:35:10 +0000636 (selector << 4), 0xffff, 0);
bellarda513fe12003-05-27 23:29:48 +0000637 } else {
bellardb453b702004-01-04 15:45:21 +0000638 load_seg(seg_reg, selector);
bellarda513fe12003-05-27 23:29:48 +0000639 }
bellard6dbad632003-03-16 18:05:05 +0000640 env = saved_env;
641}
bellard9de5e442003-03-23 16:49:39 +0000642
bellardd0a1ffc2003-05-29 20:04:28 +0000643void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
644{
645 CPUX86State *saved_env;
646
647 saved_env = env;
648 env = s;
649
bellardc27004e2005-01-03 23:35:10 +0000650 helper_fsave((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000651
652 env = saved_env;
653}
654
655void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
656{
657 CPUX86State *saved_env;
658
659 saved_env = env;
660 env = s;
661
bellardc27004e2005-01-03 23:35:10 +0000662 helper_frstor((target_ulong)ptr, data32);
bellardd0a1ffc2003-05-29 20:04:28 +0000663
664 env = saved_env;
665}
666
bellarde4533c72003-06-15 19:51:39 +0000667#endif /* TARGET_I386 */
668
bellard67b915a2004-03-31 23:37:16 +0000669#if !defined(CONFIG_SOFTMMU)
670
bellard3fb2ded2003-06-24 13:22:59 +0000671#if defined(TARGET_I386)
672
bellardb56dad12003-05-08 15:38:04 +0000673/* 'pc' is the host PC at which the exception was raised. 'address' is
bellardfd6ce8f2003-05-14 19:00:11 +0000674 the effective address of the memory exception. 'is_write' is 1 if a
675 write caused the exception and otherwise 0'. 'old_set' is the
676 signal set which should be restored */
bellard2b413142003-05-14 23:01:10 +0000677static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000678 int is_write, sigset_t *old_set,
679 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000680{
bellarda513fe12003-05-27 23:29:48 +0000681 TranslationBlock *tb;
682 int ret;
bellard68a79312003-06-30 13:12:32 +0000683
bellard83479e72003-06-25 16:12:37 +0000684 if (cpu_single_env)
685 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellardfd6ce8f2003-05-14 19:00:11 +0000686#if defined(DEBUG_SIGNAL)
bellardbf3e8bf2004-02-16 21:58:54 +0000687 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
688 pc, address, is_write, *(unsigned long *)old_set);
bellard9de5e442003-03-23 16:49:39 +0000689#endif
bellard25eb4482003-05-14 21:50:54 +0000690 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +0000691 if (is_write && page_unprotect(address, pc, puc)) {
bellardfd6ce8f2003-05-14 19:00:11 +0000692 return 1;
693 }
bellardfbf9eeb2004-04-25 21:21:33 +0000694
bellard3fb2ded2003-06-24 13:22:59 +0000695 /* see if it is an MMU fault */
bellard93a40ea2003-10-27 21:13:06 +0000696 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
697 ((env->hflags & HF_CPL_MASK) == 3), 0);
bellard3fb2ded2003-06-24 13:22:59 +0000698 if (ret < 0)
699 return 0; /* not an MMU fault */
700 if (ret == 0)
701 return 1; /* the MMU fault was handled without causing real CPU fault */
702 /* now we have a real cpu fault */
bellarda513fe12003-05-27 23:29:48 +0000703 tb = tb_find_pc(pc);
704 if (tb) {
bellard9de5e442003-03-23 16:49:39 +0000705 /* the PC is inside the translated code. It means that we have
706 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000707 cpu_restore_state(tb, env, pc, puc);
bellard3fb2ded2003-06-24 13:22:59 +0000708 }
bellard4cbf74b2003-08-10 21:48:43 +0000709 if (ret == 1) {
bellard3fb2ded2003-06-24 13:22:59 +0000710#if 0
bellard4cbf74b2003-08-10 21:48:43 +0000711 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
712 env->eip, env->cr[2], env->error_code);
bellard3fb2ded2003-06-24 13:22:59 +0000713#endif
bellard4cbf74b2003-08-10 21:48:43 +0000714 /* we restore the process signal mask as the sigreturn should
715 do it (XXX: use sigsetjmp) */
716 sigprocmask(SIG_SETMASK, old_set, NULL);
717 raise_exception_err(EXCP0E_PAGE, env->error_code);
718 } else {
719 /* activate soft MMU for this block */
bellard3f337312003-08-20 23:02:09 +0000720 env->hflags |= HF_SOFTMMU_MASK;
bellardfbf9eeb2004-04-25 21:21:33 +0000721 cpu_resume_from_signal(env, puc);
bellard4cbf74b2003-08-10 21:48:43 +0000722 }
bellard3fb2ded2003-06-24 13:22:59 +0000723 /* never comes here */
724 return 1;
725}
726
bellarde4533c72003-06-15 19:51:39 +0000727#elif defined(TARGET_ARM)
bellard3fb2ded2003-06-24 13:22:59 +0000728static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000729 int is_write, sigset_t *old_set,
730 void *puc)
bellard3fb2ded2003-06-24 13:22:59 +0000731{
bellard68016c62005-02-07 23:12:27 +0000732 TranslationBlock *tb;
733 int ret;
734
735 if (cpu_single_env)
736 env = cpu_single_env; /* XXX: find a correct solution for multithread */
737#if defined(DEBUG_SIGNAL)
738 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
739 pc, address, is_write, *(unsigned long *)old_set);
740#endif
bellard9f0777e2005-02-02 20:42:01 +0000741 /* XXX: locking issue */
742 if (is_write && page_unprotect(address, pc, puc)) {
743 return 1;
744 }
bellard68016c62005-02-07 23:12:27 +0000745 /* see if it is an MMU fault */
746 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
747 if (ret < 0)
748 return 0; /* not an MMU fault */
749 if (ret == 0)
750 return 1; /* the MMU fault was handled without causing real CPU fault */
751 /* now we have a real cpu fault */
752 tb = tb_find_pc(pc);
753 if (tb) {
754 /* the PC is inside the translated code. It means that we have
755 a virtual CPU fault */
756 cpu_restore_state(tb, env, pc, puc);
757 }
758 /* we restore the process signal mask as the sigreturn should
759 do it (XXX: use sigsetjmp) */
760 sigprocmask(SIG_SETMASK, old_set, NULL);
761 cpu_loop_exit();
bellard3fb2ded2003-06-24 13:22:59 +0000762}
bellard93ac68b2003-09-30 20:57:29 +0000763#elif defined(TARGET_SPARC)
764static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000765 int is_write, sigset_t *old_set,
766 void *puc)
bellard93ac68b2003-09-30 20:57:29 +0000767{
bellard68016c62005-02-07 23:12:27 +0000768 TranslationBlock *tb;
769 int ret;
770
771 if (cpu_single_env)
772 env = cpu_single_env; /* XXX: find a correct solution for multithread */
773#if defined(DEBUG_SIGNAL)
774 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
775 pc, address, is_write, *(unsigned long *)old_set);
776#endif
bellardb453b702004-01-04 15:45:21 +0000777 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +0000778 if (is_write && page_unprotect(address, pc, puc)) {
bellardb453b702004-01-04 15:45:21 +0000779 return 1;
780 }
bellard68016c62005-02-07 23:12:27 +0000781 /* see if it is an MMU fault */
782 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
783 if (ret < 0)
784 return 0; /* not an MMU fault */
785 if (ret == 0)
786 return 1; /* the MMU fault was handled without causing real CPU fault */
787 /* now we have a real cpu fault */
788 tb = tb_find_pc(pc);
789 if (tb) {
790 /* the PC is inside the translated code. It means that we have
791 a virtual CPU fault */
792 cpu_restore_state(tb, env, pc, puc);
793 }
794 /* we restore the process signal mask as the sigreturn should
795 do it (XXX: use sigsetjmp) */
796 sigprocmask(SIG_SETMASK, old_set, NULL);
797 cpu_loop_exit();
bellard93ac68b2003-09-30 20:57:29 +0000798}
bellard67867302003-11-23 17:05:30 +0000799#elif defined (TARGET_PPC)
800static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bellardbf3e8bf2004-02-16 21:58:54 +0000801 int is_write, sigset_t *old_set,
802 void *puc)
bellard67867302003-11-23 17:05:30 +0000803{
804 TranslationBlock *tb;
bellardce097762004-01-04 23:53:18 +0000805 int ret;
bellard67867302003-11-23 17:05:30 +0000806
bellard67867302003-11-23 17:05:30 +0000807 if (cpu_single_env)
808 env = cpu_single_env; /* XXX: find a correct solution for multithread */
bellard67867302003-11-23 17:05:30 +0000809#if defined(DEBUG_SIGNAL)
810 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
811 pc, address, is_write, *(unsigned long *)old_set);
812#endif
813 /* XXX: locking issue */
bellardfbf9eeb2004-04-25 21:21:33 +0000814 if (is_write && page_unprotect(address, pc, puc)) {
bellard67867302003-11-23 17:05:30 +0000815 return 1;
816 }
817
bellardce097762004-01-04 23:53:18 +0000818 /* see if it is an MMU fault */
bellard7f957d22004-01-18 23:19:48 +0000819 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
bellardce097762004-01-04 23:53:18 +0000820 if (ret < 0)
821 return 0; /* not an MMU fault */
822 if (ret == 0)
823 return 1; /* the MMU fault was handled without causing real CPU fault */
824
bellard67867302003-11-23 17:05:30 +0000825 /* now we have a real cpu fault */
826 tb = tb_find_pc(pc);
827 if (tb) {
828 /* the PC is inside the translated code. It means that we have
829 a virtual CPU fault */
bellardbf3e8bf2004-02-16 21:58:54 +0000830 cpu_restore_state(tb, env, pc, puc);
bellard67867302003-11-23 17:05:30 +0000831 }
bellardce097762004-01-04 23:53:18 +0000832 if (ret == 1) {
bellard67867302003-11-23 17:05:30 +0000833#if 0
bellardce097762004-01-04 23:53:18 +0000834 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
835 env->nip, env->error_code, tb);
bellard67867302003-11-23 17:05:30 +0000836#endif
837 /* we restore the process signal mask as the sigreturn should
838 do it (XXX: use sigsetjmp) */
bellardbf3e8bf2004-02-16 21:58:54 +0000839 sigprocmask(SIG_SETMASK, old_set, NULL);
bellard9fddaa02004-05-21 12:59:32 +0000840 do_raise_exception_err(env->exception_index, env->error_code);
bellardce097762004-01-04 23:53:18 +0000841 } else {
842 /* activate soft MMU for this block */
bellardfbf9eeb2004-04-25 21:21:33 +0000843 cpu_resume_from_signal(env, puc);
bellardce097762004-01-04 23:53:18 +0000844 }
bellard67867302003-11-23 17:05:30 +0000845 /* never comes here */
846 return 1;
847}
bellarde4533c72003-06-15 19:51:39 +0000848#else
849#error unsupported target CPU
850#endif
bellard9de5e442003-03-23 16:49:39 +0000851
bellard2b413142003-05-14 23:01:10 +0000852#if defined(__i386__)
853
bellardbf3e8bf2004-02-16 21:58:54 +0000854#if defined(USE_CODE_COPY)
855static void cpu_send_trap(unsigned long pc, int trap,
856 struct ucontext *uc)
857{
858 TranslationBlock *tb;
859
860 if (cpu_single_env)
861 env = cpu_single_env; /* XXX: find a correct solution for multithread */
862 /* now we have a real cpu fault */
863 tb = tb_find_pc(pc);
864 if (tb) {
865 /* the PC is inside the translated code. It means that we have
866 a virtual CPU fault */
867 cpu_restore_state(tb, env, pc, uc);
868 }
869 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
870 raise_exception_err(trap, env->error_code);
871}
872#endif
873
bellarde4533c72003-06-15 19:51:39 +0000874int cpu_signal_handler(int host_signum, struct siginfo *info,
875 void *puc)
bellard9de5e442003-03-23 16:49:39 +0000876{
bellard9de5e442003-03-23 16:49:39 +0000877 struct ucontext *uc = puc;
878 unsigned long pc;
bellardbf3e8bf2004-02-16 21:58:54 +0000879 int trapno;
bellard97eb5b12004-02-25 23:19:55 +0000880
bellardd691f662003-03-24 21:58:34 +0000881#ifndef REG_EIP
882/* for glibc 2.1 */
bellardfd6ce8f2003-05-14 19:00:11 +0000883#define REG_EIP EIP
884#define REG_ERR ERR
885#define REG_TRAPNO TRAPNO
bellardd691f662003-03-24 21:58:34 +0000886#endif
bellardfc2b4c42003-03-29 16:52:44 +0000887 pc = uc->uc_mcontext.gregs[REG_EIP];
bellardbf3e8bf2004-02-16 21:58:54 +0000888 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
889#if defined(TARGET_I386) && defined(USE_CODE_COPY)
890 if (trapno == 0x00 || trapno == 0x05) {
891 /* send division by zero or bound exception */
892 cpu_send_trap(pc, trapno, uc);
893 return 1;
894 } else
895#endif
896 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
897 trapno == 0xe ?
898 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
899 &uc->uc_sigmask, puc);
bellard2b413142003-05-14 23:01:10 +0000900}
901
bellardbc51c5c2004-03-17 23:46:04 +0000902#elif defined(__x86_64__)
903
904int cpu_signal_handler(int host_signum, struct siginfo *info,
905 void *puc)
906{
907 struct ucontext *uc = puc;
908 unsigned long pc;
909
910 pc = uc->uc_mcontext.gregs[REG_RIP];
911 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
912 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
913 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
914 &uc->uc_sigmask, puc);
915}
916
bellard83fb7ad2004-07-05 21:25:26 +0000917#elif defined(__powerpc__)
bellard2b413142003-05-14 23:01:10 +0000918
bellard83fb7ad2004-07-05 21:25:26 +0000919/***********************************************************************
920 * signal context platform-specific definitions
921 * From Wine
922 */
923#ifdef linux
924/* All Registers access - only for local access */
925# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
926/* Gpr Registers access */
927# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
928# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
929# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
930# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
931# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
932# define LR_sig(context) REG_sig(link, context) /* Link register */
933# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
934/* Float Registers access */
935# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
936# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
937/* Exception Registers access */
938# define DAR_sig(context) REG_sig(dar, context)
939# define DSISR_sig(context) REG_sig(dsisr, context)
940# define TRAP_sig(context) REG_sig(trap, context)
941#endif /* linux */
942
943#ifdef __APPLE__
944# include <sys/ucontext.h>
945typedef struct ucontext SIGCONTEXT;
946/* All Registers access - only for local access */
947# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
948# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
949# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
950# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
951/* Gpr Registers access */
952# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
953# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
954# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
955# define CTR_sig(context) REG_sig(ctr, context)
956# define XER_sig(context) REG_sig(xer, context) /* Link register */
957# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
958# define CR_sig(context) REG_sig(cr, context) /* Condition register */
959/* Float Registers access */
960# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
961# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
962/* Exception Registers access */
963# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
964# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
965# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
966#endif /* __APPLE__ */
967
bellardd1d9f422004-07-14 17:20:55 +0000968int cpu_signal_handler(int host_signum, struct siginfo *info,
bellarde4533c72003-06-15 19:51:39 +0000969 void *puc)
bellard2b413142003-05-14 23:01:10 +0000970{
bellard25eb4482003-05-14 21:50:54 +0000971 struct ucontext *uc = puc;
bellard25eb4482003-05-14 21:50:54 +0000972 unsigned long pc;
bellard25eb4482003-05-14 21:50:54 +0000973 int is_write;
974
bellard83fb7ad2004-07-05 21:25:26 +0000975 pc = IAR_sig(uc);
bellard25eb4482003-05-14 21:50:54 +0000976 is_write = 0;
977#if 0
978 /* ppc 4xx case */
bellard83fb7ad2004-07-05 21:25:26 +0000979 if (DSISR_sig(uc) & 0x00800000)
bellard25eb4482003-05-14 21:50:54 +0000980 is_write = 1;
bellard9de5e442003-03-23 16:49:39 +0000981#else
bellard83fb7ad2004-07-05 21:25:26 +0000982 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
bellard25eb4482003-05-14 21:50:54 +0000983 is_write = 1;
984#endif
985 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +0000986 is_write, &uc->uc_sigmask, puc);
bellard9de5e442003-03-23 16:49:39 +0000987}
bellard2b413142003-05-14 23:01:10 +0000988
bellard2f87c602003-06-02 20:38:09 +0000989#elif defined(__alpha__)
990
bellarde4533c72003-06-15 19:51:39 +0000991int cpu_signal_handler(int host_signum, struct siginfo *info,
bellard2f87c602003-06-02 20:38:09 +0000992 void *puc)
993{
994 struct ucontext *uc = puc;
995 uint32_t *pc = uc->uc_mcontext.sc_pc;
996 uint32_t insn = *pc;
997 int is_write = 0;
998
bellard8c6939c2003-06-09 15:28:00 +0000999 /* XXX: need kernel patch to get write flag faster */
bellard2f87c602003-06-02 20:38:09 +00001000 switch (insn >> 26) {
1001 case 0x0d: // stw
1002 case 0x0e: // stb
1003 case 0x0f: // stq_u
1004 case 0x24: // stf
1005 case 0x25: // stg
1006 case 0x26: // sts
1007 case 0x27: // stt
1008 case 0x2c: // stl
1009 case 0x2d: // stq
1010 case 0x2e: // stl_c
1011 case 0x2f: // stq_c
1012 is_write = 1;
1013 }
1014
1015 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001016 is_write, &uc->uc_sigmask, puc);
bellard2f87c602003-06-02 20:38:09 +00001017}
bellard8c6939c2003-06-09 15:28:00 +00001018#elif defined(__sparc__)
1019
bellarde4533c72003-06-15 19:51:39 +00001020int cpu_signal_handler(int host_signum, struct siginfo *info,
1021 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001022{
1023 uint32_t *regs = (uint32_t *)(info + 1);
1024 void *sigmask = (regs + 20);
1025 unsigned long pc;
1026 int is_write;
1027 uint32_t insn;
1028
1029 /* XXX: is there a standard glibc define ? */
1030 pc = regs[1];
1031 /* XXX: need kernel patch to get write flag faster */
1032 is_write = 0;
1033 insn = *(uint32_t *)pc;
1034 if ((insn >> 30) == 3) {
1035 switch((insn >> 19) & 0x3f) {
1036 case 0x05: // stb
1037 case 0x06: // sth
1038 case 0x04: // st
1039 case 0x07: // std
1040 case 0x24: // stf
1041 case 0x27: // stdf
1042 case 0x25: // stfsr
1043 is_write = 1;
1044 break;
1045 }
1046 }
1047 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bellardbf3e8bf2004-02-16 21:58:54 +00001048 is_write, sigmask, NULL);
bellard8c6939c2003-06-09 15:28:00 +00001049}
1050
1051#elif defined(__arm__)
1052
bellarde4533c72003-06-15 19:51:39 +00001053int cpu_signal_handler(int host_signum, struct siginfo *info,
1054 void *puc)
bellard8c6939c2003-06-09 15:28:00 +00001055{
1056 struct ucontext *uc = puc;
1057 unsigned long pc;
1058 int is_write;
1059
1060 pc = uc->uc_mcontext.gregs[R15];
1061 /* XXX: compute is_write */
1062 is_write = 0;
1063 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1064 is_write,
1065 &uc->uc_sigmask);
1066}
1067
bellard38e584a2003-08-10 22:14:22 +00001068#elif defined(__mc68000)
1069
1070int cpu_signal_handler(int host_signum, struct siginfo *info,
1071 void *puc)
1072{
1073 struct ucontext *uc = puc;
1074 unsigned long pc;
1075 int is_write;
1076
1077 pc = uc->uc_mcontext.gregs[16];
1078 /* XXX: compute is_write */
1079 is_write = 0;
1080 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1081 is_write,
bellardbf3e8bf2004-02-16 21:58:54 +00001082 &uc->uc_sigmask, puc);
bellard38e584a2003-08-10 22:14:22 +00001083}
1084
bellard2b413142003-05-14 23:01:10 +00001085#else
1086
bellard3fb2ded2003-06-24 13:22:59 +00001087#error host CPU specific signal handler needed
bellard2b413142003-05-14 23:01:10 +00001088
1089#endif
bellard67b915a2004-03-31 23:37:16 +00001090
1091#endif /* !defined(CONFIG_SOFTMMU) */