blob: aa7da09e76d6172a935d1ffd5f9bd46eb86952d3 [file] [log] [blame]
David Hendricksd1c55d72010-08-24 15:14:19 -07001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
David Hendricksd1c55d72010-08-24 15:14:19 -070016 */
17
David Hendricksf7924d12010-06-10 21:26:44 -070018#include <stdlib.h>
19#include <string.h>
Edward O'Callaghanb4300ca2019-09-03 16:15:21 +100020#include <strings.h>
David Hendricksf7924d12010-06-10 21:26:44 -070021
22#include "flash.h"
23#include "flashchips.h"
24#include "chipdrivers.h"
Louis Yung-Chieh Lo52aa9302010-09-06 10:45:02 +080025#include "spi.h"
David Hendricks23cd7782010-08-25 12:42:38 -070026#include "writeprotect.h"
David Hendricksf7924d12010-06-10 21:26:44 -070027
David Hendricks1c09f802012-10-03 11:03:48 -070028/*
David Hendricksf7924d12010-06-10 21:26:44 -070029 * The following procedures rely on look-up tables to match the user-specified
30 * range with the chip's supported ranges. This turned out to be the most
31 * elegant approach since diferent flash chips use different levels of
32 * granularity and methods to determine protected ranges. In other words,
David Hendrickse0512a72014-07-15 20:30:47 -070033 * be stupid and simple since clever arithmetic will not work for many chips.
David Hendricksf7924d12010-06-10 21:26:44 -070034 */
35
36struct wp_range {
37 unsigned int start; /* starting address */
38 unsigned int len; /* len */
39};
40
41enum bit_state {
42 OFF = 0,
43 ON = 1,
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +080044 X = -1 /* don't care. Must be bigger than max # of bp. */
David Hendricksf7924d12010-06-10 21:26:44 -070045};
46
David Hendrickse0512a72014-07-15 20:30:47 -070047/*
48 * Generic write-protection schema for 25-series SPI flash chips. This assumes
49 * there is a status register that contains one or more consecutive bits which
50 * determine which address range is protected.
51 */
52
53struct status_register_layout {
54 int bp0_pos; /* position of BP0 */
55 int bp_bits; /* number of block protect bits */
56 int srp_pos; /* position of status register protect enable bit */
57};
58
Edward O'Callaghan91b38272019-12-04 17:12:43 +110059/*
60 * The following ranges and functions are useful for representing the
61 * writeprotect schema in which there are typically 5 bits of
62 * relevant information stored in status register 1:
63 * m.sec: This bit indicates the units (sectors vs. blocks)
64 * m.tb: The top-bottom bit indicates if the affected range is at the top of
65 * the flash memory's address space or at the bottom.
66 * bp: Bitmask representing the number of affected sectors/blocks.
67 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +110068struct wp_range_descriptor {
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +110069 struct modifier_bits m;
David Hendrickse0512a72014-07-15 20:30:47 -070070 unsigned int bp; /* block protect bitfield */
71 struct wp_range range;
72};
73
Edward O'Callaghana3edcb22019-12-05 14:30:50 +110074struct wp_context {
David Hendrickse0512a72014-07-15 20:30:47 -070075 struct status_register_layout sr1; /* status register 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +110076 struct wp_range_descriptor *descrs;
David Hendricks148a4bf2015-03-13 21:02:42 -070077
78 /*
79 * Some chips store modifier bits in one or more special control
80 * registers instead of the status register like many older SPI NOR
81 * flash chips did. get_modifier_bits() and set_modifier_bits() will do
82 * any chip-specific operations necessary to get/set these bit values.
83 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -070084 int (*get_modifier_bits)(const struct flashctx *flash,
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +110085 struct modifier_bits *m);
Souvik Ghoshd75cd672016-06-17 14:21:39 -070086 int (*set_modifier_bits)(const struct flashctx *flash,
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +110087 struct modifier_bits *m);
David Hendrickse0512a72014-07-15 20:30:47 -070088};
89
Edward O'Callaghanc69f6b82019-12-05 16:49:21 +110090struct w25q_status {
91 /* this maps to register layout -- do not change ordering */
92 unsigned char busy : 1;
93 unsigned char wel : 1;
94 unsigned char bp0 : 1;
95 unsigned char bp1 : 1;
96 unsigned char bp2 : 1;
97 unsigned char tb : 1;
98 unsigned char sec : 1;
99 unsigned char srp0 : 1;
100} __attribute__ ((packed));
101
102/* Status register for large flash layouts with 4 BP bits */
103struct w25q_status_large {
104 unsigned char busy : 1;
105 unsigned char wel : 1;
106 unsigned char bp0 : 1;
107 unsigned char bp1 : 1;
108 unsigned char bp2 : 1;
109 unsigned char bp3 : 1;
110 unsigned char tb : 1;
111 unsigned char srp0 : 1;
112} __attribute__ ((packed));
113
114struct w25q_status_2 {
115 unsigned char srp1 : 1;
116 unsigned char qe : 1;
117 unsigned char rsvd : 6;
118} __attribute__ ((packed));
119
120int w25_range_to_status(const struct flashctx *flash,
121 unsigned int start, unsigned int len,
122 struct w25q_status *status);
123int w25_status_to_range(const struct flashctx *flash,
124 const struct w25q_status *status,
125 unsigned int *start, unsigned int *len);
126
David Hendrickse0512a72014-07-15 20:30:47 -0700127/*
David Hendrickse0512a72014-07-15 20:30:47 -0700128 * Mask to extract write-protect enable and range bits
129 * Status register 1:
130 * SRP0: bit 7
131 * range(BP2-BP0): bit 4-2
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800132 * range(BP3-BP0): bit 5-2 (large chips)
David Hendrickse0512a72014-07-15 20:30:47 -0700133 * Status register 2:
134 * SRP1: bit 1
135 */
136#define MASK_WP_AREA (0x9C)
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800137#define MASK_WP_AREA_LARGE (0x9C)
David Hendrickse0512a72014-07-15 20:30:47 -0700138#define MASK_WP2_AREA (0x01)
139
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000140static struct wp_range_descriptor en25f40_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100141 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
142 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 504 * 1024} },
143 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 496 * 1024} },
144 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 480 * 1024} },
145 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 448 * 1024} },
146 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 384 * 1024} },
147 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 256 * 1024} },
148 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 512 * 1024} },
David Hendricks57566ed2010-08-16 18:24:45 -0700149};
150
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000151static struct wp_range_descriptor en25q40_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100152 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
153 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 504 * 1024} },
154 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 496 * 1024} },
155 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 480 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700156
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100157 { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 448 * 1024} },
158 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 384 * 1024} },
159 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
160 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700161};
162
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000163static struct wp_range_descriptor en25q80_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100164 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
165 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 1016 * 1024} },
166 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 1008 * 1024} },
167 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 992 * 1024} },
168 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 960 * 1024} },
169 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 896 * 1024} },
170 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 768 * 1024} },
171 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 1024 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700172};
173
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000174static struct wp_range_descriptor en25q32_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100175 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
176 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 4032 * 1024} },
177 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 3968 * 1024} },
178 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 3840 * 1024} },
179 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 3584 * 1024} },
180 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 3072 * 1024} },
181 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 2048 * 1024} },
182 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700183
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100184 { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
185 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 4032 * 1024} },
186 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 3968 * 1024} },
187 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 3840 * 1024} },
188 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 3584 * 1024} },
189 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 3072 * 1024} },
190 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 2048 * 1024} },
191 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700192};
193
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000194static struct wp_range_descriptor en25q64_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100195 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
196 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 8128 * 1024} },
197 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 8064 * 1024} },
198 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 7936 * 1024} },
199 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 7680 * 1024} },
200 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 7168 * 1024} },
201 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 6144 * 1024} },
202 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 8192 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700203
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100204 { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
205 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 8128 * 1024} },
206 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 8064 * 1024} },
207 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 7936 * 1024} },
208 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 7680 * 1024} },
209 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 7168 * 1024} },
210 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 6144 * 1024} },
211 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 8192 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700212};
213
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000214static struct wp_range_descriptor en25q128_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100215 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
216 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 16320 * 1024} },
217 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 16256 * 1024} },
218 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 16128 * 1024} },
219 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 15872 * 1024} },
220 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 15360 * 1024} },
221 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 14336 * 1024} },
222 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 16384 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700223
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100224 { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
225 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 16320 * 1024} },
226 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 16256 * 1024} },
227 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 16128 * 1024} },
228 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x080000, 15872 * 1024} },
229 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x100000, 15360 * 1024} },
230 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x200000, 14336 * 1024} },
231 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 16384 * 1024} },
David Hendrickse185bf22011-05-24 15:34:18 -0700232};
233
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000234static struct wp_range_descriptor en25s64_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100235 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
236 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 8064 * 1024} },
237 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 7936 * 1024} },
238 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 7680 * 1024} },
239 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 7168 * 1024} },
240 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 6144 * 1024} },
241 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 4096 * 1024} },
242 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 8192 * 1024} },
Marc Jonesb2f90022014-04-29 17:37:23 -0600243
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100244 { .m = { .sec = 0, .tb = 1 }, 0, {0, 0} }, /* none */
245 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x7e0000, 128 * 1024} },
246 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x7c0000, 256 * 1024} },
247 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x780000, 512 * 1024} },
248 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x700000, 1024 * 1024} },
249 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x600000, 2048 * 1024} },
250 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x400000, 4096 * 1024} },
251 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 8192 * 1024} },
Marc Jonesb2f90022014-04-29 17:37:23 -0600252};
253
David Hendricksf8f00c72011-02-01 12:39:46 -0800254/* mx25l1005 ranges also work for the mx25l1005c */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100255static struct wp_range_descriptor mx25l1005_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100256 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
257 { .m = { .sec = X, .tb = X }, 0x1, {0x010000, 64 * 1024} },
258 { .m = { .sec = X, .tb = X }, 0x2, {0x000000, 128 * 1024} },
259 { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 128 * 1024} },
David Hendricksf8f00c72011-02-01 12:39:46 -0800260};
261
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100262static struct wp_range_descriptor mx25l2005_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100263 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
264 { .m = { .sec = X, .tb = X }, 0x1, {0x030000, 64 * 1024} },
265 { .m = { .sec = X, .tb = X }, 0x2, {0x020000, 128 * 1024} },
266 { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 256 * 1024} },
David Hendricksf8f00c72011-02-01 12:39:46 -0800267};
268
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100269static struct wp_range_descriptor mx25l4005_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100270 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
271 { .m = { .sec = X, .tb = X }, 0x1, {0x070000, 64 * 1 * 1024} }, /* block 7 */
272 { .m = { .sec = X, .tb = X }, 0x2, {0x060000, 64 * 2 * 1024} }, /* blocks 6-7 */
273 { .m = { .sec = X, .tb = X }, 0x3, {0x040000, 64 * 4 * 1024} }, /* blocks 4-7 */
274 { .m = { .sec = X, .tb = X }, 0x4, {0x000000, 512 * 1024} },
275 { .m = { .sec = X, .tb = X }, 0x5, {0x000000, 512 * 1024} },
276 { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 512 * 1024} },
277 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 512 * 1024} },
David Hendricksf8f00c72011-02-01 12:39:46 -0800278};
279
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100280static struct wp_range_descriptor mx25l8005_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100281 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
282 { .m = { .sec = X, .tb = X }, 0x1, {0x0f0000, 64 * 1 * 1024} }, /* block 15 */
283 { .m = { .sec = X, .tb = X }, 0x2, {0x0e0000, 64 * 2 * 1024} }, /* blocks 14-15 */
284 { .m = { .sec = X, .tb = X }, 0x3, {0x0c0000, 64 * 4 * 1024} }, /* blocks 12-15 */
285 { .m = { .sec = X, .tb = X }, 0x4, {0x080000, 64 * 8 * 1024} }, /* blocks 8-15 */
286 { .m = { .sec = X, .tb = X }, 0x5, {0x000000, 1024 * 1024} },
287 { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
288 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
David Hendricksf8f00c72011-02-01 12:39:46 -0800289};
290
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100291static struct wp_range_descriptor mx25l1605d_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100292 { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
293 { .m = { .sec = X, .tb = 0 }, 0x1, {0x1f0000, 64 * 1 * 1024} }, /* block 31 */
294 { .m = { .sec = X, .tb = 0 }, 0x2, {0x1e0000, 64 * 2 * 1024} }, /* blocks 30-31 */
295 { .m = { .sec = X, .tb = 0 }, 0x3, {0x1c0000, 64 * 4 * 1024} }, /* blocks 28-31 */
296 { .m = { .sec = X, .tb = 0 }, 0x4, {0x180000, 64 * 8 * 1024} }, /* blocks 24-31 */
297 { .m = { .sec = X, .tb = 0 }, 0x5, {0x100000, 64 * 16 * 1024} }, /* blocks 16-31 */
298 { .m = { .sec = X, .tb = 0 }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
299 { .m = { .sec = X, .tb = 0 }, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
David Hendricksf8f00c72011-02-01 12:39:46 -0800300
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100301 { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 2048 * 1024} },
302 { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
303 { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
304 { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 64 * 24 * 1024} }, /* blocks 0-23 */
305 { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 64 * 28 * 1024} }, /* blocks 0-27 */
306 { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 64 * 30 * 1024} }, /* blocks 0-29 */
307 { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 64 * 31 * 1024} }, /* blocks 0-30 */
308 { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
David Hendricksf8f00c72011-02-01 12:39:46 -0800309};
310
311/* FIXME: Is there an mx25l3205 (without a trailing letter)? */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100312static struct wp_range_descriptor mx25l3205d_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100313 { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
314 { .m = { .sec = X, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
315 { .m = { .sec = X, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
316 { .m = { .sec = X, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
317 { .m = { .sec = X, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
318 { .m = { .sec = X, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
319 { .m = { .sec = X, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
320 { .m = { .sec = X, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
David Hendricksac72e362010-08-16 18:20:03 -0700321
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100322 { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 4096 * 1024} },
323 { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
324 { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 3072 * 1024} },
325 { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 3584 * 1024} },
326 { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 3840 * 1024} },
327 { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 3968 * 1024} },
328 { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 4032 * 1024} },
329 { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
David Hendricksac72e362010-08-16 18:20:03 -0700330};
331
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100332static struct wp_range_descriptor mx25u3235e_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100333 { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
334 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
335 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
336 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
337 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
338 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
339 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
340 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x000000, 4096 * 1024} },
Vincent Palatin87e092a2013-02-28 15:46:14 -0800341
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100342 { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 4096 * 1024} },
343 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 2048 * 1024} },
344 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 3072 * 1024} },
345 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 3584 * 1024} },
346 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 3840 * 1024} },
347 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 3968 * 1024} },
348 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4032 * 1024} },
349 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 4096 * 1024} },
Vincent Palatin87e092a2013-02-28 15:46:14 -0800350};
351
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100352static struct wp_range_descriptor mx25u6435e_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100353 { .m = { .sec = X, .tb = 0 }, 0, {0, 0} }, /* none */
354 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7f0000, 1 * 64 * 1024} }, /* block 127 */
355 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
356 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
357 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
358 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
359 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
360 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
Jongpil66a96492014-08-14 17:59:06 +0900361
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100362 { .m = { .sec = 0, .tb = 1 }, 0x0, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
363 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 96 * 64 * 1024} }, /* blocks 0-95 */
364 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 112 * 64 * 1024} }, /* blocks 0-111 */
365 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 120 * 64 * 1024} }, /* blocks 0-119 */
366 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 124 * 64 * 1024} }, /* blocks 0-123 */
367 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 126 * 64 * 1024} }, /* blocks 0-125 */
368 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 127 * 64 * 1024} }, /* blocks 0-126 */
369 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
Jongpil66a96492014-08-14 17:59:06 +0900370};
371
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600372#define MX25U12835E_TB (1 << 3)
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100373static struct wp_range_descriptor mx25u12835e_tb0_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100374 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
375 { .m = { .sec = 0, .tb = 0 }, 0x1, {0xff0000, 1 * 64 * 1024} }, /* block 255 */
376 { .m = { .sec = 0, .tb = 0 }, 0x2, {0xfe0000, 2 * 64 * 1024} }, /* blocks 254-255 */
377 { .m = { .sec = 0, .tb = 0 }, 0x3, {0xfc0000, 4 * 64 * 1024} }, /* blocks 252-255 */
378 { .m = { .sec = 0, .tb = 0 }, 0x4, {0xf80000, 8 * 64 * 1024} }, /* blocks 248-255 */
379 { .m = { .sec = 0, .tb = 0 }, 0x5, {0xf00000, 16 * 64 * 1024} }, /* blocks 240-255 */
380 { .m = { .sec = 0, .tb = 0 }, 0x6, {0xe00000, 32 * 64 * 1024} }, /* blocks 224-255 */
381 { .m = { .sec = 0, .tb = 0 }, 0x7, {0xc00000, 64 * 64 * 1024} }, /* blocks 192-255 */
382 { .m = { .sec = 0, .tb = 0 }, 0x8, {0x800000, 128 * 64 * 1024} }, /* blocks 128-255 */
383 { .m = { .sec = 0, .tb = 0 }, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
384 { .m = { .sec = 0, .tb = 0 }, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
385 { .m = { .sec = 0, .tb = 0 }, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
386 { .m = { .sec = 0, .tb = 0 }, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
387 { .m = { .sec = 0, .tb = 0 }, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
388 { .m = { .sec = 0, .tb = 0 }, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
389 { .m = { .sec = 0, .tb = 0 }, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600390};
Alex Lu831c6092017-11-02 23:19:34 -0700391
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100392static struct wp_range_descriptor mx25u12835e_tb1_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100393 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 1 * 64 * 1024} }, /* block 0 */
394 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
395 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
396 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
397 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
398 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
399 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
400 { .m = { .sec = 0, .tb = 1 }, 0x8, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
401 { .m = { .sec = 0, .tb = 1 }, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
402 { .m = { .sec = 0, .tb = 1 }, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
403 { .m = { .sec = 0, .tb = 1 }, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
404 { .m = { .sec = 0, .tb = 1 }, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
405 { .m = { .sec = 0, .tb = 1 }, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
406 { .m = { .sec = 0, .tb = 1 }, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
407 { .m = { .sec = 0, .tb = 1 }, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
Alex Lu831c6092017-11-02 23:19:34 -0700408};
409
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100410static struct wp_range_descriptor n25q064_ranges[] = {
David Hendricksfe9123b2015-04-21 13:18:31 -0700411 /*
412 * Note: For N25Q064, sec (usually in bit position 6) is called BP3
413 * (block protect bit 3). It is only useful when all blocks are to
414 * be write-protected.
415 */
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100416 { .m = { .sec = 0, .tb = 0 }, 0, {0, 0} }, /* none */
David Hendricksbfa624b2012-07-24 12:47:59 -0700417
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100418 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7f0000, 64 * 1024} }, /* block 127 */
419 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
420 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
421 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
422 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
423 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
424 { .m = { .sec = 0, .tb = 0 }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
David Hendricksbfa624b2012-07-24 12:47:59 -0700425
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100426 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} }, /* block 0 */
427 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
428 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
429 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
430 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
431 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
432 { .m = { .sec = 0, .tb = 1 }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
David Hendricksbfa624b2012-07-24 12:47:59 -0700433
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100434 { .m = { .sec = X, .tb = 1 }, 0x0, {0x000000, 128 * 64 * 1024} }, /* all */
435 { .m = { .sec = X, .tb = 1 }, 0x1, {0x000000, 128 * 64 * 1024} }, /* all */
436 { .m = { .sec = X, .tb = 1 }, 0x2, {0x000000, 128 * 64 * 1024} }, /* all */
437 { .m = { .sec = X, .tb = 1 }, 0x3, {0x000000, 128 * 64 * 1024} }, /* all */
438 { .m = { .sec = X, .tb = 1 }, 0x4, {0x000000, 128 * 64 * 1024} }, /* all */
439 { .m = { .sec = X, .tb = 1 }, 0x5, {0x000000, 128 * 64 * 1024} }, /* all */
440 { .m = { .sec = X, .tb = 1 }, 0x6, {0x000000, 128 * 64 * 1024} }, /* all */
441 { .m = { .sec = X, .tb = 1 }, 0x7, {0x000000, 128 * 64 * 1024} }, /* all */
David Hendricksbfa624b2012-07-24 12:47:59 -0700442};
443
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100444static struct wp_range_descriptor w25q16_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100445 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
446 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x1f0000, 64 * 1024} },
447 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x1e0000, 128 * 1024} },
448 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x1c0000, 256 * 1024} },
449 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x180000, 512 * 1024} },
450 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x100000, 1024 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700451
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100452 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
453 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
454 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
455 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
456 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 1024 * 1024} },
457 { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 2048 * 1024} },
458 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 2048 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700459
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100460 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x1ff000, 4 * 1024} },
461 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x1fe000, 8 * 1024} },
462 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x1fc000, 16 * 1024} },
463 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x1f8000, 32 * 1024} },
464 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x1f8000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700465
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100466 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
467 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
468 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
469 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
470 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700471};
472
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100473static struct wp_range_descriptor w25q32_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100474 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
475 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x3f0000, 64 * 1024} },
476 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x3e0000, 128 * 1024} },
477 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x3c0000, 256 * 1024} },
478 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x380000, 512 * 1024} },
479 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x300000, 1024 * 1024} },
480 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x200000, 2048 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700481
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100482 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
483 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
484 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
485 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
486 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 1024 * 1024} },
487 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 2048 * 1024} },
488 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 4096 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700489
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100490 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x3ff000, 4 * 1024} },
491 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x3fe000, 8 * 1024} },
492 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x3fc000, 16 * 1024} },
493 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x3f8000, 32 * 1024} },
494 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x3f8000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700495
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100496 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
497 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
498 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
499 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
500 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700501};
502
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100503static struct wp_range_descriptor w25q80_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100504 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
505 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x0f0000, 64 * 1024} },
506 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x0e0000, 128 * 1024} },
507 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x0c0000, 256 * 1024} },
508 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x080000, 512 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700509
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100510 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
511 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
512 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
513 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
514 { .m = { .sec = X, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
515 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700516
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100517 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x1ff000, 4 * 1024} },
518 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x1fe000, 8 * 1024} },
519 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x1fc000, 16 * 1024} },
520 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x1f8000, 32 * 1024} },
521 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x1f8000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700522
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100523 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
524 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
525 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
526 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
527 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700528};
529
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100530static struct wp_range_descriptor w25q64_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100531 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
David Hendricks2c4a76c2010-06-28 14:00:43 -0700532
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100533 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7e0000, 128 * 1024} },
534 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7c0000, 256 * 1024} },
535 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x780000, 512 * 1024} },
536 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x700000, 1024 * 1024} },
537 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x600000, 2048 * 1024} },
538 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x400000, 4096 * 1024} },
David Hendricks2c4a76c2010-06-28 14:00:43 -0700539
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100540 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 128 * 1024} },
541 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
542 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
543 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 1024 * 1024} },
544 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 2048 * 1024} },
545 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4096 * 1024} },
546 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 8192 * 1024} },
David Hendricks2c4a76c2010-06-28 14:00:43 -0700547
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100548 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x7ff000, 4 * 1024} },
549 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x7fe000, 8 * 1024} },
550 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x7fc000, 16 * 1024} },
551 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x7f8000, 32 * 1024} },
552 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x7f8000, 32 * 1024} },
David Hendricks2c4a76c2010-06-28 14:00:43 -0700553
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100554 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
555 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
556 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
557 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
558 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
David Hendricks2c4a76c2010-06-28 14:00:43 -0700559};
560
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100561static struct wp_range_descriptor w25rq128_cmp0_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100562 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* NONE */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530563
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100564 { .m = { .sec = 0, .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* Upper 1/64 */
565 { .m = { .sec = 0, .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* Upper 1/32 */
566 { .m = { .sec = 0, .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* Upper 1/16 */
567 { .m = { .sec = 0, .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* Upper 1/8 */
568 { .m = { .sec = 0, .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* Upper 1/4 */
569 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* Upper 1/2 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530570
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100571 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* Lower 1/64 */
572 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* Lower 1/32 */
573 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* Lower 1/16 */
574 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* Lower 1/8 */
575 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* Lower 1/4 */
576 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* Lower 1/2 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530577
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100578 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 16384 * 1024} }, /* ALL */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530579
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100580 { .m = { .sec = 1, .tb = 0 }, 0x1, {0xfff000, 4 * 1024} }, /* Upper 1/4096 */
581 { .m = { .sec = 1, .tb = 0 }, 0x2, {0xffe000, 8 * 1024} }, /* Upper 1/2048 */
582 { .m = { .sec = 1, .tb = 0 }, 0x3, {0xffc000, 16 * 1024} }, /* Upper 1/1024 */
583 { .m = { .sec = 1, .tb = 0 }, 0x4, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
584 { .m = { .sec = 1, .tb = 0 }, 0x5, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700585
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100586 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} }, /* Lower 1/4096 */
587 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} }, /* Lower 1/2048 */
588 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} }, /* Lower 1/1024 */
589 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} }, /* Lower 1/512 */
590 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} }, /* Lower 1/512 */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700591};
592
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100593static struct wp_range_descriptor w25rq128_cmp1_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100594 { .m = { .sec = X, .tb = X }, 0x0, {0x000000, 16 * 1024 * 1024} }, /* ALL */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700595
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100596 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 16128 * 1024} }, /* Lower 63/64 */
597 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 15872 * 1024} }, /* Lower 31/32 */
598 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 15 * 1024 * 1024} }, /* Lower 15/16 */
599 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x000000, 14 * 1024 * 1024} }, /* Lower 7/8 */
600 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x000000, 12 * 1024 * 1024} }, /* Lower 3/4 */
601 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x000000, 8 * 1024 * 1024} }, /* Lower 1/2 */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700602
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100603 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x040000, 16128 * 1024} }, /* Upper 63/64 */
604 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x080000, 15872 * 1024} }, /* Upper 31/32 */
605 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x100000, 15 * 1024 * 1024} }, /* Upper 15/16 */
606 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x200000, 14 * 1024 * 1024} }, /* Upper 7/8 */
607 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x400000, 12 * 1024 * 1024} }, /* Upper 3/4 */
608 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x800000, 8 * 1024 * 1024} }, /* Upper 1/2 */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700609
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100610 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 0} }, /* NONE */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700611
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100612 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x000000, 16380 * 1024} }, /* Lower 4095/4096 */
613 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x000000, 16376 * 1024} }, /* Lower 2048/2048 */
614 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x000000, 16368 * 1024} }, /* Lower 1023/1024 */
615 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
616 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700617
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100618 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x001000, 16380 * 1024} }, /* Upper 4095/4096 */
619 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x002000, 16376 * 1024} }, /* Upper 2047/2048 */
620 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x004000, 16368 * 1024} }, /* Upper 1023/1024 */
621 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
622 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530623};
624
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100625static struct wp_range_descriptor w25rq256_cmp0_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100626 { .m = { .sec = X, .tb = X }, 0x0, {0x0000000, 0x0000000} }, /* NONE */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800627
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100628 { .m = { .sec = X, .tb = 0 }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* Upper 1/512 */
629 { .m = { .sec = X, .tb = 0 }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* Upper 1/256 */
630 { .m = { .sec = X, .tb = 0 }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* Upper 1/128 */
631 { .m = { .sec = X, .tb = 0 }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* Upper 1/64 */
632 { .m = { .sec = X, .tb = 0 }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* Upper 1/32 */
633 { .m = { .sec = X, .tb = 0 }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* Upper 1/16 */
634 { .m = { .sec = X, .tb = 0 }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* Upper 1/8 */
635 { .m = { .sec = X, .tb = 0 }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* Upper 1/4 */
636 { .m = { .sec = X, .tb = 0 }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800637
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100638 { .m = { .sec = X, .tb = 1 }, 0x1, {0x0000000, 64 * 1 * 1024} }, /* Lower 1/512 */
639 { .m = { .sec = X, .tb = 1 }, 0x2, {0x0000000, 64 * 2 * 1024} }, /* Lower 1/256 */
640 { .m = { .sec = X, .tb = 1 }, 0x3, {0x0000000, 64 * 4 * 1024} }, /* Lower 1/128 */
641 { .m = { .sec = X, .tb = 1 }, 0x4, {0x0000000, 64 * 8 * 1024} }, /* Lower 1/64 */
642 { .m = { .sec = X, .tb = 1 }, 0x5, {0x0000000, 64 * 16 * 1024} }, /* Lower 1/32 */
643 { .m = { .sec = X, .tb = 1 }, 0x6, {0x0000000, 64 * 32 * 1024} }, /* Lower 1/16 */
644 { .m = { .sec = X, .tb = 1 }, 0x7, {0x0000000, 64 * 64 * 1024} }, /* Lower 1/8 */
645 { .m = { .sec = X, .tb = 1 }, 0x8, {0x0000000, 64 * 128 * 1024} }, /* Lower 1/4 */
646 { .m = { .sec = X, .tb = 1 }, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800647
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100648 { .m = { .sec = X, .tb = X }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* ALL */
649 { .m = { .sec = X, .tb = X }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* ALL */
650 { .m = { .sec = X, .tb = X }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* ALL */
651 { .m = { .sec = X, .tb = X }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* ALL */
652 { .m = { .sec = X, .tb = X }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* ALL */
653 { .m = { .sec = X, .tb = X }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* ALL */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800654};
655
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100656static struct wp_range_descriptor w25rq256_cmp1_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100657 { .m = { .sec = X, .tb = X }, 0x0, {0x0000000, 64 * 512 * 1024} }, /* ALL */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800658
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100659 { .m = { .sec = X, .tb = 0 }, 0x1, {0x0000000, 64 * 511 * 1024} }, /* Lower 511/512 */
660 { .m = { .sec = X, .tb = 0 }, 0x2, {0x0000000, 64 * 510 * 1024} }, /* Lower 255/256 */
661 { .m = { .sec = X, .tb = 0 }, 0x3, {0x0000000, 64 * 508 * 1024} }, /* Lower 127/128 */
662 { .m = { .sec = X, .tb = 0 }, 0x4, {0x0000000, 64 * 504 * 1024} }, /* Lower 63/64 */
663 { .m = { .sec = X, .tb = 0 }, 0x5, {0x0000000, 64 * 496 * 1024} }, /* Lower 31/32 */
664 { .m = { .sec = X, .tb = 0 }, 0x6, {0x0000000, 64 * 480 * 1024} }, /* Lower 15/16 */
665 { .m = { .sec = X, .tb = 0 }, 0x7, {0x0000000, 64 * 448 * 1024} }, /* Lower 7/8 */
666 { .m = { .sec = X, .tb = 0 }, 0x8, {0x0000000, 64 * 384 * 1024} }, /* Lower 3/4 */
667 { .m = { .sec = X, .tb = 0 }, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800668
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100669 { .m = { .sec = X, .tb = 1 }, 0x1, {0x0010000, 64 * 511 * 1024} }, /* Upper 511/512 */
670 { .m = { .sec = X, .tb = 1 }, 0x2, {0x0020000, 64 * 510 * 1024} }, /* Upper 255/256 */
671 { .m = { .sec = X, .tb = 1 }, 0x3, {0x0040000, 64 * 508 * 1024} }, /* Upper 127/128 */
672 { .m = { .sec = X, .tb = 1 }, 0x4, {0x0080000, 64 * 504 * 1024} }, /* Upper 63/64 */
673 { .m = { .sec = X, .tb = 1 }, 0x5, {0x0100000, 64 * 496 * 1024} }, /* Upper 31/32 */
674 { .m = { .sec = X, .tb = 1 }, 0x6, {0x0200000, 64 * 480 * 1024} }, /* Upper 15/16 */
675 { .m = { .sec = X, .tb = 1 }, 0x7, {0x0400000, 64 * 448 * 1024} }, /* Upper 7/8 */
676 { .m = { .sec = X, .tb = 1 }, 0x8, {0x0800000, 64 * 384 * 1024} }, /* Upper 3/4 */
677 { .m = { .sec = X, .tb = 1 }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800678
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100679 { .m = { .sec = X, .tb = X }, 0xa, {0x0000000, 0x0000000} }, /* NONE */
680 { .m = { .sec = X, .tb = X }, 0xb, {0x0000000, 0x0000000} }, /* NONE */
681 { .m = { .sec = X, .tb = X }, 0xc, {0x0000000, 0x0000000} }, /* NONE */
682 { .m = { .sec = X, .tb = X }, 0xd, {0x0000000, 0x0000000} }, /* NONE */
683 { .m = { .sec = X, .tb = X }, 0xe, {0x0000000, 0x0000000} }, /* NONE */
684 { .m = { .sec = X, .tb = X }, 0xf, {0x0000000, 0x0000000} }, /* NONE */
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800685};
686
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000687static struct wp_range_descriptor w25x10_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100688 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
689 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x010000, 64 * 1024} },
690 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
691 { .m = { .sec = X, .tb = X }, 0x2, {0x000000, 128 * 1024} },
692 { .m = { .sec = X, .tb = X }, 0x3, {0x000000, 128 * 1024} },
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800693};
694
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000695static struct wp_range_descriptor w25x20_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100696 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
697 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x030000, 64 * 1024} },
698 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x020000, 128 * 1024} },
699 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
700 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
701 { .m = { .sec = 0, .tb = X }, 0x3, {0x000000, 256 * 1024} },
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800702};
703
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000704static struct wp_range_descriptor w25x40_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100705 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
706 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x070000, 64 * 1024} },
707 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x060000, 128 * 1024} },
708 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x040000, 256 * 1024} },
709 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
710 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
711 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
712 { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 512 * 1024} },
713 { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 512 * 1024} },
714 { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 512 * 1024} },
715 { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 512 * 1024} },
David Hendricks470ca952010-08-13 14:01:53 -0700716};
717
Edward O'Callaghan3b996502020-04-12 20:46:51 +1000718static struct wp_range_descriptor w25x80_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100719 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
720 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x0F0000, 64 * 1024} },
721 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x0E0000, 128 * 1024} },
722 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x0C0000, 256 * 1024} },
723 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x080000, 512 * 1024} },
724 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
725 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
726 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
727 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 512 * 1024} },
728 { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 1024 * 1024} },
729 { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 1024 * 1024} },
730 { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 1024 * 1024} },
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800731};
732
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100733static struct wp_range_descriptor gd25q40_cmp0_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100734 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* None */
735 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x070000, 64 * 1024} },
736 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x060000, 128 * 1024} },
737 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x040000, 256 * 1024} },
738 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 64 * 1024} },
739 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 128 * 1024} },
740 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 256 * 1024} },
741 { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 512 * 1024} }, /* All */
742 { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 512 * 1024} }, /* All */
743 { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 512 * 1024} }, /* All */
744 { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 512 * 1024} }, /* All */
745 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x07F000, 4 * 1024} },
746 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x07E000, 8 * 1024} },
747 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x07C000, 16 * 1024} },
748 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x078000, 32 * 1024} },
749 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x078000, 32 * 1024} },
750 { .m = { .sec = 1, .tb = 0 }, 0x6, {0x078000, 32 * 1024} },
751 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
752 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
753 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
754 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
755 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
756 { .m = { .sec = 1, .tb = 1 }, 0x6, {0x000000, 32 * 1024} },
757 { .m = { .sec = 1, .tb = X }, 0x7, {0x000000, 512 * 1024} }, /* All */
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600758};
759
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100760static struct wp_range_descriptor gd25q40_cmp1_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100761 { .m = { .sec = X, .tb = X }, 0x0, {0x000000, 512 * 1024} }, /* ALL */
762 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x000000, 448 * 1024} },
763 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x000000, 384 * 1024} },
764 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x000000, 256 * 1024} },
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600765
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100766 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x010000, 448 * 1024} },
767 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x020000, 384 * 1024} },
768 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x040000, 256 * 1024} },
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600769
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100770 { .m = { .sec = 0, .tb = X }, 0x4, {0x000000, 0} }, /* None */
771 { .m = { .sec = 0, .tb = X }, 0x5, {0x000000, 0} }, /* None */
772 { .m = { .sec = 0, .tb = X }, 0x6, {0x000000, 0} }, /* None */
773 { .m = { .sec = 0, .tb = X }, 0x7, {0x000000, 0} }, /* None */
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600774
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100775 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x000000, 508 * 1024} },
776 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x000000, 504 * 1024} },
777 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x000000, 496 * 1024} },
778 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x000000, 480 * 1024} },
779 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x000000, 480 * 1024} },
780 { .m = { .sec = 1, .tb = 0 }, 0x6, {0x000000, 480 * 1024} },
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600781
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100782 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x001000, 508 * 1024} },
783 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x002000, 504 * 1024} },
784 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x004000, 496 * 1024} },
785 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x008000, 480 * 1024} },
786 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x008000, 480 * 1024} },
787 { .m = { .sec = 1, .tb = 1 }, 0x6, {0x008000, 480 * 1024} },
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600788
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100789 { .m = { .sec = 1, .tb = X }, 0x7, {0x000000, 0} }, /* None */
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600790};
791
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100792static struct wp_range_descriptor gd25q64_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100793 { .m = { .sec = X, .tb = X }, 0, {0, 0} }, /* none */
794 { .m = { .sec = 0, .tb = 0 }, 0x1, {0x7e0000, 128 * 1024} },
795 { .m = { .sec = 0, .tb = 0 }, 0x2, {0x7c0000, 256 * 1024} },
796 { .m = { .sec = 0, .tb = 0 }, 0x3, {0x780000, 512 * 1024} },
797 { .m = { .sec = 0, .tb = 0 }, 0x4, {0x700000, 1024 * 1024} },
798 { .m = { .sec = 0, .tb = 0 }, 0x5, {0x600000, 2048 * 1024} },
799 { .m = { .sec = 0, .tb = 0 }, 0x6, {0x400000, 4096 * 1024} },
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -0700800
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100801 { .m = { .sec = 0, .tb = 1 }, 0x1, {0x000000, 128 * 1024} },
802 { .m = { .sec = 0, .tb = 1 }, 0x2, {0x000000, 256 * 1024} },
803 { .m = { .sec = 0, .tb = 1 }, 0x3, {0x000000, 512 * 1024} },
804 { .m = { .sec = 0, .tb = 1 }, 0x4, {0x000000, 1024 * 1024} },
805 { .m = { .sec = 0, .tb = 1 }, 0x5, {0x000000, 2048 * 1024} },
806 { .m = { .sec = 0, .tb = 1 }, 0x6, {0x000000, 4096 * 1024} },
807 { .m = { .sec = X, .tb = X }, 0x7, {0x000000, 8192 * 1024} },
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -0700808
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100809 { .m = { .sec = 1, .tb = 0 }, 0x1, {0x7ff000, 4 * 1024} },
810 { .m = { .sec = 1, .tb = 0 }, 0x2, {0x7fe000, 8 * 1024} },
811 { .m = { .sec = 1, .tb = 0 }, 0x3, {0x7fc000, 16 * 1024} },
812 { .m = { .sec = 1, .tb = 0 }, 0x4, {0x7f8000, 32 * 1024} },
813 { .m = { .sec = 1, .tb = 0 }, 0x5, {0x7f8000, 32 * 1024} },
814 { .m = { .sec = 1, .tb = 0 }, 0x6, {0x7f8000, 32 * 1024} },
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -0700815
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100816 { .m = { .sec = 1, .tb = 1 }, 0x1, {0x000000, 4 * 1024} },
817 { .m = { .sec = 1, .tb = 1 }, 0x2, {0x000000, 8 * 1024} },
818 { .m = { .sec = 1, .tb = 1 }, 0x3, {0x000000, 16 * 1024} },
819 { .m = { .sec = 1, .tb = 1 }, 0x4, {0x000000, 32 * 1024} },
820 { .m = { .sec = 1, .tb = 1 }, 0x5, {0x000000, 32 * 1024} },
821 { .m = { .sec = 1, .tb = 1 }, 0x6, {0x000000, 32 * 1024} },
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -0700822};
823
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100824static struct wp_range_descriptor a25l040_ranges[] = {
Edward O'Callaghan91b38272019-12-04 17:12:43 +1100825 { .m = { .sec = X, .tb = X }, 0x0, {0, 0} }, /* none */
826 { .m = { .sec = X, .tb = X }, 0x1, {0x70000, 64 * 1024} },
827 { .m = { .sec = X, .tb = X }, 0x2, {0x60000, 128 * 1024} },
828 { .m = { .sec = X, .tb = X }, 0x3, {0x40000, 256 * 1024} },
829 { .m = { .sec = X, .tb = X }, 0x4, {0x00000, 512 * 1024} },
830 { .m = { .sec = X, .tb = X }, 0x5, {0x00000, 512 * 1024} },
831 { .m = { .sec = X, .tb = X }, 0x6, {0x00000, 512 * 1024} },
832 { .m = { .sec = X, .tb = X }, 0x7, {0x00000, 512 * 1024} },
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +0800833};
834
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700835static uint8_t do_read_status(const struct flashctx *flash)
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530836{
Patrick Georgif3fa2992017-02-02 16:24:44 +0100837 if (flash->chip->read_status)
838 return flash->chip->read_status(flash);
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530839 else
840 return spi_read_status_register(flash);
841}
842
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700843static int do_write_status(const struct flashctx *flash, int status)
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530844{
Patrick Georgif3fa2992017-02-02 16:24:44 +0100845 if (flash->chip->write_status)
846 return flash->chip->write_status(flash, status);
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530847 else
848 return spi_write_status_register(flash, status);
849}
850
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700851/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700852static uint8_t w25q_read_status_register_2(const struct flashctx *flash)
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700853{
854 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x35 };
855 unsigned char readarr[2];
856 int ret;
857
Edward O'Callaghan70f3e8f2020-12-21 12:50:52 +1100858 if (flash->chip->read_status) {
859 msg_cdbg("RDSR2 failed! cmd=0x35 unimpl for opaque chips\n");
860 return 0;
861 }
862
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700863 /* Read Status Register */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700864 ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700865 if (ret) {
866 /*
867 * FIXME: make this a benign failure for now in case we are
868 * unable to execute the opcode
869 */
870 msg_cdbg("RDSR2 failed!\n");
871 readarr[0] = 0x00;
872 }
873
874 return readarr[0];
875}
876
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600877/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
Edward O'Callaghandf43e902020-11-13 23:08:26 +1100878static uint8_t mx25l_read_config_register(const struct flashctx *flash)
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600879{
880 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x15 };
881 unsigned char readarr[2]; /* leave room for dummy byte */
882 int ret;
883
Edward O'Callaghan70f3e8f2020-12-21 12:50:52 +1100884 if (flash->chip->read_status) {
885 msg_cdbg("RDCR failed! cmd=0x15 unimpl for opaque chips\n");
886 return 0;
887 }
888
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600889 ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
890 if (ret) {
891 msg_cdbg("RDCR failed!\n");
892 readarr[0] = 0x00;
893 }
894
895 return readarr[0];
896}
897
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800898/* Given a flash chip, this function returns its range table. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700899static int w25_range_table(const struct flashctx *flash,
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100900 struct wp_range_descriptor **descrs,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800901 int *num_entries)
David Hendricksf7924d12010-06-10 21:26:44 -0700902{
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600903 uint8_t cr;
904
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100905 *descrs = 0;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800906 *num_entries = 0;
David Hendricksf7924d12010-06-10 21:26:44 -0700907
Patrick Georgif3fa2992017-02-02 16:24:44 +0100908 switch (flash->chip->manufacture_id) {
David Hendricksd494b0a2010-08-16 16:28:50 -0700909 case WINBOND_NEX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +0100910 switch(flash->chip->model_id) {
David Hendricksc801adb2010-12-09 16:58:56 -0800911 case WINBOND_NEX_W25X10:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100912 *descrs = w25x10_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800913 *num_entries = ARRAY_SIZE(w25x10_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800914 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800915 case WINBOND_NEX_W25X20:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100916 *descrs = w25x20_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800917 *num_entries = ARRAY_SIZE(w25x20_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800918 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800919 case WINBOND_NEX_W25X40:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100920 *descrs = w25x40_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800921 *num_entries = ARRAY_SIZE(w25x40_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700922 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800923 case WINBOND_NEX_W25X80:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100924 *descrs = w25x80_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800925 *num_entries = ARRAY_SIZE(w25x80_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800926 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100927 case WINBOND_NEX_W25Q80_V:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100928 *descrs = w25q80_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800929 *num_entries = ARRAY_SIZE(w25q80_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700930 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100931 case WINBOND_NEX_W25Q16_V:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100932 *descrs = w25q16_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800933 *num_entries = ARRAY_SIZE(w25q16_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700934 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100935 case WINBOND_NEX_W25Q32_V:
936 case WINBOND_NEX_W25Q32_W:
Edward O'Callaghand80cf712019-05-24 22:06:36 +1000937 case WINBOND_NEX_W25Q32JW:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100938 *descrs = w25q32_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800939 *num_entries = ARRAY_SIZE(w25q32_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700940 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100941 case WINBOND_NEX_W25Q64_V:
942 case WINBOND_NEX_W25Q64_W:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100943 *descrs = w25q64_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800944 *num_entries = ARRAY_SIZE(w25q64_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700945 break;
Edward O'Callaghan517cb822019-11-21 14:08:32 +1100946 case WINBOND_NEX_W25Q128_DTR:
Alan Green77a95de2019-07-01 16:40:39 +1000947 case WINBOND_NEX_W25Q128_V_M:
Patrick Georgicc04a452017-02-06 12:14:43 +0100948 case WINBOND_NEX_W25Q128_V:
949 case WINBOND_NEX_W25Q128_W:
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700950 if (w25q_read_status_register_2(flash) & (1 << 6)) {
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700951 /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100952 *descrs = w25rq128_cmp1_ranges;
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700953 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
954 } else {
955 /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100956 *descrs = w25rq128_cmp0_ranges;
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700957 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
958 }
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530959 break;
Justin TerAvest40083232020-08-17 16:34:46 -0600960 case WINBOND_NEX_W25Q256_V:
Alan Green77a95de2019-07-01 16:40:39 +1000961 case WINBOND_NEX_W25Q256JV_M:
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800962 if (w25q_read_status_register_2(flash) & (1 << 6)) {
963 /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100964 *descrs = w25rq256_cmp1_ranges;
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800965 *num_entries = ARRAY_SIZE(w25rq256_cmp1_ranges);
966 } else {
967 /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100968 *descrs = w25rq256_cmp0_ranges;
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800969 *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
970 }
971 break;
David Hendricksd494b0a2010-08-16 16:28:50 -0700972 default:
973 msg_cerr("%s() %d: WINBOND flash chip mismatch (0x%04x)"
974 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +0100975 flash->chip->model_id);
David Hendricksd494b0a2010-08-16 16:28:50 -0700976 return -1;
977 }
David Hendricks2c4a76c2010-06-28 14:00:43 -0700978 break;
David Hendricks57566ed2010-08-16 18:24:45 -0700979 case EON_ID_NOPREFIX:
Patrick Georgif3fa2992017-02-02 16:24:44 +0100980 switch (flash->chip->model_id) {
David Hendricksc801adb2010-12-09 16:58:56 -0800981 case EON_EN25F40:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100982 *descrs = en25f40_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800983 *num_entries = ARRAY_SIZE(en25f40_ranges);
David Hendricks57566ed2010-08-16 18:24:45 -0700984 break;
David Hendrickse185bf22011-05-24 15:34:18 -0700985 case EON_EN25Q40:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100986 *descrs = en25q40_ranges;
David Hendrickse185bf22011-05-24 15:34:18 -0700987 *num_entries = ARRAY_SIZE(en25q40_ranges);
988 break;
989 case EON_EN25Q80:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100990 *descrs = en25q80_ranges;
David Hendrickse185bf22011-05-24 15:34:18 -0700991 *num_entries = ARRAY_SIZE(en25q80_ranges);
992 break;
993 case EON_EN25Q32:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100994 *descrs = en25q32_ranges;
David Hendrickse185bf22011-05-24 15:34:18 -0700995 *num_entries = ARRAY_SIZE(en25q32_ranges);
996 break;
997 case EON_EN25Q64:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +1100998 *descrs = en25q64_ranges;
David Hendrickse185bf22011-05-24 15:34:18 -0700999 *num_entries = ARRAY_SIZE(en25q64_ranges);
1000 break;
1001 case EON_EN25Q128:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001002 *descrs = en25q128_ranges;
David Hendrickse185bf22011-05-24 15:34:18 -07001003 *num_entries = ARRAY_SIZE(en25q128_ranges);
1004 break;
Tim Chen136fd0a2020-06-30 19:12:50 +08001005 case EON_EN25QH128:
1006 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1007 /* CMP == 1 */
1008 *descrs = w25rq128_cmp1_ranges;
1009 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
1010 } else {
1011 /* CMP == 0 */
1012 *descrs = w25rq128_cmp0_ranges;
1013 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
1014 }
1015 break;
Marc Jonesb2f90022014-04-29 17:37:23 -06001016 case EON_EN25S64:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001017 *descrs = en25s64_ranges;
Marc Jonesb2f90022014-04-29 17:37:23 -06001018 *num_entries = ARRAY_SIZE(en25s64_ranges);
1019 break;
David Hendricks57566ed2010-08-16 18:24:45 -07001020 default:
1021 msg_cerr("%s():%d: EON flash chip mismatch (0x%04x)"
1022 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001023 flash->chip->model_id);
David Hendricks57566ed2010-08-16 18:24:45 -07001024 return -1;
1025 }
1026 break;
David Hendricksc801adb2010-12-09 16:58:56 -08001027 case MACRONIX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001028 switch (flash->chip->model_id) {
David Hendricksf8f00c72011-02-01 12:39:46 -08001029 case MACRONIX_MX25L1005:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001030 *descrs = mx25l1005_ranges;
David Hendricksf8f00c72011-02-01 12:39:46 -08001031 *num_entries = ARRAY_SIZE(mx25l1005_ranges);
1032 break;
1033 case MACRONIX_MX25L2005:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001034 *descrs = mx25l2005_ranges;
David Hendricksf8f00c72011-02-01 12:39:46 -08001035 *num_entries = ARRAY_SIZE(mx25l2005_ranges);
1036 break;
1037 case MACRONIX_MX25L4005:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001038 *descrs = mx25l4005_ranges;
David Hendricksf8f00c72011-02-01 12:39:46 -08001039 *num_entries = ARRAY_SIZE(mx25l4005_ranges);
1040 break;
1041 case MACRONIX_MX25L8005:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001042 *descrs = mx25l8005_ranges;
David Hendricksf8f00c72011-02-01 12:39:46 -08001043 *num_entries = ARRAY_SIZE(mx25l8005_ranges);
1044 break;
1045 case MACRONIX_MX25L1605:
1046 /* FIXME: MX25L1605 and MX25L1605D have different write
1047 * protection capabilities, but share IDs */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001048 *descrs = mx25l1605d_ranges;
David Hendricksf8f00c72011-02-01 12:39:46 -08001049 *num_entries = ARRAY_SIZE(mx25l1605d_ranges);
1050 break;
David Hendricksc801adb2010-12-09 16:58:56 -08001051 case MACRONIX_MX25L3205:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001052 *descrs = mx25l3205d_ranges;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001053 *num_entries = ARRAY_SIZE(mx25l3205d_ranges);
David Hendricksac72e362010-08-16 18:20:03 -07001054 break;
Vincent Palatin87e092a2013-02-28 15:46:14 -08001055 case MACRONIX_MX25U3235E:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001056 *descrs = mx25u3235e_ranges;
Vincent Palatin87e092a2013-02-28 15:46:14 -08001057 *num_entries = ARRAY_SIZE(mx25u3235e_ranges);
1058 break;
Jongpil66a96492014-08-14 17:59:06 +09001059 case MACRONIX_MX25U6435E:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001060 *descrs = mx25u6435e_ranges;
Jongpil66a96492014-08-14 17:59:06 +09001061 *num_entries = ARRAY_SIZE(mx25u6435e_ranges);
1062 break;
Alan Greendc0792e2019-07-01 15:01:34 +10001063 case MACRONIX_MX25U12835E:
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001064 cr = mx25l_read_config_register(flash);
1065 if (cr & MX25U12835E_TB) { /* T/B == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001066 *descrs = mx25u12835e_tb1_ranges;
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001067 *num_entries = ARRAY_SIZE(mx25u12835e_tb1_ranges);
1068 } else { /* T/B == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001069 *descrs = mx25u12835e_tb0_ranges;
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001070 *num_entries = ARRAY_SIZE(mx25u12835e_tb0_ranges);
1071 }
Alex Lu831c6092017-11-02 23:19:34 -07001072 break;
David Hendricksac72e362010-08-16 18:20:03 -07001073 default:
1074 msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
1075 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001076 flash->chip->model_id);
David Hendricksac72e362010-08-16 18:20:03 -07001077 return -1;
1078 }
1079 break;
David Hendricksbfa624b2012-07-24 12:47:59 -07001080 case ST_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001081 switch(flash->chip->model_id) {
David Hendricksbfa624b2012-07-24 12:47:59 -07001082 case ST_N25Q064__1E:
1083 case ST_N25Q064__3E:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001084 *descrs = n25q064_ranges;
David Hendricksbfa624b2012-07-24 12:47:59 -07001085 *num_entries = ARRAY_SIZE(n25q064_ranges);
1086 break;
1087 default:
1088 msg_cerr("%s() %d: Micron flash chip mismatch"
1089 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001090 flash->chip->model_id);
David Hendricksbfa624b2012-07-24 12:47:59 -07001091 return -1;
1092 }
1093 break;
Bryan Freed9a0051f2012-05-22 16:06:09 -07001094 case GIGADEVICE_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001095 switch(flash->chip->model_id) {
Bryan Freed9a0051f2012-05-22 16:06:09 -07001096 case GIGADEVICE_GD25LQ32:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001097 *descrs = w25q32_ranges;
Bryan Freed9a0051f2012-05-22 16:06:09 -07001098 *num_entries = ARRAY_SIZE(w25q32_ranges);
1099 break;
Martin Rothf3c3d5f2017-04-28 14:56:41 -06001100 case GIGADEVICE_GD25Q40:
1101 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1102 /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001103 *descrs = gd25q40_cmp1_ranges;
Martin Rothf3c3d5f2017-04-28 14:56:41 -06001104 *num_entries = ARRAY_SIZE(gd25q40_cmp1_ranges);
1105 } else {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001106 *descrs = gd25q40_cmp0_ranges;
Martin Rothf3c3d5f2017-04-28 14:56:41 -06001107 *num_entries = ARRAY_SIZE(gd25q40_cmp0_ranges);
1108 }
1109 break;
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -07001110 case GIGADEVICE_GD25Q64:
Marc Jonesb18734f2014-04-03 16:19:47 -06001111 case GIGADEVICE_GD25LQ64:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001112 *descrs = gd25q64_ranges;
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -07001113 *num_entries = ARRAY_SIZE(gd25q64_ranges);
1114 break;
Martin Roth1fd87ed2017-02-27 20:50:50 -07001115 case GIGADEVICE_GD25Q128:
Aaron Durbin6c957d72018-08-20 09:31:01 -06001116 case GIGADEVICE_GD25LQ128CD:
Martin Roth1fd87ed2017-02-27 20:50:50 -07001117 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1118 /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001119 *descrs = w25rq128_cmp1_ranges;
Martin Roth1fd87ed2017-02-27 20:50:50 -07001120 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
1121 } else {
1122 /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001123 *descrs = w25rq128_cmp0_ranges;
Martin Roth1fd87ed2017-02-27 20:50:50 -07001124 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
1125 }
1126 break;
Duncan Laurie0c383552019-03-16 12:35:16 -07001127 case GIGADEVICE_GD25Q256D:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001128 *descrs = w25rq256_cmp0_ranges;
Duncan Laurie0c383552019-03-16 12:35:16 -07001129 *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
1130 break;
Bryan Freed9a0051f2012-05-22 16:06:09 -07001131 default:
1132 msg_cerr("%s() %d: GigaDevice flash chip mismatch"
1133 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001134 flash->chip->model_id);
Bryan Freed9a0051f2012-05-22 16:06:09 -07001135 return -1;
1136 }
1137 break;
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001138 case AMIC_ID_NOPREFIX:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001139 switch(flash->chip->model_id) {
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001140 case AMIC_A25L040:
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001141 *descrs = a25l040_ranges;
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001142 *num_entries = ARRAY_SIZE(a25l040_ranges);
1143 break;
1144 default:
1145 msg_cerr("%s() %d: AMIC flash chip mismatch"
1146 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001147 flash->chip->model_id);
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001148 return -1;
1149 }
1150 break;
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001151 case ATMEL_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001152 switch(flash->chip->model_id) {
Edward O'Callaghan1fa87e02019-05-03 02:27:24 -04001153 case ATMEL_AT25SF128A:
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001154 case ATMEL_AT25SL128A:
1155 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1156 /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001157 *descrs = w25rq128_cmp1_ranges;
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001158 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
1159 } else {
1160 /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001161 *descrs = w25rq128_cmp0_ranges;
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001162 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
1163 }
1164 break;
1165 default:
1166 msg_cerr("%s() %d: Atmel flash chip mismatch"
1167 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001168 flash->chip->model_id);
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001169 return -1;
1170 }
1171 break;
David Hendricksf7924d12010-06-10 21:26:44 -07001172 default:
David Hendricksd494b0a2010-08-16 16:28:50 -07001173 msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
Patrick Georgif3fa2992017-02-02 16:24:44 +01001174 __func__, flash->chip->manufacture_id);
David Hendricksf7924d12010-06-10 21:26:44 -07001175 return -1;
1176 }
1177
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001178 return 0;
1179}
1180
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001181int w25_range_to_status(const struct flashctx *flash,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001182 unsigned int start, unsigned int len,
1183 struct w25q_status *status)
1184{
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001185 struct wp_range_descriptor *descrs;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001186 int i, range_found = 0;
1187 int num_entries;
1188
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001189 if (w25_range_table(flash, &descrs, &num_entries))
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001190 return -1;
1191
David Hendricksf7924d12010-06-10 21:26:44 -07001192 for (i = 0; i < num_entries; i++) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001193 struct wp_range *r = &descrs[i].range;
David Hendricksf7924d12010-06-10 21:26:44 -07001194
1195 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
1196 start, len, r->start, r->len);
1197 if ((start == r->start) && (len == r->len)) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001198 status->bp0 = descrs[i].bp & 1;
1199 status->bp1 = descrs[i].bp >> 1;
1200 status->bp2 = descrs[i].bp >> 2;
1201 status->tb = descrs[i].m.tb;
1202 status->sec = descrs[i].m.sec;
David Hendricksf7924d12010-06-10 21:26:44 -07001203
1204 range_found = 1;
1205 break;
1206 }
1207 }
1208
1209 if (!range_found) {
Edward O'Callaghan3be63e02020-03-27 14:44:24 +11001210 msg_cerr("%s: matching range not found\n", __func__);
David Hendricksf7924d12010-06-10 21:26:44 -07001211 return -1;
1212 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001213
David Hendricksd494b0a2010-08-16 16:28:50 -07001214 return 0;
1215}
1216
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001217int w25_status_to_range(const struct flashctx *flash,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001218 const struct w25q_status *status,
1219 unsigned int *start, unsigned int *len)
1220{
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001221 struct wp_range_descriptor *descrs;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001222 int i, status_found = 0;
1223 int num_entries;
1224
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001225 if (w25_range_table(flash, &descrs, &num_entries))
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001226 return -1;
1227
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001228 for (i = 0; i < num_entries; i++) {
1229 int bp;
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +08001230 int table_bp, table_tb, table_sec;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001231
1232 bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2);
1233 msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x / 0x%x 0x%x\n",
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001234 bp, descrs[i].bp,
1235 status->tb, descrs[i].m.tb,
1236 status->sec, descrs[i].m.sec);
1237 table_bp = descrs[i].bp;
1238 table_tb = descrs[i].m.tb;
1239 table_sec = descrs[i].m.sec;
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +08001240 if ((bp == table_bp || table_bp == X) &&
1241 (status->tb == table_tb || table_tb == X) &&
1242 (status->sec == table_sec || table_sec == X)) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001243 *start = descrs[i].range.start;
1244 *len = descrs[i].range.len;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001245
1246 status_found = 1;
1247 break;
1248 }
1249 }
1250
1251 if (!status_found) {
1252 msg_cerr("matching status not found\n");
1253 return -1;
1254 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001255
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001256 return 0;
1257}
1258
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001259/* Given a [start, len], this function calls w25_range_to_status() to convert
1260 * it to flash-chip-specific range bits, then sets into status register.
1261 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001262static int w25_set_range(const struct flashctx *flash,
David Hendricksd494b0a2010-08-16 16:28:50 -07001263 unsigned int start, unsigned int len)
1264{
1265 struct w25q_status status;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001266 int tmp = 0;
1267 int expected = 0;
David Hendricksd494b0a2010-08-16 16:28:50 -07001268
1269 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301270 tmp = do_read_status(flash);
David Hendricksd494b0a2010-08-16 16:28:50 -07001271 memcpy(&status, &tmp, 1);
1272 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1273
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001274 if (w25_range_to_status(flash, start, len, &status))
1275 return -1;
David Hendricksf7924d12010-06-10 21:26:44 -07001276
1277 msg_cdbg("status.busy: %x\n", status.busy);
1278 msg_cdbg("status.wel: %x\n", status.wel);
1279 msg_cdbg("status.bp0: %x\n", status.bp0);
1280 msg_cdbg("status.bp1: %x\n", status.bp1);
1281 msg_cdbg("status.bp2: %x\n", status.bp2);
1282 msg_cdbg("status.tb: %x\n", status.tb);
1283 msg_cdbg("status.sec: %x\n", status.sec);
1284 msg_cdbg("status.srp0: %x\n", status.srp0);
1285
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001286 memcpy(&expected, &status, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301287 do_write_status(flash, expected);
David Hendricksf7924d12010-06-10 21:26:44 -07001288
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301289 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001290 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
Edward O'Callaghan2672fb92019-12-04 14:47:58 +11001291 if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA)) {
David Hendricksc801adb2010-12-09 16:58:56 -08001292 msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001293 expected, tmp);
1294 return 1;
1295 }
Edward O'Callaghan2672fb92019-12-04 14:47:58 +11001296
1297 return 0;
David Hendricksf7924d12010-06-10 21:26:44 -07001298}
1299
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001300/* Print out the current status register value with human-readable text. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001301static int w25_wp_status(const struct flashctx *flash)
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001302{
1303 struct w25q_status status;
1304 int tmp;
David Hendricksce8ded32010-10-08 11:23:38 -07001305 unsigned int start, len;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001306 int ret = 0;
1307
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001308 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301309 tmp = do_read_status(flash);
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001310 memcpy(&status, &tmp, 1);
1311 msg_cinfo("WP: status: 0x%02x\n", tmp);
1312 msg_cinfo("WP: status.srp0: %x\n", status.srp0);
1313 msg_cinfo("WP: write protect is %s.\n",
1314 status.srp0 ? "enabled" : "disabled");
1315
1316 msg_cinfo("WP: write protect range: ");
1317 if (w25_status_to_range(flash, &status, &start, &len)) {
1318 msg_cinfo("(cannot resolve the range)\n");
1319 ret = -1;
1320 } else {
1321 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1322 }
1323
1324 return ret;
1325}
1326
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001327static int w25q_large_range_to_status(const struct flashctx *flash,
1328 unsigned int start, unsigned int len,
1329 struct w25q_status_large *status)
1330{
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001331 struct wp_range_descriptor *descrs;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001332 int i, range_found = 0;
1333 int num_entries;
1334
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001335 if (w25_range_table(flash, &descrs, &num_entries))
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001336 return -1;
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001337
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001338 for (i = 0; i < num_entries; i++) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001339 struct wp_range *r = &descrs[i].range;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001340
1341 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
1342 start, len, r->start, r->len);
1343 if ((start == r->start) && (len == r->len)) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001344 status->bp0 = descrs[i].bp & 1;
1345 status->bp1 = descrs[i].bp >> 1;
1346 status->bp2 = descrs[i].bp >> 2;
1347 status->bp3 = descrs[i].bp >> 3;
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001348 /*
1349 * For MX25U12835E chip, Top/Bottom (T/B) bit is not
1350 * part of status register and in that bit position is
1351 * Quad Enable (QE)
1352 */
1353 if (flash->chip->manufacture_id != MACRONIX_ID ||
1354 flash->chip->model_id != MACRONIX_MX25U12835E)
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001355 status->tb = descrs[i].m.tb;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001356
1357 range_found = 1;
1358 break;
1359 }
1360 }
1361
1362 if (!range_found) {
Edward O'Callaghan3be63e02020-03-27 14:44:24 +11001363 msg_cerr("%s: matching range not found\n", __func__);
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001364 return -1;
1365 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001366
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001367 return 0;
1368}
1369
1370static int w25_large_status_to_range(const struct flashctx *flash,
1371 const struct w25q_status_large *status,
1372 unsigned int *start, unsigned int *len)
1373{
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001374 struct wp_range_descriptor *descrs;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001375 int i, status_found = 0;
1376 int num_entries;
1377
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001378 if (w25_range_table(flash, &descrs, &num_entries))
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001379 return -1;
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001380
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001381 for (i = 0; i < num_entries; i++) {
1382 int bp;
1383 int table_bp, table_tb;
1384
1385 bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2) |
1386 (status->bp3 << 3);
1387 msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x\n",
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001388 bp, descrs[i].bp,
1389 status->tb, descrs[i].m.tb);
1390 table_bp = descrs[i].bp;
1391 table_tb = descrs[i].m.tb;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001392 if ((bp == table_bp || table_bp == X) &&
1393 (status->tb == table_tb || table_tb == X)) {
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001394 *start = descrs[i].range.start;
1395 *len = descrs[i].range.len;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001396
1397 status_found = 1;
1398 break;
1399 }
1400 }
1401
1402 if (!status_found) {
1403 msg_cerr("matching status not found\n");
1404 return -1;
1405 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001406
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001407 return 0;
1408}
1409
1410/* Given a [start, len], this function calls w25_range_to_status() to convert
1411 * it to flash-chip-specific range bits, then sets into status register.
1412 * Returns 0 if successful, -1 on error, and 1 if reading back was different.
1413 */
1414static int w25q_large_set_range(const struct flashctx *flash,
1415 unsigned int start, unsigned int len)
1416{
1417 struct w25q_status_large status;
1418 int tmp;
1419 int expected = 0;
1420
1421 memset(&status, 0, sizeof(status));
1422 tmp = do_read_status(flash);
1423 memcpy(&status, &tmp, 1);
1424 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1425
1426 if (w25q_large_range_to_status(flash, start, len, &status))
1427 return -1;
1428
1429 msg_cdbg("status.busy: %x\n", status.busy);
1430 msg_cdbg("status.wel: %x\n", status.wel);
1431 msg_cdbg("status.bp0: %x\n", status.bp0);
1432 msg_cdbg("status.bp1: %x\n", status.bp1);
1433 msg_cdbg("status.bp2: %x\n", status.bp2);
1434 msg_cdbg("status.bp3: %x\n", status.bp3);
1435 msg_cdbg("status.tb: %x\n", status.tb);
1436 msg_cdbg("status.srp0: %x\n", status.srp0);
1437
1438 memcpy(&expected, &status, sizeof(status));
1439 do_write_status(flash, expected);
1440
1441 tmp = do_read_status(flash);
1442 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
Edward O'Callaghan2672fb92019-12-04 14:47:58 +11001443 if ((tmp & MASK_WP_AREA_LARGE) != (expected & MASK_WP_AREA_LARGE)) {
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001444 msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
1445 expected, tmp);
1446 return 1;
1447 }
Edward O'Callaghan2672fb92019-12-04 14:47:58 +11001448
1449 return 0;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001450}
1451
1452static int w25q_large_wp_status(const struct flashctx *flash)
1453{
1454 struct w25q_status_large sr1;
1455 struct w25q_status_2 sr2;
1456 uint8_t tmp[2];
1457 unsigned int start, len;
1458 int ret = 0;
1459
1460 memset(&sr1, 0, sizeof(sr1));
1461 tmp[0] = do_read_status(flash);
1462 memcpy(&sr1, &tmp[0], 1);
1463
1464 memset(&sr2, 0, sizeof(sr2));
1465 tmp[1] = w25q_read_status_register_2(flash);
1466 memcpy(&sr2, &tmp[1], 1);
1467
1468 msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
1469 msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
1470 msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
1471 msg_cinfo("WP: write protect is %s.\n",
1472 (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
1473
1474 msg_cinfo("WP: write protect range: ");
1475 if (w25_large_status_to_range(flash, &sr1, &start, &len)) {
1476 msg_cinfo("(cannot resolve the range)\n");
1477 ret = -1;
1478 } else {
1479 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1480 }
1481
1482 return ret;
1483}
1484
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001485/* Set/clear the SRP0 bit in the status register. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001486static int w25_set_srp0(const struct flashctx *flash, int enable)
David Hendricksf7924d12010-06-10 21:26:44 -07001487{
1488 struct w25q_status status;
1489 int tmp = 0;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001490 int expected = 0;
David Hendricksf7924d12010-06-10 21:26:44 -07001491
1492 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301493 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001494 /* FIXME: this is NOT endian-free copy. */
David Hendricksf7924d12010-06-10 21:26:44 -07001495 memcpy(&status, &tmp, 1);
1496 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1497
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001498 status.srp0 = enable ? 1 : 0;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001499 memcpy(&expected, &status, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301500 do_write_status(flash, expected);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001501
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301502 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001503 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
1504 if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA))
1505 return 1;
David Hendricksf7924d12010-06-10 21:26:44 -07001506
1507 return 0;
1508}
1509
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001510static int w25_enable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001511 enum wp_mode wp_mode)
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001512{
1513 int ret;
1514
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11001515 if (wp_mode != WP_MODE_HARDWARE) {
David Hendricks1c09f802012-10-03 11:03:48 -07001516 msg_cerr("%s(): unsupported write-protect mode\n", __func__);
1517 return 1;
1518 }
1519
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11001520 ret = w25_set_srp0(flash, 1);
David Hendricksc801adb2010-12-09 16:58:56 -08001521 if (ret)
1522 msg_cerr("%s(): error=%d.\n", __func__, ret);
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001523 return ret;
1524}
1525
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001526static int w25_disable_writeprotect(const struct flashctx *flash)
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001527{
1528 int ret;
1529
1530 ret = w25_set_srp0(flash, 0);
David Hendricksc801adb2010-12-09 16:58:56 -08001531 if (ret)
1532 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001533
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001534 return ret;
1535}
1536
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001537static int w25_list_ranges(const struct flashctx *flash)
David Hendricks0f7f5382011-02-11 18:12:31 -08001538{
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001539 struct wp_range_descriptor *descrs;
David Hendricks0f7f5382011-02-11 18:12:31 -08001540 int i, num_entries;
1541
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001542 if (w25_range_table(flash, &descrs, &num_entries))
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001543 return -1;
1544
David Hendricks0f7f5382011-02-11 18:12:31 -08001545 for (i = 0; i < num_entries; i++) {
1546 msg_cinfo("start: 0x%06x, length: 0x%06x\n",
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11001547 descrs[i].range.start,
1548 descrs[i].range.len);
David Hendricks0f7f5382011-02-11 18:12:31 -08001549 }
1550
1551 return 0;
1552}
1553
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001554static int w25q_wp_status(const struct flashctx *flash)
David Hendricks1c09f802012-10-03 11:03:48 -07001555{
1556 struct w25q_status sr1;
1557 struct w25q_status_2 sr2;
David Hendricksf1bd8802012-10-30 11:37:57 -07001558 uint8_t tmp[2];
David Hendricks1c09f802012-10-03 11:03:48 -07001559 unsigned int start, len;
1560 int ret = 0;
1561
1562 memset(&sr1, 0, sizeof(sr1));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301563 tmp[0] = do_read_status(flash);
David Hendricksf1bd8802012-10-30 11:37:57 -07001564 memcpy(&sr1, &tmp[0], 1);
David Hendricks1c09f802012-10-03 11:03:48 -07001565
David Hendricksf1bd8802012-10-30 11:37:57 -07001566 memset(&sr2, 0, sizeof(sr2));
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001567 tmp[1] = w25q_read_status_register_2(flash);
David Hendricksf1bd8802012-10-30 11:37:57 -07001568 memcpy(&sr2, &tmp[1], 1);
1569
1570 msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
David Hendricks1c09f802012-10-03 11:03:48 -07001571 msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
1572 msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
1573 msg_cinfo("WP: write protect is %s.\n",
1574 (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
1575
1576 msg_cinfo("WP: write protect range: ");
1577 if (w25_status_to_range(flash, &sr1, &start, &len)) {
1578 msg_cinfo("(cannot resolve the range)\n");
1579 ret = -1;
1580 } else {
1581 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1582 }
1583
1584 return ret;
1585}
1586
1587/*
1588 * W25Q adds an optional byte to the standard WRSR opcode. If /CS is
1589 * de-asserted after the first byte, then it acts like a JEDEC-standard
1590 * WRSR command. if /CS is asserted, then the next data byte is written
1591 * into status register 2.
1592 */
1593#define W25Q_WRSR_OUTSIZE 0x03
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001594static int w25q_write_status_register_WREN(const struct flashctx *flash, uint8_t s1, uint8_t s2)
David Hendricks1c09f802012-10-03 11:03:48 -07001595{
1596 int result;
1597 struct spi_command cmds[] = {
1598 {
1599 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
1600 .writecnt = JEDEC_WREN_OUTSIZE,
1601 .writearr = (const unsigned char[]){ JEDEC_WREN },
1602 .readcnt = 0,
1603 .readarr = NULL,
1604 }, {
1605 .writecnt = W25Q_WRSR_OUTSIZE,
1606 .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 },
1607 .readcnt = 0,
1608 .readarr = NULL,
1609 }, {
1610 .writecnt = 0,
1611 .writearr = NULL,
1612 .readcnt = 0,
1613 .readarr = NULL,
1614 }};
1615
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001616 result = spi_send_multicommand(flash, cmds);
David Hendricks1c09f802012-10-03 11:03:48 -07001617 if (result) {
1618 msg_cerr("%s failed during command execution\n",
1619 __func__);
1620 }
1621
1622 /* WRSR performs a self-timed erase before the changes take effect. */
David Hendricks60824042014-12-11 17:22:06 -08001623 programmer_delay(100 * 1000);
David Hendricks1c09f802012-10-03 11:03:48 -07001624
1625 return result;
1626}
1627
1628/*
1629 * Set/clear the SRP1 bit in status register 2.
1630 * FIXME: make this more generic if other chips use the same SR2 layout
1631 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001632static int w25q_set_srp1(const struct flashctx *flash, int enable)
David Hendricks1c09f802012-10-03 11:03:48 -07001633{
1634 struct w25q_status sr1;
1635 struct w25q_status_2 sr2;
1636 uint8_t tmp, expected;
1637
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301638 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001639 memcpy(&sr1, &tmp, 1);
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001640 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001641 memcpy(&sr2, &tmp, 1);
1642
1643 msg_cdbg("%s: old status 2: 0x%02x\n", __func__, tmp);
1644
1645 sr2.srp1 = enable ? 1 : 0;
1646
1647 memcpy(&expected, &sr2, 1);
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001648 w25q_write_status_register_WREN(flash, *((uint8_t *)&sr1), *((uint8_t *)&sr2));
David Hendricks1c09f802012-10-03 11:03:48 -07001649
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001650 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001651 msg_cdbg("%s: new status 2: 0x%02x\n", __func__, tmp);
1652 if ((tmp & MASK_WP2_AREA) != (expected & MASK_WP2_AREA))
1653 return 1;
1654
1655 return 0;
1656}
1657
1658enum wp_mode get_wp_mode(const char *mode_str)
1659{
1660 enum wp_mode wp_mode = WP_MODE_UNKNOWN;
1661
1662 if (!strcasecmp(mode_str, "hardware"))
1663 wp_mode = WP_MODE_HARDWARE;
1664 else if (!strcasecmp(mode_str, "power_cycle"))
1665 wp_mode = WP_MODE_POWER_CYCLE;
1666 else if (!strcasecmp(mode_str, "permanent"))
1667 wp_mode = WP_MODE_PERMANENT;
1668
1669 return wp_mode;
1670}
1671
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001672static int w25q_disable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001673 enum wp_mode wp_mode)
1674{
1675 int ret = 1;
David Hendricks1c09f802012-10-03 11:03:48 -07001676 struct w25q_status_2 sr2;
1677 uint8_t tmp;
1678
1679 switch (wp_mode) {
1680 case WP_MODE_HARDWARE:
1681 ret = w25_set_srp0(flash, 0);
1682 break;
1683 case WP_MODE_POWER_CYCLE:
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001684 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001685 memcpy(&sr2, &tmp, 1);
1686 if (sr2.srp1) {
1687 msg_cerr("%s(): must disconnect power to disable "
1688 "write-protection\n", __func__);
1689 } else {
1690 ret = 0;
1691 }
1692 break;
1693 case WP_MODE_PERMANENT:
1694 msg_cerr("%s(): cannot disable permanent write-protection\n",
1695 __func__);
1696 break;
1697 default:
1698 msg_cerr("%s(): invalid mode specified\n", __func__);
1699 break;
1700 }
1701
1702 if (ret)
1703 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001704
David Hendricks1c09f802012-10-03 11:03:48 -07001705 return ret;
1706}
1707
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001708static int w25q_disable_writeprotect_default(const struct flashctx *flash)
David Hendricks1c09f802012-10-03 11:03:48 -07001709{
1710 return w25q_disable_writeprotect(flash, WP_MODE_HARDWARE);
1711}
1712
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001713static int w25q_enable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001714 enum wp_mode wp_mode)
1715{
1716 int ret = 1;
1717 struct w25q_status sr1;
1718 struct w25q_status_2 sr2;
1719 uint8_t tmp;
1720
1721 switch (wp_mode) {
1722 case WP_MODE_HARDWARE:
1723 if (w25q_disable_writeprotect(flash, WP_MODE_POWER_CYCLE)) {
1724 msg_cerr("%s(): cannot disable power cycle WP mode\n",
1725 __func__);
1726 break;
1727 }
1728
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301729 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001730 memcpy(&sr1, &tmp, 1);
1731 if (sr1.srp0)
1732 ret = 0;
1733 else
1734 ret = w25_set_srp0(flash, 1);
1735
1736 break;
1737 case WP_MODE_POWER_CYCLE:
1738 if (w25q_disable_writeprotect(flash, WP_MODE_HARDWARE)) {
1739 msg_cerr("%s(): cannot disable hardware WP mode\n",
1740 __func__);
1741 break;
1742 }
1743
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001744 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001745 memcpy(&sr2, &tmp, 1);
1746 if (sr2.srp1)
1747 ret = 0;
1748 else
1749 ret = w25q_set_srp1(flash, 1);
1750
1751 break;
1752 case WP_MODE_PERMANENT:
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301753 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001754 memcpy(&sr1, &tmp, 1);
1755 if (sr1.srp0 == 0) {
1756 ret = w25_set_srp0(flash, 1);
1757 if (ret) {
David Hendricksf1bd8802012-10-30 11:37:57 -07001758 msg_perr("%s(): cannot enable SRP0 for "
David Hendricks1c09f802012-10-03 11:03:48 -07001759 "permanent WP\n", __func__);
1760 break;
1761 }
1762 }
1763
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001764 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001765 memcpy(&sr2, &tmp, 1);
1766 if (sr2.srp1 == 0) {
1767 ret = w25q_set_srp1(flash, 1);
1768 if (ret) {
David Hendricksf1bd8802012-10-30 11:37:57 -07001769 msg_perr("%s(): cannot enable SRP1 for "
David Hendricks1c09f802012-10-03 11:03:48 -07001770 "permanent WP\n", __func__);
1771 break;
1772 }
1773 }
1774
1775 break;
David Hendricksf1bd8802012-10-30 11:37:57 -07001776 default:
1777 msg_perr("%s(): invalid mode %d\n", __func__, wp_mode);
1778 break;
David Hendricks1c09f802012-10-03 11:03:48 -07001779 }
1780
1781 if (ret)
1782 msg_cerr("%s(): error=%d.\n", __func__, ret);
1783 return ret;
1784}
1785
1786/* W25P, W25X, and many flash chips from various vendors */
David Hendricksf7924d12010-06-10 21:26:44 -07001787struct wp wp_w25 = {
David Hendricks0f7f5382011-02-11 18:12:31 -08001788 .list_ranges = w25_list_ranges,
David Hendricksf7924d12010-06-10 21:26:44 -07001789 .set_range = w25_set_range,
1790 .enable = w25_enable_writeprotect,
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001791 .disable = w25_disable_writeprotect,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001792 .wp_status = w25_wp_status,
David Hendricks1c09f802012-10-03 11:03:48 -07001793
1794};
1795
1796/* W25Q series has features such as a second status register and SFDP */
1797struct wp wp_w25q = {
1798 .list_ranges = w25_list_ranges,
1799 .set_range = w25_set_range,
1800 .enable = w25q_enable_writeprotect,
1801 /*
1802 * By default, disable hardware write-protection. We may change
1803 * this later if we want to add fine-grained write-protect disable
1804 * as a command-line option.
1805 */
1806 .disable = w25q_disable_writeprotect_default,
1807 .wp_status = w25q_wp_status,
David Hendricksf7924d12010-06-10 21:26:44 -07001808};
David Hendrickse0512a72014-07-15 20:30:47 -07001809
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001810/* W25Q large series has 4 block-protect bits */
1811struct wp wp_w25q_large = {
1812 .list_ranges = w25_list_ranges,
1813 .set_range = w25q_large_set_range,
1814 .enable = w25q_enable_writeprotect,
1815 /*
1816 * By default, disable hardware write-protection. We may change
1817 * this later if we want to add fine-grained write-protect disable
1818 * as a command-line option.
1819 */
1820 .disable = w25q_disable_writeprotect_default,
1821 .wp_status = w25q_large_wp_status,
1822};
1823
Edward O'Callaghan3b996502020-04-12 20:46:51 +10001824static struct wp_range_descriptor gd25q32_cmp0_ranges[] = {
David Hendricksaf3944a2014-07-28 18:37:40 -07001825 /* none, bp4 and bp3 => don't care */
David Hendricks148a4bf2015-03-13 21:02:42 -07001826 { { }, 0x00, {0, 0} },
1827 { { }, 0x08, {0, 0} },
1828 { { }, 0x10, {0, 0} },
1829 { { }, 0x18, {0, 0} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001830
David Hendricks148a4bf2015-03-13 21:02:42 -07001831 { { }, 0x01, {0x3f0000, 64 * 1024} },
1832 { { }, 0x02, {0x3e0000, 128 * 1024} },
1833 { { }, 0x03, {0x3c0000, 256 * 1024} },
1834 { { }, 0x04, {0x380000, 512 * 1024} },
1835 { { }, 0x05, {0x300000, 1024 * 1024} },
1836 { { }, 0x06, {0x200000, 2048 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001837
David Hendricks148a4bf2015-03-13 21:02:42 -07001838 { { }, 0x09, {0x000000, 64 * 1024} },
1839 { { }, 0x0a, {0x000000, 128 * 1024} },
1840 { { }, 0x0b, {0x000000, 256 * 1024} },
1841 { { }, 0x0c, {0x000000, 512 * 1024} },
1842 { { }, 0x0d, {0x000000, 1024 * 1024} },
1843 { { }, 0x0e, {0x000000, 2048 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001844
1845 /* all, bp4 and bp3 => don't care */
David Hendricks148a4bf2015-03-13 21:02:42 -07001846 { { }, 0x07, {0x000000, 4096 * 1024} },
1847 { { }, 0x0f, {0x000000, 4096 * 1024} },
1848 { { }, 0x17, {0x000000, 4096 * 1024} },
1849 { { }, 0x1f, {0x000000, 4096 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001850
David Hendricks148a4bf2015-03-13 21:02:42 -07001851 { { }, 0x11, {0x3ff000, 4 * 1024} },
1852 { { }, 0x12, {0x3fe000, 8 * 1024} },
1853 { { }, 0x13, {0x3fc000, 16 * 1024} },
1854 { { }, 0x14, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
1855 { { }, 0x15, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
1856 { { }, 0x16, {0x3f8000, 32 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001857
David Hendricks148a4bf2015-03-13 21:02:42 -07001858 { { }, 0x19, {0x000000, 4 * 1024} },
1859 { { }, 0x1a, {0x000000, 8 * 1024} },
1860 { { }, 0x1b, {0x000000, 16 * 1024} },
1861 { { }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1862 { { }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1863 { { }, 0x1e, {0x000000, 32 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001864};
1865
Edward O'Callaghan3b996502020-04-12 20:46:51 +10001866static struct wp_range_descriptor gd25q32_cmp1_ranges[] = {
Martin Roth563a1fe2017-04-18 14:26:27 -06001867 /* All, bp4 and bp3 => don't care */
1868 { { }, 0x00, {0x000000, 4096 * 1024} }, /* All */
1869 { { }, 0x08, {0x000000, 4096 * 1024} },
1870 { { }, 0x10, {0x000000, 4096 * 1024} },
1871 { { }, 0x18, {0x000000, 4096 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001872
David Hendricks148a4bf2015-03-13 21:02:42 -07001873 { { }, 0x01, {0x000000, 4032 * 1024} },
1874 { { }, 0x02, {0x000000, 3968 * 1024} },
1875 { { }, 0x03, {0x000000, 3840 * 1024} },
1876 { { }, 0x04, {0x000000, 3584 * 1024} },
1877 { { }, 0x05, {0x000000, 3 * 1024 * 1024} },
1878 { { }, 0x06, {0x000000, 2 * 1024 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001879
David Hendricks148a4bf2015-03-13 21:02:42 -07001880 { { }, 0x09, {0x010000, 4032 * 1024} },
1881 { { }, 0x0a, {0x020000, 3968 * 1024} },
1882 { { }, 0x0b, {0x040000, 3840 * 1024} },
1883 { { }, 0x0c, {0x080000, 3584 * 1024} },
1884 { { }, 0x0d, {0x100000, 3 * 1024 * 1024} },
1885 { { }, 0x0e, {0x200000, 2 * 1024 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001886
Martin Roth563a1fe2017-04-18 14:26:27 -06001887 /* None, bp4 and bp3 => don't care */
1888 { { }, 0x07, {0, 0} }, /* None */
1889 { { }, 0x0f, {0, 0} },
1890 { { }, 0x17, {0, 0} },
1891 { { }, 0x1f, {0, 0} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001892
David Hendricks148a4bf2015-03-13 21:02:42 -07001893 { { }, 0x11, {0x000000, 4092 * 1024} },
1894 { { }, 0x12, {0x000000, 4088 * 1024} },
1895 { { }, 0x13, {0x000000, 4080 * 1024} },
1896 { { }, 0x14, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
1897 { { }, 0x15, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
1898 { { }, 0x16, {0x000000, 4064 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001899
David Hendricks148a4bf2015-03-13 21:02:42 -07001900 { { }, 0x19, {0x001000, 4092 * 1024} },
1901 { { }, 0x1a, {0x002000, 4088 * 1024} },
1902 { { }, 0x1b, {0x040000, 4080 * 1024} },
1903 { { }, 0x1c, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
1904 { { }, 0x1d, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
1905 { { }, 0x1e, {0x080000, 4064 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001906};
1907
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11001908static struct wp_context gd25q32_wp = {
David Hendricksaf3944a2014-07-28 18:37:40 -07001909 /* TODO: map second status register */
1910 .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
1911};
1912
Edward O'Callaghan3b996502020-04-12 20:46:51 +10001913static struct wp_range_descriptor gd25q128_cmp0_ranges[] = {
David Hendricks1e9d7ca2016-03-14 15:50:34 -07001914 /* none, bp4 and bp3 => don't care, others = 0 */
1915 { { .tb = 0 }, 0x00, {0, 0} },
1916 { { .tb = 0 }, 0x08, {0, 0} },
1917 { { .tb = 0 }, 0x10, {0, 0} },
1918 { { .tb = 0 }, 0x18, {0, 0} },
1919
1920 { { .tb = 0 }, 0x01, {0xfc0000, 256 * 1024} },
1921 { { .tb = 0 }, 0x02, {0xf80000, 512 * 1024} },
1922 { { .tb = 0 }, 0x03, {0xf00000, 1024 * 1024} },
1923 { { .tb = 0 }, 0x04, {0xe00000, 2048 * 1024} },
1924 { { .tb = 0 }, 0x05, {0xc00000, 4096 * 1024} },
1925 { { .tb = 0 }, 0x06, {0x800000, 8192 * 1024} },
1926
1927 { { .tb = 0 }, 0x09, {0x000000, 256 * 1024} },
1928 { { .tb = 0 }, 0x0a, {0x000000, 512 * 1024} },
1929 { { .tb = 0 }, 0x0b, {0x000000, 1024 * 1024} },
1930 { { .tb = 0 }, 0x0c, {0x000000, 2048 * 1024} },
1931 { { .tb = 0 }, 0x0d, {0x000000, 4096 * 1024} },
1932 { { .tb = 0 }, 0x0e, {0x000000, 8192 * 1024} },
1933
1934 /* all, bp4 and bp3 => don't care, others = 1 */
1935 { { .tb = 0 }, 0x07, {0x000000, 16384 * 1024} },
1936 { { .tb = 0 }, 0x0f, {0x000000, 16384 * 1024} },
1937 { { .tb = 0 }, 0x17, {0x000000, 16384 * 1024} },
1938 { { .tb = 0 }, 0x1f, {0x000000, 16384 * 1024} },
1939
1940 { { .tb = 0 }, 0x11, {0xfff000, 4 * 1024} },
1941 { { .tb = 0 }, 0x12, {0xffe000, 8 * 1024} },
1942 { { .tb = 0 }, 0x13, {0xffc000, 16 * 1024} },
1943 { { .tb = 0 }, 0x14, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
1944 { { .tb = 0 }, 0x15, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
1945
1946 { { .tb = 0 }, 0x19, {0x000000, 4 * 1024} },
1947 { { .tb = 0 }, 0x1a, {0x000000, 8 * 1024} },
1948 { { .tb = 0 }, 0x1b, {0x000000, 16 * 1024} },
1949 { { .tb = 0 }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1950 { { .tb = 0 }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1951 { { .tb = 0 }, 0x1e, {0x000000, 32 * 1024} },
1952};
1953
Edward O'Callaghan3b996502020-04-12 20:46:51 +10001954static struct wp_range_descriptor gd25q128_cmp1_ranges[] = {
David Hendricks1e9d7ca2016-03-14 15:50:34 -07001955 /* none, bp4 and bp3 => don't care, others = 0 */
1956 { { .tb = 1 }, 0x00, {0x000000, 16384 * 1024} },
1957 { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
1958 { { .tb = 1 }, 0x10, {0x000000, 16384 * 1024} },
1959 { { .tb = 1 }, 0x18, {0x000000, 16384 * 1024} },
1960
1961 { { .tb = 1 }, 0x01, {0x000000, 16128 * 1024} },
1962 { { .tb = 1 }, 0x02, {0x000000, 15872 * 1024} },
1963 { { .tb = 1 }, 0x03, {0x000000, 15360 * 1024} },
1964 { { .tb = 1 }, 0x04, {0x000000, 14336 * 1024} },
1965 { { .tb = 1 }, 0x05, {0x000000, 12288 * 1024} },
1966 { { .tb = 1 }, 0x06, {0x000000, 8192 * 1024} },
1967
1968 { { .tb = 1 }, 0x09, {0x000000, 16128 * 1024} },
1969 { { .tb = 1 }, 0x0a, {0x000000, 15872 * 1024} },
1970 { { .tb = 1 }, 0x0b, {0x000000, 15360 * 1024} },
1971 { { .tb = 1 }, 0x0c, {0x000000, 14336 * 1024} },
1972 { { .tb = 1 }, 0x0d, {0x000000, 12288 * 1024} },
1973 { { .tb = 1 }, 0x0e, {0x000000, 8192 * 1024} },
1974
1975 /* none, bp4 and bp3 => don't care, others = 1 */
1976 { { .tb = 1 }, 0x07, {0x000000, 16384 * 1024} },
1977 { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
1978 { { .tb = 1 }, 0x0f, {0x000000, 16384 * 1024} },
1979 { { .tb = 1 }, 0x17, {0x000000, 16384 * 1024} },
1980 { { .tb = 1 }, 0x1f, {0x000000, 16384 * 1024} },
1981
1982 { { .tb = 1 }, 0x11, {0x000000, 16380 * 1024} },
1983 { { .tb = 1 }, 0x12, {0x000000, 16376 * 1024} },
1984 { { .tb = 1 }, 0x13, {0x000000, 16368 * 1024} },
1985 { { .tb = 1 }, 0x14, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
1986 { { .tb = 1 }, 0x15, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
1987
1988 { { .tb = 1 }, 0x19, {0x001000, 16380 * 1024} },
1989 { { .tb = 1 }, 0x1a, {0x002000, 16376 * 1024} },
1990 { { .tb = 1 }, 0x1b, {0x004000, 16368 * 1024} },
1991 { { .tb = 1 }, 0x1c, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
1992 { { .tb = 1 }, 0x1d, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
1993 { { .tb = 1 }, 0x1e, {0x008000, 16352 * 1024} },
1994};
1995
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11001996static struct wp_context gd25q128_wp = {
David Hendricks1e9d7ca2016-03-14 15:50:34 -07001997 /* TODO: map second and third status registers */
1998 .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
1999};
2000
David Hendricks83541d32014-07-15 20:58:21 -07002001/* FIXME: MX25L6406 has same ID as MX25L6405D */
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002002static struct wp_range_descriptor mx25l6406e_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002003 { { }, 0, {0, 0} }, /* none */
2004 { { }, 0x1, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
2005 { { }, 0x2, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
2006 { { }, 0x3, {0x7a0000, 64 * 8 * 1024} }, /* blocks 120-127 */
2007 { { }, 0x4, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
2008 { { }, 0x5, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
2009 { { }, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
David Hendricks83541d32014-07-15 20:58:21 -07002010
David Hendricks148a4bf2015-03-13 21:02:42 -07002011 { { }, 0x7, {0x000000, 64 * 128 * 1024} }, /* all */
2012 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2013 { { }, 0x9, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2014 { { }, 0xa, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */
2015 { { }, 0xb, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */
2016 { { }, 0xc, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */
2017 { { }, 0xd, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */
2018 { { }, 0xe, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */
2019 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricks83541d32014-07-15 20:58:21 -07002020};
2021
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002022static struct wp_context mx25l6406e_wp = {
David Hendricks83541d32014-07-15 20:58:21 -07002023 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002024 .descrs = &mx25l6406e_ranges[0],
David Hendricks83541d32014-07-15 20:58:21 -07002025};
David Hendrickse0512a72014-07-15 20:30:47 -07002026
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002027static struct wp_range_descriptor mx25l6495f_tb0_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002028 { { }, 0, {0, 0} }, /* none */
2029 { { }, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */
2030 { { }, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
2031 { { }, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
David Hendricksc3496092014-11-13 17:20:55 -08002032
David Hendricks148a4bf2015-03-13 21:02:42 -07002033 { { }, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */
2034 { { }, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
2035 { { }, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
2036 { { }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
2037 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2038 { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
2039 { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
2040 { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
2041 { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
2042 { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
2043 { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
2044 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricksc3496092014-11-13 17:20:55 -08002045};
2046
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002047static struct wp_range_descriptor mx25l6495f_tb1_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002048 { { }, 0, {0, 0} }, /* none */
2049 { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
2050 { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
2051 { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
2052 { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
2053 { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
2054 { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
2055 { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2056 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2057 { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
2058 { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
2059 { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
2060 { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
2061 { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
2062 { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
2063 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricksc3496092014-11-13 17:20:55 -08002064};
2065
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002066static struct wp_context mx25l6495f_wp = {
David Hendricksc3496092014-11-13 17:20:55 -08002067 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
2068};
2069
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002070static struct wp_range_descriptor mx25l25635f_tb0_ranges[] = {
Vic Yang848bfd12018-03-23 10:24:07 -07002071 { { }, 0, {0, 0} }, /* none */
2072 { { }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* block 511 */
2073 { { }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* blocks 510-511 */
2074 { { }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* blocks 508-511 */
2075 { { }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* blocks 504-511 */
2076 { { }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* blocks 496-511 */
2077 { { }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* blocks 480-511 */
2078 { { }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* blocks 448-511 */
2079 { { }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* blocks 384-511 */
2080 { { }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* blocks 256-511 */
2081 { { }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* all */
2082 { { }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* all */
2083 { { }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* all */
2084 { { }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* all */
2085 { { }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* all */
2086 { { }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* all */
2087};
2088
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002089static struct wp_range_descriptor mx25l25635f_tb1_ranges[] = {
Vic Yang848bfd12018-03-23 10:24:07 -07002090 { { }, 0, {0, 0} }, /* none */
2091 { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
2092 { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
2093 { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
2094 { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
2095 { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
2096 { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
2097 { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2098 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */
2099 { { }, 0x9, {0x000000, 64 * 256 * 1024} }, /* blocks 0-255 */
2100 { { }, 0xa, {0x000000, 64 * 512 * 1024} }, /* all */
2101 { { }, 0xb, {0x000000, 64 * 512 * 1024} }, /* all */
2102 { { }, 0xc, {0x000000, 64 * 512 * 1024} }, /* all */
2103 { { }, 0xd, {0x000000, 64 * 512 * 1024} }, /* all */
2104 { { }, 0xe, {0x000000, 64 * 512 * 1024} }, /* all */
2105 { { }, 0xf, {0x000000, 64 * 512 * 1024} }, /* all */
2106};
2107
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002108static struct wp_context mx25l25635f_wp = {
Vic Yang848bfd12018-03-23 10:24:07 -07002109 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
2110};
2111
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002112static struct wp_range_descriptor s25fs128s_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002113 { { .tb = 1 }, 0, {0, 0} }, /* none */
2114 { { .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* lower 64th */
2115 { { .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* lower 32nd */
2116 { { .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* lower 16th */
2117 { { .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* lower 8th */
2118 { { .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* lower 4th */
2119 { { .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* lower half */
2120 { { .tb = 1 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
David Hendricksa9884852014-12-11 15:31:12 -08002121
David Hendricks148a4bf2015-03-13 21:02:42 -07002122 { { .tb = 0 }, 0, {0, 0} }, /* none */
2123 { { .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* upper 64th */
2124 { { .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* upper 32nd */
2125 { { .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* upper 16th */
2126 { { .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* upper 8th */
2127 { { .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* upper 4th */
2128 { { .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* upper half */
2129 { { .tb = 0 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
David Hendricksa9884852014-12-11 15:31:12 -08002130};
2131
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002132static struct wp_context s25fs128s_wp = {
David Hendricksa9884852014-12-11 15:31:12 -08002133 .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
David Hendricks148a4bf2015-03-13 21:02:42 -07002134 .get_modifier_bits = s25f_get_modifier_bits,
2135 .set_modifier_bits = s25f_set_modifier_bits,
David Hendricksa9884852014-12-11 15:31:12 -08002136};
2137
David Hendricksc694bb82015-02-25 14:52:17 -08002138
Edward O'Callaghan3b996502020-04-12 20:46:51 +10002139static struct wp_range_descriptor s25fl256s_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002140 { { .tb = 1 }, 0, {0, 0} }, /* none */
2141 { { .tb = 1 }, 0x1, {0x000000, 512 * 1024} }, /* lower 64th */
2142 { { .tb = 1 }, 0x2, {0x000000, 1024 * 1024} }, /* lower 32nd */
2143 { { .tb = 1 }, 0x3, {0x000000, 2048 * 1024} }, /* lower 16th */
2144 { { .tb = 1 }, 0x4, {0x000000, 4096 * 1024} }, /* lower 8th */
2145 { { .tb = 1 }, 0x5, {0x000000, 8192 * 1024} }, /* lower 4th */
2146 { { .tb = 1 }, 0x6, {0x000000, 16384 * 1024} }, /* lower half */
2147 { { .tb = 1 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
2148
2149 { { .tb = 0 }, 0, {0, 0} }, /* none */
2150 { { .tb = 0 }, 0x1, {0x1f80000, 512 * 1024} }, /* upper 64th */
2151 { { .tb = 0 }, 0x2, {0x1f00000, 1024 * 1024} }, /* upper 32nd */
2152 { { .tb = 0 }, 0x3, {0x1e00000, 2048 * 1024} }, /* upper 16th */
2153 { { .tb = 0 }, 0x4, {0x1c00000, 4096 * 1024} }, /* upper 8th */
2154 { { .tb = 0 }, 0x5, {0x1800000, 8192 * 1024} }, /* upper 4th */
2155 { { .tb = 0 }, 0x6, {0x1000000, 16384 * 1024} }, /* upper half */
2156 { { .tb = 0 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
David Hendricksc694bb82015-02-25 14:52:17 -08002157};
2158
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002159static struct wp_context s25fl256s_wp = {
David Hendricksc694bb82015-02-25 14:52:17 -08002160 .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
David Hendricks148a4bf2015-03-13 21:02:42 -07002161 .get_modifier_bits = s25f_get_modifier_bits,
2162 .set_modifier_bits = s25f_set_modifier_bits,
David Hendricksc694bb82015-02-25 14:52:17 -08002163};
2164
David Hendrickse0512a72014-07-15 20:30:47 -07002165/* Given a flash chip, this function returns its writeprotect info. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002166static int generic_range_table(const struct flashctx *flash,
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002167 struct wp_context **wp,
David Hendrickse0512a72014-07-15 20:30:47 -07002168 int *num_entries)
2169{
2170 *wp = NULL;
2171 *num_entries = 0;
2172
Patrick Georgif3fa2992017-02-02 16:24:44 +01002173 switch (flash->chip->manufacture_id) {
David Hendricksaf3944a2014-07-28 18:37:40 -07002174 case GIGADEVICE_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002175 switch(flash->chip->model_id) {
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002176
Martin Roth563a1fe2017-04-18 14:26:27 -06002177 case GIGADEVICE_GD25LQ32:
David Hendricksaf3944a2014-07-28 18:37:40 -07002178 case GIGADEVICE_GD25Q32: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002179 uint8_t sr1 = w25q_read_status_register_2(flash);
David Hendricksaf3944a2014-07-28 18:37:40 -07002180 *wp = &gd25q32_wp;
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002181
David Hendricksaf3944a2014-07-28 18:37:40 -07002182 if (!(sr1 & (1 << 6))) { /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002183 (*wp)->descrs = &gd25q32_cmp0_ranges[0];
David Hendricksaf3944a2014-07-28 18:37:40 -07002184 *num_entries = ARRAY_SIZE(gd25q32_cmp0_ranges);
2185 } else { /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002186 (*wp)->descrs = &gd25q32_cmp1_ranges[0];
David Hendricksaf3944a2014-07-28 18:37:40 -07002187 *num_entries = ARRAY_SIZE(gd25q32_cmp1_ranges);
2188 }
2189
2190 break;
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002191 }
Furquan Shaikh62cd8102016-07-17 23:04:06 -07002192 case GIGADEVICE_GD25Q128:
Aaron Durbin6c957d72018-08-20 09:31:01 -06002193 case GIGADEVICE_GD25LQ128CD: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002194 uint8_t sr1 = w25q_read_status_register_2(flash);
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002195 *wp = &gd25q128_wp;
2196
2197 if (!(sr1 & (1 << 6))) { /* CMP == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002198 (*wp)->descrs = &gd25q128_cmp0_ranges[0];
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002199 *num_entries = ARRAY_SIZE(gd25q128_cmp0_ranges);
2200 } else { /* CMP == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002201 (*wp)->descrs = &gd25q128_cmp1_ranges[0];
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002202 *num_entries = ARRAY_SIZE(gd25q128_cmp1_ranges);
2203 }
2204
2205 break;
David Hendricksaf3944a2014-07-28 18:37:40 -07002206 }
2207 default:
2208 msg_cerr("%s() %d: GigaDevice flash chip mismatch"
2209 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01002210 flash->chip->model_id);
David Hendricksaf3944a2014-07-28 18:37:40 -07002211 return -1;
2212 }
2213 break;
David Hendricks83541d32014-07-15 20:58:21 -07002214 case MACRONIX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002215 switch (flash->chip->model_id) {
David Hendricks83541d32014-07-15 20:58:21 -07002216 case MACRONIX_MX25L6405:
2217 /* FIXME: MX25L64* chips have mixed capabilities and
2218 share IDs */
2219 *wp = &mx25l6406e_wp;
2220 *num_entries = ARRAY_SIZE(mx25l6406e_ranges);
2221 break;
David Hendricksc3496092014-11-13 17:20:55 -08002222 case MACRONIX_MX25L6495F: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002223 uint8_t cr = mx25l_read_config_register(flash);
David Hendricksc3496092014-11-13 17:20:55 -08002224
2225 *wp = &mx25l6495f_wp;
2226 if (!(cr & (1 << 3))) { /* T/B == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002227 (*wp)->descrs = &mx25l6495f_tb0_ranges[0];
David Hendricksc3496092014-11-13 17:20:55 -08002228 *num_entries = ARRAY_SIZE(mx25l6495f_tb0_ranges);
2229 } else { /* T/B == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002230 (*wp)->descrs = &mx25l6495f_tb1_ranges[0];
David Hendricksc3496092014-11-13 17:20:55 -08002231 *num_entries = ARRAY_SIZE(mx25l6495f_tb1_ranges);
2232 }
2233 break;
2234 }
Vic Yang848bfd12018-03-23 10:24:07 -07002235 case MACRONIX_MX25L25635F: {
2236 uint8_t cr = mx25l_read_config_register(flash);
2237
2238 *wp = &mx25l25635f_wp;
2239 if (!(cr & (1 << 3))) { /* T/B == 0 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002240 (*wp)->descrs = &mx25l25635f_tb0_ranges[0];
Vic Yang848bfd12018-03-23 10:24:07 -07002241 *num_entries = ARRAY_SIZE(mx25l25635f_tb0_ranges);
2242 } else { /* T/B == 1 */
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002243 (*wp)->descrs = &mx25l25635f_tb1_ranges[0];
Vic Yang848bfd12018-03-23 10:24:07 -07002244 *num_entries = ARRAY_SIZE(mx25l25635f_tb1_ranges);
2245 }
2246 break;
2247 }
David Hendricks83541d32014-07-15 20:58:21 -07002248 default:
2249 msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
2250 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01002251 flash->chip->model_id);
David Hendricks83541d32014-07-15 20:58:21 -07002252 return -1;
2253 }
2254 break;
David Hendricksa9884852014-12-11 15:31:12 -08002255 case SPANSION_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002256 switch (flash->chip->model_id) {
David Hendricksa9884852014-12-11 15:31:12 -08002257 case SPANSION_S25FS128S_L:
2258 case SPANSION_S25FS128S_S: {
David Hendricksa9884852014-12-11 15:31:12 -08002259 *wp = &s25fs128s_wp;
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002260 (*wp)->descrs = s25fs128s_ranges;
David Hendricks148a4bf2015-03-13 21:02:42 -07002261 *num_entries = ARRAY_SIZE(s25fs128s_ranges);
David Hendricksa9884852014-12-11 15:31:12 -08002262 break;
2263 }
David Hendricksc694bb82015-02-25 14:52:17 -08002264 case SPANSION_S25FL256S_UL:
2265 case SPANSION_S25FL256S_US: {
David Hendricksc694bb82015-02-25 14:52:17 -08002266 *wp = &s25fl256s_wp;
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002267 (*wp)->descrs = s25fl256s_ranges;
David Hendricks148a4bf2015-03-13 21:02:42 -07002268 *num_entries = ARRAY_SIZE(s25fl256s_ranges);
David Hendricksc694bb82015-02-25 14:52:17 -08002269 break;
2270 }
David Hendricksa9884852014-12-11 15:31:12 -08002271 default:
2272 msg_cerr("%s():%d Spansion flash chip mismatch (0x%04x)"
Patrick Georgif3fa2992017-02-02 16:24:44 +01002273 ", aborting\n", __func__, __LINE__,
2274 flash->chip->model_id);
David Hendricksa9884852014-12-11 15:31:12 -08002275 return -1;
2276 }
2277 break;
David Hendrickse0512a72014-07-15 20:30:47 -07002278 default:
2279 msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
Patrick Georgif3fa2992017-02-02 16:24:44 +01002280 __func__, flash->chip->manufacture_id);
David Hendrickse0512a72014-07-15 20:30:47 -07002281 return -1;
2282 }
2283
2284 return 0;
2285}
2286
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002287static uint8_t generic_get_bp_mask(struct wp_context *wp)
Marco Chen9d5bddb2020-02-11 17:12:56 +08002288{
2289 return ((1 << (wp->sr1.bp0_pos + wp->sr1.bp_bits)) - 1) ^ \
2290 ((1 << wp->sr1.bp0_pos) - 1);
2291}
2292
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002293static uint8_t generic_get_status_check_mask(struct wp_context *wp)
Marco Chen9d5bddb2020-02-11 17:12:56 +08002294{
2295 return generic_get_bp_mask(wp) | 1 << wp->sr1.srp_pos;
2296}
2297
David Hendrickse0512a72014-07-15 20:30:47 -07002298/* Given a [start, len], this function finds a block protect bit combination
2299 * (if possible) and sets the corresponding bits in "status". Remaining bits
2300 * are preserved. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002301static int generic_range_to_status(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002302 unsigned int start, unsigned int len,
Marco Chen9d5bddb2020-02-11 17:12:56 +08002303 uint8_t *status, uint8_t *check_mask)
David Hendrickse0512a72014-07-15 20:30:47 -07002304{
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002305 struct wp_context *wp;
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002306 struct wp_range_descriptor *r;
David Hendrickse0512a72014-07-15 20:30:47 -07002307 int i, range_found = 0, num_entries;
2308 uint8_t bp_mask;
2309
2310 if (generic_range_table(flash, &wp, &num_entries))
2311 return -1;
2312
Marco Chen9d5bddb2020-02-11 17:12:56 +08002313 bp_mask = generic_get_bp_mask(wp);
David Hendrickse0512a72014-07-15 20:30:47 -07002314
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002315 for (i = 0, r = &wp->descrs[0]; i < num_entries; i++, r++) {
David Hendrickse0512a72014-07-15 20:30:47 -07002316 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
2317 start, len, r->range.start, r->range.len);
2318 if ((start == r->range.start) && (len == r->range.len)) {
2319 *status &= ~(bp_mask);
2320 *status |= r->bp << (wp->sr1.bp0_pos);
David Hendricks148a4bf2015-03-13 21:02:42 -07002321
2322 if (wp->set_modifier_bits) {
2323 if (wp->set_modifier_bits(flash, &r->m) < 0) {
2324 msg_cerr("error setting modifier "
2325 "bits for range.\n");
2326 return -1;
2327 }
2328 }
2329
David Hendrickse0512a72014-07-15 20:30:47 -07002330 range_found = 1;
2331 break;
2332 }
2333 }
2334
2335 if (!range_found) {
Edward O'Callaghan3be63e02020-03-27 14:44:24 +11002336 msg_cerr("%s: matching range not found\n", __func__);
David Hendrickse0512a72014-07-15 20:30:47 -07002337 return -1;
2338 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002339
Marco Chen9d5bddb2020-02-11 17:12:56 +08002340 *check_mask = generic_get_status_check_mask(wp);
David Hendrickse0512a72014-07-15 20:30:47 -07002341 return 0;
2342}
2343
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002344static int generic_status_to_range(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002345 const uint8_t sr1, unsigned int *start, unsigned int *len)
2346{
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002347 struct wp_context *wp;
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002348 struct wp_range_descriptor *r;
Duncan Laurie04ca1172015-03-12 09:25:34 -07002349 int num_entries, i, status_found = 0;
David Hendrickse0512a72014-07-15 20:30:47 -07002350 uint8_t sr1_bp;
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +11002351 struct modifier_bits m;
David Hendrickse0512a72014-07-15 20:30:47 -07002352
2353 if (generic_range_table(flash, &wp, &num_entries))
2354 return -1;
2355
David Hendricks148a4bf2015-03-13 21:02:42 -07002356 /* modifier bits may be compared more than once, so get them here */
Edward O'Callaghanadcc7782019-12-04 14:50:14 +11002357 if (wp->get_modifier_bits && wp->get_modifier_bits(flash, &m) < 0)
David Hendricks148a4bf2015-03-13 21:02:42 -07002358 return -1;
David Hendricks148a4bf2015-03-13 21:02:42 -07002359
David Hendrickse0512a72014-07-15 20:30:47 -07002360 sr1_bp = (sr1 >> wp->sr1.bp0_pos) & ((1 << wp->sr1.bp_bits) - 1);
2361
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002362 for (i = 0, r = &wp->descrs[0]; i < num_entries; i++, r++) {
David Hendricks148a4bf2015-03-13 21:02:42 -07002363 if (wp->get_modifier_bits) {
2364 if (memcmp(&m, &r->m, sizeof(m)))
2365 continue;
2366 }
David Hendrickse0512a72014-07-15 20:30:47 -07002367 msg_cspew("comparing 0x%02x 0x%02x\n", sr1_bp, r->bp);
2368 if (sr1_bp == r->bp) {
2369 *start = r->range.start;
2370 *len = r->range.len;
2371 status_found = 1;
2372 break;
2373 }
2374 }
2375
2376 if (!status_found) {
2377 msg_cerr("matching status not found\n");
2378 return -1;
2379 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002380
David Hendrickse0512a72014-07-15 20:30:47 -07002381 return 0;
2382}
2383
2384/* Given a [start, len], this function calls generic_range_to_status() to
2385 * convert it to flash-chip-specific range bits, then sets into status register.
2386 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002387static int generic_set_range(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002388 unsigned int start, unsigned int len)
2389{
Marco Chen9d5bddb2020-02-11 17:12:56 +08002390 uint8_t status, expected, check_mask;
David Hendrickse0512a72014-07-15 20:30:47 -07002391
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302392 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002393 msg_cdbg("%s: old status: 0x%02x\n", __func__, status);
2394
2395 expected = status; /* preserve non-bp bits */
Marco Chen9d5bddb2020-02-11 17:12:56 +08002396 if (generic_range_to_status(flash, start, len, &expected, &check_mask))
David Hendrickse0512a72014-07-15 20:30:47 -07002397 return -1;
2398
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302399 do_write_status(flash, expected);
David Hendrickse0512a72014-07-15 20:30:47 -07002400
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302401 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002402 msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
Marco Chen9d5bddb2020-02-11 17:12:56 +08002403 if ((status & check_mask) != (expected & check_mask)) {
2404 msg_cerr("expected=0x%02x, but actual=0x%02x. check mask=0x%02x\n",
2405 expected, status, check_mask);
David Hendrickse0512a72014-07-15 20:30:47 -07002406 return 1;
2407 }
David Hendrickse0512a72014-07-15 20:30:47 -07002408 return 0;
2409}
2410
2411/* Set/clear the status regsiter write protect bit in SR1. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002412static int generic_set_srp0(const struct flashctx *flash, int enable)
David Hendrickse0512a72014-07-15 20:30:47 -07002413{
Marco Chen9d5bddb2020-02-11 17:12:56 +08002414 uint8_t status, expected, check_mask;
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002415 struct wp_context *wp;
David Hendrickse0512a72014-07-15 20:30:47 -07002416 int num_entries;
2417
2418 if (generic_range_table(flash, &wp, &num_entries))
2419 return -1;
2420
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302421 expected = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002422 msg_cdbg("%s: old status: 0x%02x\n", __func__, expected);
2423
2424 if (enable)
2425 expected |= 1 << wp->sr1.srp_pos;
2426 else
2427 expected &= ~(1 << wp->sr1.srp_pos);
2428
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302429 do_write_status(flash, expected);
David Hendrickse0512a72014-07-15 20:30:47 -07002430
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302431 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002432 msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
Marco Chen9d5bddb2020-02-11 17:12:56 +08002433
2434 check_mask = generic_get_status_check_mask(wp);
2435 msg_cdbg("%s: check mask: 0x%02x\n", __func__, check_mask);
2436 if ((status & check_mask) != (expected & check_mask)) {
2437 msg_cerr("expected=0x%02x, but actual=0x%02x. check mask=0x%02x\n",
2438 expected, status, check_mask);
David Hendrickse0512a72014-07-15 20:30:47 -07002439 return -1;
Marco Chen9d5bddb2020-02-11 17:12:56 +08002440 }
David Hendrickse0512a72014-07-15 20:30:47 -07002441
2442 return 0;
2443}
2444
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002445static int generic_enable_writeprotect(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002446 enum wp_mode wp_mode)
2447{
2448 int ret;
2449
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002450 if (wp_mode != WP_MODE_HARDWARE) {
David Hendrickse0512a72014-07-15 20:30:47 -07002451 msg_cerr("%s(): unsupported write-protect mode\n", __func__);
2452 return 1;
2453 }
2454
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002455 ret = generic_set_srp0(flash, 1);
David Hendrickse0512a72014-07-15 20:30:47 -07002456 if (ret)
2457 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002458
David Hendrickse0512a72014-07-15 20:30:47 -07002459 return ret;
2460}
2461
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002462static int generic_disable_writeprotect(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002463{
2464 int ret;
2465
2466 ret = generic_set_srp0(flash, 0);
2467 if (ret)
2468 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002469
David Hendrickse0512a72014-07-15 20:30:47 -07002470 return ret;
2471}
2472
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002473static int generic_list_ranges(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002474{
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002475 struct wp_context *wp;
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002476 struct wp_range_descriptor *r;
David Hendrickse0512a72014-07-15 20:30:47 -07002477 int i, num_entries;
2478
2479 if (generic_range_table(flash, &wp, &num_entries))
2480 return -1;
2481
Edward O'Callaghane146f9a2019-12-05 14:27:24 +11002482 r = &wp->descrs[0];
David Hendrickse0512a72014-07-15 20:30:47 -07002483 for (i = 0; i < num_entries; i++) {
2484 msg_cinfo("start: 0x%06x, length: 0x%06x\n",
2485 r->range.start, r->range.len);
2486 r++;
2487 }
2488
2489 return 0;
2490}
2491
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002492static int wp_context_status(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002493{
2494 uint8_t sr1;
2495 unsigned int start, len;
2496 int ret = 0;
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002497 struct wp_context *wp;
David Hendrickse0512a72014-07-15 20:30:47 -07002498 int num_entries, wp_en;
2499
2500 if (generic_range_table(flash, &wp, &num_entries))
2501 return -1;
2502
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302503 sr1 = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002504 wp_en = (sr1 >> wp->sr1.srp_pos) & 1;
2505
2506 msg_cinfo("WP: status: 0x%04x\n", sr1);
2507 msg_cinfo("WP: status.srp0: %x\n", wp_en);
2508 /* FIXME: SRP1 is not really generic, but we probably should print
2509 * it anyway to have consistent output. #legacycruft */
2510 msg_cinfo("WP: status.srp1: %x\n", 0);
2511 msg_cinfo("WP: write protect is %s.\n",
2512 wp_en ? "enabled" : "disabled");
2513
2514 msg_cinfo("WP: write protect range: ");
2515 if (generic_status_to_range(flash, sr1, &start, &len)) {
2516 msg_cinfo("(cannot resolve the range)\n");
2517 ret = -1;
2518 } else {
2519 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
2520 }
2521
2522 return ret;
2523}
2524
2525struct wp wp_generic = {
2526 .list_ranges = generic_list_ranges,
2527 .set_range = generic_set_range,
2528 .enable = generic_enable_writeprotect,
2529 .disable = generic_disable_writeprotect,
Edward O'Callaghana3edcb22019-12-05 14:30:50 +11002530 .wp_status = wp_context_status,
David Hendrickse0512a72014-07-15 20:30:47 -07002531};