blob: 3d4d9e7e7875efc95e093936bdcf9e3ac3dbdfc0 [file] [log] [blame]
David Hendricksd1c55d72010-08-24 15:14:19 -07001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
David Hendricksd1c55d72010-08-24 15:14:19 -070016 */
17
David Hendricksf7924d12010-06-10 21:26:44 -070018#include <stdlib.h>
19#include <string.h>
Edward O'Callaghanb4300ca2019-09-03 16:15:21 +100020#include <strings.h>
David Hendricksf7924d12010-06-10 21:26:44 -070021
22#include "flash.h"
23#include "flashchips.h"
24#include "chipdrivers.h"
Louis Yung-Chieh Lo52aa9302010-09-06 10:45:02 +080025#include "spi.h"
David Hendricks23cd7782010-08-25 12:42:38 -070026#include "writeprotect.h"
David Hendricksf7924d12010-06-10 21:26:44 -070027
David Hendricks1c09f802012-10-03 11:03:48 -070028/*
David Hendricksf7924d12010-06-10 21:26:44 -070029 * The following procedures rely on look-up tables to match the user-specified
30 * range with the chip's supported ranges. This turned out to be the most
31 * elegant approach since diferent flash chips use different levels of
32 * granularity and methods to determine protected ranges. In other words,
David Hendrickse0512a72014-07-15 20:30:47 -070033 * be stupid and simple since clever arithmetic will not work for many chips.
David Hendricksf7924d12010-06-10 21:26:44 -070034 */
35
36struct wp_range {
37 unsigned int start; /* starting address */
38 unsigned int len; /* len */
39};
40
41enum bit_state {
42 OFF = 0,
43 ON = 1,
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +080044 X = -1 /* don't care. Must be bigger than max # of bp. */
David Hendricksf7924d12010-06-10 21:26:44 -070045};
46
David Hendrickse0512a72014-07-15 20:30:47 -070047/*
48 * Generic write-protection schema for 25-series SPI flash chips. This assumes
49 * there is a status register that contains one or more consecutive bits which
50 * determine which address range is protected.
51 */
52
53struct status_register_layout {
54 int bp0_pos; /* position of BP0 */
55 int bp_bits; /* number of block protect bits */
56 int srp_pos; /* position of status register protect enable bit */
57};
58
59struct generic_range {
David Hendricks148a4bf2015-03-13 21:02:42 -070060 struct generic_modifier_bits m;
David Hendrickse0512a72014-07-15 20:30:47 -070061 unsigned int bp; /* block protect bitfield */
62 struct wp_range range;
63};
64
65struct generic_wp {
66 struct status_register_layout sr1; /* status register 1 */
67 struct generic_range *ranges;
David Hendricks148a4bf2015-03-13 21:02:42 -070068
69 /*
70 * Some chips store modifier bits in one or more special control
71 * registers instead of the status register like many older SPI NOR
72 * flash chips did. get_modifier_bits() and set_modifier_bits() will do
73 * any chip-specific operations necessary to get/set these bit values.
74 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -070075 int (*get_modifier_bits)(const struct flashctx *flash,
David Hendricks148a4bf2015-03-13 21:02:42 -070076 struct generic_modifier_bits *m);
Souvik Ghoshd75cd672016-06-17 14:21:39 -070077 int (*set_modifier_bits)(const struct flashctx *flash,
David Hendricks148a4bf2015-03-13 21:02:42 -070078 struct generic_modifier_bits *m);
David Hendrickse0512a72014-07-15 20:30:47 -070079};
80
81/*
82 * The following ranges and functions are useful for representing Winbond-
83 * style writeprotect schema in which there are typically 5 bits of
84 * relevant information stored in status register 1:
85 * sec: This bit indicates the units (sectors vs. blocks)
86 * tb: The top-bottom bit indicates if the affected range is at the top of
87 * the flash memory's address space or at the bottom.
Duncan Laurie1801f7c2019-01-09 18:02:51 -080088 * bp: Bitmask representing the number of affected sectors/blocks.
David Hendrickse0512a72014-07-15 20:30:47 -070089 */
David Hendricksf7924d12010-06-10 21:26:44 -070090struct w25q_range {
Duncan Laurie1801f7c2019-01-09 18:02:51 -080091 enum bit_state sec; /* if 1, bp bits describe sectors */
David Hendricksf7924d12010-06-10 21:26:44 -070092 enum bit_state tb; /* top/bottom select */
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +080093 int bp; /* block protect bitfield */
David Hendricksf7924d12010-06-10 21:26:44 -070094 struct wp_range range;
95};
96
David Hendrickse0512a72014-07-15 20:30:47 -070097/*
98 * Mask to extract write-protect enable and range bits
99 * Status register 1:
100 * SRP0: bit 7
101 * range(BP2-BP0): bit 4-2
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800102 * range(BP3-BP0): bit 5-2 (large chips)
David Hendrickse0512a72014-07-15 20:30:47 -0700103 * Status register 2:
104 * SRP1: bit 1
105 */
106#define MASK_WP_AREA (0x9C)
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800107#define MASK_WP_AREA_LARGE (0x9C)
David Hendrickse0512a72014-07-15 20:30:47 -0700108#define MASK_WP2_AREA (0x01)
109
David Hendricks57566ed2010-08-16 18:24:45 -0700110struct w25q_range en25f40_ranges[] = {
111 { X, X, 0, {0, 0} }, /* none */
112 { 0, 0, 0x1, {0x000000, 504 * 1024} },
113 { 0, 0, 0x2, {0x000000, 496 * 1024} },
114 { 0, 0, 0x3, {0x000000, 480 * 1024} },
115 { 0, 0, 0x4, {0x000000, 448 * 1024} },
116 { 0, 0, 0x5, {0x000000, 384 * 1024} },
117 { 0, 0, 0x6, {0x000000, 256 * 1024} },
118 { 0, 0, 0x7, {0x000000, 512 * 1024} },
119};
120
David Hendrickse185bf22011-05-24 15:34:18 -0700121struct w25q_range en25q40_ranges[] = {
122 { 0, 0, 0, {0, 0} }, /* none */
123 { 0, 0, 0x1, {0x000000, 504 * 1024} },
124 { 0, 0, 0x2, {0x000000, 496 * 1024} },
125 { 0, 0, 0x3, {0x000000, 480 * 1024} },
126
127 { 0, 1, 0x0, {0x000000, 448 * 1024} },
128 { 0, 1, 0x1, {0x000000, 384 * 1024} },
129 { 0, 1, 0x2, {0x000000, 256 * 1024} },
130 { 0, 1, 0x3, {0x000000, 512 * 1024} },
131};
132
133struct w25q_range en25q80_ranges[] = {
134 { 0, 0, 0, {0, 0} }, /* none */
135 { 0, 0, 0x1, {0x000000, 1016 * 1024} },
136 { 0, 0, 0x2, {0x000000, 1008 * 1024} },
137 { 0, 0, 0x3, {0x000000, 992 * 1024} },
138 { 0, 0, 0x4, {0x000000, 960 * 1024} },
139 { 0, 0, 0x5, {0x000000, 896 * 1024} },
140 { 0, 0, 0x6, {0x000000, 768 * 1024} },
141 { 0, 0, 0x7, {0x000000, 1024 * 1024} },
142};
143
144struct w25q_range en25q32_ranges[] = {
145 { 0, 0, 0, {0, 0} }, /* none */
146 { 0, 0, 0x1, {0x000000, 4032 * 1024} },
147 { 0, 0, 0x2, {0x000000, 3968 * 1024} },
148 { 0, 0, 0x3, {0x000000, 3840 * 1024} },
149 { 0, 0, 0x4, {0x000000, 3584 * 1024} },
150 { 0, 0, 0x5, {0x000000, 3072 * 1024} },
151 { 0, 0, 0x6, {0x000000, 2048 * 1024} },
152 { 0, 0, 0x7, {0x000000, 4096 * 1024} },
153
154 { 0, 1, 0, {0, 0} }, /* none */
155 { 0, 1, 0x1, {0x010000, 4032 * 1024} },
156 { 0, 1, 0x2, {0x020000, 3968 * 1024} },
157 { 0, 1, 0x3, {0x040000, 3840 * 1024} },
158 { 0, 1, 0x4, {0x080000, 3584 * 1024} },
159 { 0, 1, 0x5, {0x100000, 3072 * 1024} },
160 { 0, 1, 0x6, {0x200000, 2048 * 1024} },
161 { 0, 1, 0x7, {0x000000, 4096 * 1024} },
162};
163
164struct w25q_range en25q64_ranges[] = {
165 { 0, 0, 0, {0, 0} }, /* none */
166 { 0, 0, 0x1, {0x000000, 8128 * 1024} },
167 { 0, 0, 0x2, {0x000000, 8064 * 1024} },
168 { 0, 0, 0x3, {0x000000, 7936 * 1024} },
169 { 0, 0, 0x4, {0x000000, 7680 * 1024} },
170 { 0, 0, 0x5, {0x000000, 7168 * 1024} },
171 { 0, 0, 0x6, {0x000000, 6144 * 1024} },
172 { 0, 0, 0x7, {0x000000, 8192 * 1024} },
173
174 { 0, 1, 0, {0, 0} }, /* none */
175 { 0, 1, 0x1, {0x010000, 8128 * 1024} },
176 { 0, 1, 0x2, {0x020000, 8064 * 1024} },
177 { 0, 1, 0x3, {0x040000, 7936 * 1024} },
178 { 0, 1, 0x4, {0x080000, 7680 * 1024} },
179 { 0, 1, 0x5, {0x100000, 7168 * 1024} },
180 { 0, 1, 0x6, {0x200000, 6144 * 1024} },
181 { 0, 1, 0x7, {0x000000, 8192 * 1024} },
182};
183
184struct w25q_range en25q128_ranges[] = {
185 { 0, 0, 0, {0, 0} }, /* none */
186 { 0, 0, 0x1, {0x000000, 16320 * 1024} },
187 { 0, 0, 0x2, {0x000000, 16256 * 1024} },
188 { 0, 0, 0x3, {0x000000, 16128 * 1024} },
189 { 0, 0, 0x4, {0x000000, 15872 * 1024} },
190 { 0, 0, 0x5, {0x000000, 15360 * 1024} },
191 { 0, 0, 0x6, {0x000000, 14336 * 1024} },
192 { 0, 0, 0x7, {0x000000, 16384 * 1024} },
193
194 { 0, 1, 0, {0, 0} }, /* none */
195 { 0, 1, 0x1, {0x010000, 16320 * 1024} },
196 { 0, 1, 0x2, {0x020000, 16256 * 1024} },
197 { 0, 1, 0x3, {0x040000, 16128 * 1024} },
198 { 0, 1, 0x4, {0x080000, 15872 * 1024} },
199 { 0, 1, 0x5, {0x100000, 15360 * 1024} },
200 { 0, 1, 0x6, {0x200000, 14336 * 1024} },
201 { 0, 1, 0x7, {0x000000, 16384 * 1024} },
202};
203
Marc Jonesb2f90022014-04-29 17:37:23 -0600204struct w25q_range en25s64_ranges[] = {
205 { 0, 0, 0, {0, 0} }, /* none */
206 { 0, 0, 0x1, {0x000000, 8064 * 1024} },
207 { 0, 0, 0x2, {0x000000, 7936 * 1024} },
208 { 0, 0, 0x3, {0x000000, 7680 * 1024} },
209 { 0, 0, 0x4, {0x000000, 7168 * 1024} },
210 { 0, 0, 0x5, {0x000000, 6144 * 1024} },
211 { 0, 0, 0x6, {0x000000, 4096 * 1024} },
212 { 0, 0, 0x7, {0x000000, 8192 * 1024} },
213
214 { 0, 1, 0, {0, 0} }, /* none */
215 { 0, 1, 0x1, {0x7e0000, 128 * 1024} },
216 { 0, 1, 0x2, {0x7c0000, 256 * 1024} },
217 { 0, 1, 0x3, {0x780000, 512 * 1024} },
218 { 0, 1, 0x4, {0x700000, 1024 * 1024} },
219 { 0, 1, 0x5, {0x600000, 2048 * 1024} },
220 { 0, 1, 0x6, {0x400000, 4096 * 1024} },
221 { 0, 1, 0x7, {0x000000, 8192 * 1024} },
222};
223
David Hendricksf8f00c72011-02-01 12:39:46 -0800224/* mx25l1005 ranges also work for the mx25l1005c */
225static struct w25q_range mx25l1005_ranges[] = {
226 { X, X, 0, {0, 0} }, /* none */
227 { X, X, 0x1, {0x010000, 64 * 1024} },
228 { X, X, 0x2, {0x000000, 128 * 1024} },
229 { X, X, 0x3, {0x000000, 128 * 1024} },
230};
231
232static struct w25q_range mx25l2005_ranges[] = {
233 { X, X, 0, {0, 0} }, /* none */
234 { X, X, 0x1, {0x030000, 64 * 1024} },
235 { X, X, 0x2, {0x020000, 128 * 1024} },
236 { X, X, 0x3, {0x000000, 256 * 1024} },
237};
238
239static struct w25q_range mx25l4005_ranges[] = {
240 { X, X, 0, {0, 0} }, /* none */
241 { X, X, 0x1, {0x070000, 64 * 1 * 1024} }, /* block 7 */
242 { X, X, 0x2, {0x060000, 64 * 2 * 1024} }, /* blocks 6-7 */
243 { X, X, 0x3, {0x040000, 64 * 4 * 1024} }, /* blocks 4-7 */
244 { X, X, 0x4, {0x000000, 512 * 1024} },
245 { X, X, 0x5, {0x000000, 512 * 1024} },
246 { X, X, 0x6, {0x000000, 512 * 1024} },
247 { X, X, 0x7, {0x000000, 512 * 1024} },
248};
249
250static struct w25q_range mx25l8005_ranges[] = {
251 { X, X, 0, {0, 0} }, /* none */
252 { X, X, 0x1, {0x0f0000, 64 * 1 * 1024} }, /* block 15 */
253 { X, X, 0x2, {0x0e0000, 64 * 2 * 1024} }, /* blocks 14-15 */
254 { X, X, 0x3, {0x0c0000, 64 * 4 * 1024} }, /* blocks 12-15 */
255 { X, X, 0x4, {0x080000, 64 * 8 * 1024} }, /* blocks 8-15 */
256 { X, X, 0x5, {0x000000, 1024 * 1024} },
257 { X, X, 0x6, {0x000000, 1024 * 1024} },
258 { X, X, 0x7, {0x000000, 1024 * 1024} },
259};
260
261#if 0
262/* FIXME: mx25l1605 has the same IDs as the mx25l1605d */
263static struct w25q_range mx25l1605_ranges[] = {
264 { X, X, 0, {0, 0} }, /* none */
265 { X, X, 0x1, {0x1f0000, 64 * 1024} }, /* block 31 */
266 { X, X, 0x2, {0x1e0000, 128 * 1024} }, /* blocks 30-31 */
267 { X, X, 0x3, {0x1c0000, 256 * 1024} }, /* blocks 28-31 */
268 { X, X, 0x4, {0x180000, 512 * 1024} }, /* blocks 24-31 */
269 { X, X, 0x4, {0x100000, 1024 * 1024} }, /* blocks 16-31 */
270 { X, X, 0x6, {0x000000, 2048 * 1024} },
271 { X, X, 0x7, {0x000000, 2048 * 1024} },
272};
273#endif
274
275#if 0
276/* FIXME: mx25l6405 has the same IDs as the mx25l6405d */
277static struct w25q_range mx25l6405_ranges[] = {
278 { X, 0, 0, {0, 0} }, /* none */
279 { X, 0, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */
280 { X, 0, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
281 { X, 0, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
282 { X, 0, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */
283 { X, 0, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
284 { X, 0, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
285 { X, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
286
287 { X, 1, 0x0, {0x000000, 8192 * 1024} },
288 { X, 1, 0x1, {0x000000, 8192 * 1024} },
289 { X, 1, 0x2, {0x000000, 8192 * 1024} },
290 { X, 1, 0x3, {0x000000, 8192 * 1024} },
291 { X, 1, 0x4, {0x000000, 8192 * 1024} },
292 { X, 1, 0x5, {0x000000, 8192 * 1024} },
293 { X, 1, 0x6, {0x000000, 8192 * 1024} },
294 { X, 1, 0x7, {0x000000, 8192 * 1024} },
295};
296#endif
297
298static struct w25q_range mx25l1605d_ranges[] = {
299 { X, 0, 0, {0, 0} }, /* none */
300 { X, 0, 0x1, {0x1f0000, 64 * 1 * 1024} }, /* block 31 */
301 { X, 0, 0x2, {0x1e0000, 64 * 2 * 1024} }, /* blocks 30-31 */
302 { X, 0, 0x3, {0x1c0000, 64 * 4 * 1024} }, /* blocks 28-31 */
303 { X, 0, 0x4, {0x180000, 64 * 8 * 1024} }, /* blocks 24-31 */
304 { X, 0, 0x5, {0x100000, 64 * 16 * 1024} }, /* blocks 16-31 */
305 { X, 0, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
306 { X, 0, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
307
308 { X, 1, 0x0, {0x000000, 2048 * 1024} },
309 { X, 1, 0x1, {0x000000, 2048 * 1024} },
310 { X, 1, 0x2, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
311 { X, 1, 0x3, {0x000000, 64 * 24 * 1024} }, /* blocks 0-23 */
312 { X, 1, 0x4, {0x000000, 64 * 28 * 1024} }, /* blocks 0-27 */
313 { X, 1, 0x5, {0x000000, 64 * 30 * 1024} }, /* blocks 0-29 */
314 { X, 1, 0x6, {0x000000, 64 * 31 * 1024} }, /* blocks 0-30 */
315 { X, 1, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
316};
317
318/* FIXME: Is there an mx25l3205 (without a trailing letter)? */
David Hendricksac72e362010-08-16 18:20:03 -0700319static struct w25q_range mx25l3205d_ranges[] = {
320 { X, 0, 0, {0, 0} }, /* none */
321 { X, 0, 0x1, {0x3f0000, 64 * 1024} },
322 { X, 0, 0x2, {0x3e0000, 128 * 1024} },
323 { X, 0, 0x3, {0x3c0000, 256 * 1024} },
324 { X, 0, 0x4, {0x380000, 512 * 1024} },
325 { X, 0, 0x5, {0x300000, 1024 * 1024} },
326 { X, 0, 0x6, {0x200000, 2048 * 1024} },
327 { X, 0, 0x7, {0x000000, 4096 * 1024} },
328
329 { X, 1, 0x0, {0x000000, 4096 * 1024} },
330 { X, 1, 0x1, {0x000000, 2048 * 1024} },
331 { X, 1, 0x2, {0x000000, 3072 * 1024} },
332 { X, 1, 0x3, {0x000000, 3584 * 1024} },
333 { X, 1, 0x4, {0x000000, 3840 * 1024} },
334 { X, 1, 0x5, {0x000000, 3968 * 1024} },
335 { X, 1, 0x6, {0x000000, 4032 * 1024} },
336 { X, 1, 0x7, {0x000000, 4096 * 1024} },
337};
338
Vincent Palatin87e092a2013-02-28 15:46:14 -0800339static struct w25q_range mx25u3235e_ranges[] = {
340 { X, 0, 0, {0, 0} }, /* none */
341 { 0, 0, 0x1, {0x3f0000, 64 * 1024} },
342 { 0, 0, 0x2, {0x3e0000, 128 * 1024} },
343 { 0, 0, 0x3, {0x3c0000, 256 * 1024} },
344 { 0, 0, 0x4, {0x380000, 512 * 1024} },
345 { 0, 0, 0x5, {0x300000, 1024 * 1024} },
346 { 0, 0, 0x6, {0x200000, 2048 * 1024} },
347 { 0, 0, 0x7, {0x000000, 4096 * 1024} },
348
349 { 0, 1, 0x0, {0x000000, 4096 * 1024} },
350 { 0, 1, 0x1, {0x000000, 2048 * 1024} },
351 { 0, 1, 0x2, {0x000000, 3072 * 1024} },
352 { 0, 1, 0x3, {0x000000, 3584 * 1024} },
353 { 0, 1, 0x4, {0x000000, 3840 * 1024} },
354 { 0, 1, 0x5, {0x000000, 3968 * 1024} },
355 { 0, 1, 0x6, {0x000000, 4032 * 1024} },
356 { 0, 1, 0x7, {0x000000, 4096 * 1024} },
357};
358
Jongpil66a96492014-08-14 17:59:06 +0900359static struct w25q_range mx25u6435e_ranges[] = {
360 { X, 0, 0, {0, 0} }, /* none */
361 { 0, 0, 0x1, {0x7f0000, 1 * 64 * 1024} }, /* block 127 */
362 { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
363 { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
364 { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
365 { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
366 { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
367 { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
368
369 { 0, 1, 0x0, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
370 { 0, 1, 0x1, {0x000000, 96 * 64 * 1024} }, /* blocks 0-95 */
371 { 0, 1, 0x2, {0x000000, 112 * 64 * 1024} }, /* blocks 0-111 */
372 { 0, 1, 0x3, {0x000000, 120 * 64 * 1024} }, /* blocks 0-119 */
373 { 0, 1, 0x4, {0x000000, 124 * 64 * 1024} }, /* blocks 0-123 */
374 { 0, 1, 0x5, {0x000000, 126 * 64 * 1024} }, /* blocks 0-125 */
375 { 0, 1, 0x6, {0x000000, 127 * 64 * 1024} }, /* blocks 0-126 */
376 { 0, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
377};
378
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600379#define MX25U12835E_TB (1 << 3)
380static struct w25q_range mx25u12835e_tb0_ranges[] = {
Paul Fagerburg90571582019-03-15 11:32:57 -0600381 { X, X, 0, {0, 0} }, /* none */
Alex Lu831c6092017-11-02 23:19:34 -0700382 { 0, 0, 0x1, {0xff0000, 1 * 64 * 1024} }, /* block 255 */
383 { 0, 0, 0x2, {0xfe0000, 2 * 64 * 1024} }, /* blocks 254-255 */
384 { 0, 0, 0x3, {0xfc0000, 4 * 64 * 1024} }, /* blocks 252-255 */
385 { 0, 0, 0x4, {0xf80000, 8 * 64 * 1024} }, /* blocks 248-255 */
386 { 0, 0, 0x5, {0xf00000, 16 * 64 * 1024} }, /* blocks 240-255 */
387 { 0, 0, 0x6, {0xe00000, 32 * 64 * 1024} }, /* blocks 224-255 */
388 { 0, 0, 0x7, {0xc00000, 64 * 64 * 1024} }, /* blocks 192-255 */
Paul Fagerburg90571582019-03-15 11:32:57 -0600389 { 0, 0, 0x8, {0x800000, 128 * 64 * 1024} }, /* blocks 128-255 */
390 { 0, 0, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
391 { 0, 0, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
392 { 0, 0, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
393 { 0, 0, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
394 { 0, 0, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
395 { 0, 0, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
396 { 0, 0, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600397};
Alex Lu831c6092017-11-02 23:19:34 -0700398
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600399static struct w25q_range mx25u12835e_tb1_ranges[] = {
Paul Fagerburg90571582019-03-15 11:32:57 -0600400 { 0, 1, 0x1, {0x000000, 1 * 64 * 1024} }, /* block 0 */
401 { 0, 1, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
402 { 0, 1, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
403 { 0, 1, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
404 { 0, 1, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
405 { 0, 1, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
406 { 0, 1, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
407 { 0, 1, 0x8, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */
408 { 0, 1, 0x9, {0x000000, 256 * 64 * 1024} }, /* blocks all */
409 { 0, 1, 0xa, {0x000000, 256 * 64 * 1024} }, /* blocks all */
410 { 0, 1, 0xb, {0x000000, 256 * 64 * 1024} }, /* blocks all */
411 { 0, 1, 0xc, {0x000000, 256 * 64 * 1024} }, /* blocks all */
412 { 0, 1, 0xd, {0x000000, 256 * 64 * 1024} }, /* blocks all */
413 { 0, 1, 0xe, {0x000000, 256 * 64 * 1024} }, /* blocks all */
414 { 0, 1, 0xf, {0x000000, 256 * 64 * 1024} }, /* blocks all */
Alex Lu831c6092017-11-02 23:19:34 -0700415};
416
David Hendricksbfa624b2012-07-24 12:47:59 -0700417static struct w25q_range n25q064_ranges[] = {
David Hendricksfe9123b2015-04-21 13:18:31 -0700418 /*
419 * Note: For N25Q064, sec (usually in bit position 6) is called BP3
420 * (block protect bit 3). It is only useful when all blocks are to
421 * be write-protected.
422 */
David Hendricks42a549a2015-04-22 11:25:07 -0700423 { 0, 0, 0, {0, 0} }, /* none */
David Hendricksbfa624b2012-07-24 12:47:59 -0700424
425 { 0, 0, 0x1, {0x7f0000, 64 * 1024} }, /* block 127 */
426 { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
427 { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
428 { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
429 { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
430 { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
431 { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
432
David Hendricksfe9123b2015-04-21 13:18:31 -0700433 { 0, 1, 0x1, {0x000000, 64 * 1024} }, /* block 0 */
434 { 0, 1, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */
435 { 0, 1, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */
436 { 0, 1, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */
437 { 0, 1, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */
438 { 0, 1, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */
439 { 0, 1, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
David Hendricksbfa624b2012-07-24 12:47:59 -0700440
441 { X, 1, 0x0, {0x000000, 128 * 64 * 1024} }, /* all */
442 { X, 1, 0x1, {0x000000, 128 * 64 * 1024} }, /* all */
443 { X, 1, 0x2, {0x000000, 128 * 64 * 1024} }, /* all */
444 { X, 1, 0x3, {0x000000, 128 * 64 * 1024} }, /* all */
445 { X, 1, 0x4, {0x000000, 128 * 64 * 1024} }, /* all */
446 { X, 1, 0x5, {0x000000, 128 * 64 * 1024} }, /* all */
447 { X, 1, 0x6, {0x000000, 128 * 64 * 1024} }, /* all */
448 { X, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* all */
449};
450
David Hendricksf7924d12010-06-10 21:26:44 -0700451static struct w25q_range w25q16_ranges[] = {
452 { X, X, 0, {0, 0} }, /* none */
453 { 0, 0, 0x1, {0x1f0000, 64 * 1024} },
454 { 0, 0, 0x2, {0x1e0000, 128 * 1024} },
455 { 0, 0, 0x3, {0x1c0000, 256 * 1024} },
456 { 0, 0, 0x4, {0x180000, 512 * 1024} },
457 { 0, 0, 0x5, {0x100000, 1024 * 1024} },
458
459 { 0, 1, 0x1, {0x000000, 64 * 1024} },
460 { 0, 1, 0x2, {0x000000, 128 * 1024} },
461 { 0, 1, 0x3, {0x000000, 256 * 1024} },
462 { 0, 1, 0x4, {0x000000, 512 * 1024} },
463 { 0, 1, 0x5, {0x000000, 1024 * 1024} },
464 { X, X, 0x6, {0x000000, 2048 * 1024} },
465 { X, X, 0x7, {0x000000, 2048 * 1024} },
466
467 { 1, 0, 0x1, {0x1ff000, 4 * 1024} },
468 { 1, 0, 0x2, {0x1fe000, 8 * 1024} },
469 { 1, 0, 0x3, {0x1fc000, 16 * 1024} },
470 { 1, 0, 0x4, {0x1f8000, 32 * 1024} },
Paul Fagerburg90571582019-03-15 11:32:57 -0600471 { 1, 0, 0x5, {0x1f8000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700472
473 { 1, 1, 0x1, {0x000000, 4 * 1024} },
474 { 1, 1, 0x2, {0x000000, 8 * 1024} },
475 { 1, 1, 0x3, {0x000000, 16 * 1024} },
Paul Fagerburg90571582019-03-15 11:32:57 -0600476 { 1, 1, 0x4, {0x000000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700477 { 1, 1, 0x5, {0x000000, 32 * 1024} },
478};
479
480static struct w25q_range w25q32_ranges[] = {
481 { X, X, 0, {0, 0} }, /* none */
482 { 0, 0, 0x1, {0x3f0000, 64 * 1024} },
483 { 0, 0, 0x2, {0x3e0000, 128 * 1024} },
484 { 0, 0, 0x3, {0x3c0000, 256 * 1024} },
485 { 0, 0, 0x4, {0x380000, 512 * 1024} },
486 { 0, 0, 0x5, {0x300000, 1024 * 1024} },
David Hendricks05653ff2010-06-15 16:05:12 -0700487 { 0, 0, 0x6, {0x200000, 2048 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700488
489 { 0, 1, 0x1, {0x000000, 64 * 1024} },
490 { 0, 1, 0x2, {0x000000, 128 * 1024} },
491 { 0, 1, 0x3, {0x000000, 256 * 1024} },
492 { 0, 1, 0x4, {0x000000, 512 * 1024} },
493 { 0, 1, 0x5, {0x000000, 1024 * 1024} },
494 { 0, 1, 0x6, {0x000000, 2048 * 1024} },
495 { X, X, 0x7, {0x000000, 4096 * 1024} },
496
497 { 1, 0, 0x1, {0x3ff000, 4 * 1024} },
498 { 1, 0, 0x2, {0x3fe000, 8 * 1024} },
499 { 1, 0, 0x3, {0x3fc000, 16 * 1024} },
500 { 1, 0, 0x4, {0x3f8000, 32 * 1024} },
Paul Fagerburg90571582019-03-15 11:32:57 -0600501 { 1, 0, 0x5, {0x3f8000, 32 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700502
503 { 1, 1, 0x1, {0x000000, 4 * 1024} },
504 { 1, 1, 0x2, {0x000000, 8 * 1024} },
505 { 1, 1, 0x3, {0x000000, 16 * 1024} },
506 { 1, 1, 0x4, {0x000000, 32 * 1024} },
507 { 1, 1, 0x5, {0x000000, 32 * 1024} },
508};
509
510static struct w25q_range w25q80_ranges[] = {
511 { X, X, 0, {0, 0} }, /* none */
512 { 0, 0, 0x1, {0x0f0000, 64 * 1024} },
513 { 0, 0, 0x2, {0x0e0000, 128 * 1024} },
514 { 0, 0, 0x3, {0x0c0000, 256 * 1024} },
515 { 0, 0, 0x4, {0x080000, 512 * 1024} },
516
517 { 0, 1, 0x1, {0x000000, 64 * 1024} },
518 { 0, 1, 0x2, {0x000000, 128 * 1024} },
519 { 0, 1, 0x3, {0x000000, 256 * 1024} },
520 { 0, 1, 0x4, {0x000000, 512 * 1024} },
David Hendricks05653ff2010-06-15 16:05:12 -0700521 { X, X, 0x6, {0x000000, 1024 * 1024} },
522 { X, X, 0x7, {0x000000, 1024 * 1024} },
David Hendricksf7924d12010-06-10 21:26:44 -0700523
524 { 1, 0, 0x1, {0x1ff000, 4 * 1024} },
525 { 1, 0, 0x2, {0x1fe000, 8 * 1024} },
526 { 1, 0, 0x3, {0x1fc000, 16 * 1024} },
527 { 1, 0, 0x4, {0x1f8000, 32 * 1024} },
528 { 1, 0, 0x5, {0x1f8000, 32 * 1024} },
529
530 { 1, 1, 0x1, {0x000000, 4 * 1024} },
531 { 1, 1, 0x2, {0x000000, 8 * 1024} },
532 { 1, 1, 0x3, {0x000000, 16 * 1024} },
533 { 1, 1, 0x4, {0x000000, 32 * 1024} },
534 { 1, 1, 0x5, {0x000000, 32 * 1024} },
535};
536
David Hendricks2c4a76c2010-06-28 14:00:43 -0700537static struct w25q_range w25q64_ranges[] = {
538 { X, X, 0, {0, 0} }, /* none */
539
540 { 0, 0, 0x1, {0x7e0000, 128 * 1024} },
541 { 0, 0, 0x2, {0x7c0000, 256 * 1024} },
542 { 0, 0, 0x3, {0x780000, 512 * 1024} },
543 { 0, 0, 0x4, {0x700000, 1024 * 1024} },
544 { 0, 0, 0x5, {0x600000, 2048 * 1024} },
545 { 0, 0, 0x6, {0x400000, 4096 * 1024} },
546
547 { 0, 1, 0x1, {0x000000, 128 * 1024} },
548 { 0, 1, 0x2, {0x000000, 256 * 1024} },
549 { 0, 1, 0x3, {0x000000, 512 * 1024} },
550 { 0, 1, 0x4, {0x000000, 1024 * 1024} },
551 { 0, 1, 0x5, {0x000000, 2048 * 1024} },
552 { 0, 1, 0x6, {0x000000, 4096 * 1024} },
553 { X, X, 0x7, {0x000000, 8192 * 1024} },
554
555 { 1, 0, 0x1, {0x7ff000, 4 * 1024} },
556 { 1, 0, 0x2, {0x7fe000, 8 * 1024} },
557 { 1, 0, 0x3, {0x7fc000, 16 * 1024} },
558 { 1, 0, 0x4, {0x7f8000, 32 * 1024} },
559 { 1, 0, 0x5, {0x7f8000, 32 * 1024} },
560
561 { 1, 1, 0x1, {0x000000, 4 * 1024} },
562 { 1, 1, 0x2, {0x000000, 8 * 1024} },
563 { 1, 1, 0x3, {0x000000, 16 * 1024} },
564 { 1, 1, 0x4, {0x000000, 32 * 1024} },
565 { 1, 1, 0x5, {0x000000, 32 * 1024} },
566};
567
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700568static struct w25q_range w25rq128_cmp0_ranges[] = {
569 { X, X, 0, {0, 0} }, /* NONE */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530570
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700571 { 0, 0, 0x1, {0xfc0000, 256 * 1024} }, /* Upper 1/64 */
572 { 0, 0, 0x2, {0xf80000, 512 * 1024} }, /* Upper 1/32 */
573 { 0, 0, 0x3, {0xf00000, 1024 * 1024} }, /* Upper 1/16 */
574 { 0, 0, 0x4, {0xe00000, 2048 * 1024} }, /* Upper 1/8 */
575 { 0, 0, 0x5, {0xc00000, 4096 * 1024} }, /* Upper 1/4 */
576 { 0, 0, 0x6, {0x800000, 8192 * 1024} }, /* Upper 1/2 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530577
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700578 { 0, 1, 0x1, {0x000000, 256 * 1024} }, /* Lower 1/64 */
579 { 0, 1, 0x2, {0x000000, 512 * 1024} }, /* Lower 1/32 */
580 { 0, 1, 0x3, {0x000000, 1024 * 1024} }, /* Lower 1/16 */
581 { 0, 1, 0x4, {0x000000, 2048 * 1024} }, /* Lower 1/8 */
582 { 0, 1, 0x5, {0x000000, 4096 * 1024} }, /* Lower 1/4 */
583 { 0, 1, 0x6, {0x000000, 8192 * 1024} }, /* Lower 1/2 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530584
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700585 { X, X, 0x7, {0x000000, 16384 * 1024} }, /* ALL */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530586
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700587 { 1, 0, 0x1, {0xfff000, 4 * 1024} }, /* Upper 1/4096 */
588 { 1, 0, 0x2, {0xffe000, 8 * 1024} }, /* Upper 1/2048 */
589 { 1, 0, 0x3, {0xffc000, 16 * 1024} }, /* Upper 1/1024 */
590 { 1, 0, 0x4, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
591 { 1, 0, 0x5, {0xff8000, 32 * 1024} }, /* Upper 1/512 */
592
593 { 1, 1, 0x1, {0x000000, 4 * 1024} }, /* Lower 1/4096 */
594 { 1, 1, 0x2, {0x000000, 8 * 1024} }, /* Lower 1/2048 */
595 { 1, 1, 0x3, {0x000000, 16 * 1024} }, /* Lower 1/1024 */
596 { 1, 1, 0x4, {0x000000, 32 * 1024} }, /* Lower 1/512 */
597 { 1, 1, 0x5, {0x000000, 32 * 1024} }, /* Lower 1/512 */
598};
599
600static struct w25q_range w25rq128_cmp1_ranges[] = {
601 { X, X, 0x0, {0x000000, 16 * 1024 * 1024} }, /* ALL */
602
603 { 0, 0, 0x1, {0x000000, 16128 * 1024} }, /* Lower 63/64 */
604 { 0, 0, 0x2, {0x000000, 15872 * 1024} }, /* Lower 31/32 */
605 { 0, 0, 0x3, {0x000000, 15 * 1024 * 1024} }, /* Lower 15/16 */
606 { 0, 0, 0x4, {0x000000, 14 * 1024 * 1024} }, /* Lower 7/8 */
607 { 0, 0, 0x5, {0x000000, 12 * 1024 * 1024} }, /* Lower 3/4 */
608 { 0, 0, 0x6, {0x000000, 8 * 1024 * 1024} }, /* Lower 1/2 */
609
610 { 0, 1, 0x1, {0x040000, 16128 * 1024} }, /* Upper 63/64 */
611 { 0, 1, 0x2, {0x080000, 15872 * 1024} }, /* Upper 31/32 */
612 { 0, 1, 0x3, {0x100000, 15 * 1024 * 1024} }, /* Upper 15/16 */
613 { 0, 1, 0x4, {0x200000, 14 * 1024 * 1024} }, /* Upper 7/8 */
614 { 0, 1, 0x5, {0x400000, 12 * 1024 * 1024} }, /* Upper 3/4 */
615 { 0, 1, 0x6, {0x800000, 8 * 1024 * 1024} }, /* Upper 1/2 */
616
617 { X, X, 0x7, {0x000000, 0} }, /* NONE */
618
619 { 1, 0, 0x1, {0x000000, 16380 * 1024} }, /* Lower 4095/4096 */
620 { 1, 0, 0x2, {0x000000, 16376 * 1024} }, /* Lower 2048/2048 */
621 { 1, 0, 0x3, {0x000000, 16368 * 1024} }, /* Lower 1023/1024 */
622 { 1, 0, 0x4, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
623 { 1, 0, 0x5, {0x000000, 16352 * 1024} }, /* Lower 511/512 */
624
625 { 1, 1, 0x1, {0x001000, 16380 * 1024} }, /* Upper 4095/4096 */
626 { 1, 1, 0x2, {0x002000, 16376 * 1024} }, /* Upper 2047/2048 */
627 { 1, 1, 0x3, {0x004000, 16368 * 1024} }, /* Upper 1023/1024 */
628 { 1, 1, 0x4, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
629 { 1, 1, 0x5, {0x008000, 16352 * 1024} }, /* Upper 511/512 */
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530630};
631
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800632static struct w25q_range w25rq256_cmp0_ranges[] = {
633 { X, X, 0x0, {0x0000000, 0x0000000} }, /* NONE */
634
635 { X, 0, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* Upper 1/512 */
636 { X, 0, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* Upper 1/256 */
637 { X, 0, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* Upper 1/128 */
638 { X, 0, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* Upper 1/64 */
639 { X, 0, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* Upper 1/32 */
640 { X, 0, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* Upper 1/16 */
641 { X, 0, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* Upper 1/8 */
642 { X, 0, 0x8, {0x1800000, 64 * 128 * 1024} }, /* Upper 1/4 */
643 { X, 0, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
644
645 { X, 1, 0x1, {0x0000000, 64 * 1 * 1024} }, /* Lower 1/512 */
646 { X, 1, 0x2, {0x0000000, 64 * 2 * 1024} }, /* Lower 1/256 */
647 { X, 1, 0x3, {0x0000000, 64 * 4 * 1024} }, /* Lower 1/128 */
648 { X, 1, 0x4, {0x0000000, 64 * 8 * 1024} }, /* Lower 1/64 */
649 { X, 1, 0x5, {0x0000000, 64 * 16 * 1024} }, /* Lower 1/32 */
650 { X, 1, 0x6, {0x0000000, 64 * 32 * 1024} }, /* Lower 1/16 */
651 { X, 1, 0x7, {0x0000000, 64 * 64 * 1024} }, /* Lower 1/8 */
652 { X, 1, 0x8, {0x0000000, 64 * 128 * 1024} }, /* Lower 1/4 */
653 { X, 1, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
654
655 { X, X, 0xa, {0x0000000, 64 * 512 * 1024} }, /* ALL */
656 { X, X, 0xb, {0x0000000, 64 * 512 * 1024} }, /* ALL */
657 { X, X, 0xc, {0x0000000, 64 * 512 * 1024} }, /* ALL */
658 { X, X, 0xd, {0x0000000, 64 * 512 * 1024} }, /* ALL */
659 { X, X, 0xe, {0x0000000, 64 * 512 * 1024} }, /* ALL */
660 { X, X, 0xf, {0x0000000, 64 * 512 * 1024} }, /* ALL */
661};
662
663static struct w25q_range w25rq256_cmp1_ranges[] = {
664 { X, X, 0x0, {0x0000000, 64 * 512 * 1024} }, /* ALL */
665
666 { X, 0, 0x1, {0x0000000, 64 * 511 * 1024} }, /* Lower 511/512 */
667 { X, 0, 0x2, {0x0000000, 64 * 510 * 1024} }, /* Lower 255/256 */
668 { X, 0, 0x3, {0x0000000, 64 * 508 * 1024} }, /* Lower 127/128 */
669 { X, 0, 0x4, {0x0000000, 64 * 504 * 1024} }, /* Lower 63/64 */
670 { X, 0, 0x5, {0x0000000, 64 * 496 * 1024} }, /* Lower 31/32 */
671 { X, 0, 0x6, {0x0000000, 64 * 480 * 1024} }, /* Lower 15/16 */
672 { X, 0, 0x7, {0x0000000, 64 * 448 * 1024} }, /* Lower 7/8 */
673 { X, 0, 0x8, {0x0000000, 64 * 384 * 1024} }, /* Lower 3/4 */
674 { X, 0, 0x9, {0x0000000, 64 * 256 * 1024} }, /* Lower 1/2 */
675
676 { X, 1, 0x1, {0x0010000, 64 * 511 * 1024} }, /* Upper 511/512 */
677 { X, 1, 0x2, {0x0020000, 64 * 510 * 1024} }, /* Upper 255/256 */
678 { X, 1, 0x3, {0x0040000, 64 * 508 * 1024} }, /* Upper 127/128 */
679 { X, 1, 0x4, {0x0080000, 64 * 504 * 1024} }, /* Upper 63/64 */
680 { X, 1, 0x5, {0x0100000, 64 * 496 * 1024} }, /* Upper 31/32 */
681 { X, 1, 0x6, {0x0200000, 64 * 480 * 1024} }, /* Upper 15/16 */
682 { X, 1, 0x7, {0x0400000, 64 * 448 * 1024} }, /* Upper 7/8 */
683 { X, 1, 0x8, {0x0800000, 64 * 384 * 1024} }, /* Upper 3/4 */
684 { X, 1, 0x9, {0x1000000, 64 * 256 * 1024} }, /* Upper 1/2 */
685
686 { X, X, 0xa, {0x0000000, 0x0000000} }, /* NONE */
687 { X, X, 0xb, {0x0000000, 0x0000000} }, /* NONE */
688 { X, X, 0xc, {0x0000000, 0x0000000} }, /* NONE */
689 { X, X, 0xd, {0x0000000, 0x0000000} }, /* NONE */
690 { X, X, 0xe, {0x0000000, 0x0000000} }, /* NONE */
691 { X, X, 0xf, {0x0000000, 0x0000000} }, /* NONE */
692};
693
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800694struct w25q_range w25x10_ranges[] = {
695 { X, X, 0, {0, 0} }, /* none */
696 { 0, 0, 0x1, {0x010000, 64 * 1024} },
697 { 0, 1, 0x1, {0x000000, 64 * 1024} },
698 { X, X, 0x2, {0x000000, 128 * 1024} },
699 { X, X, 0x3, {0x000000, 128 * 1024} },
700};
701
702struct w25q_range w25x20_ranges[] = {
703 { X, X, 0, {0, 0} }, /* none */
704 { 0, 0, 0x1, {0x030000, 64 * 1024} },
705 { 0, 0, 0x2, {0x020000, 128 * 1024} },
706 { 0, 1, 0x1, {0x000000, 64 * 1024} },
707 { 0, 1, 0x2, {0x000000, 128 * 1024} },
708 { 0, X, 0x3, {0x000000, 256 * 1024} },
709};
710
David Hendricks470ca952010-08-13 14:01:53 -0700711struct w25q_range w25x40_ranges[] = {
712 { X, X, 0, {0, 0} }, /* none */
713 { 0, 0, 0x1, {0x070000, 64 * 1024} },
714 { 0, 0, 0x2, {0x060000, 128 * 1024} },
715 { 0, 0, 0x3, {0x040000, 256 * 1024} },
716 { 0, 1, 0x1, {0x000000, 64 * 1024} },
717 { 0, 1, 0x2, {0x000000, 128 * 1024} },
718 { 0, 1, 0x3, {0x000000, 256 * 1024} },
719 { 0, X, 0x4, {0x000000, 512 * 1024} },
David Hendricksb389abb2016-06-17 16:47:00 -0700720 { 0, X, 0x5, {0x000000, 512 * 1024} },
721 { 0, X, 0x6, {0x000000, 512 * 1024} },
722 { 0, X, 0x7, {0x000000, 512 * 1024} },
David Hendricks470ca952010-08-13 14:01:53 -0700723};
724
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800725struct w25q_range w25x80_ranges[] = {
726 { X, X, 0, {0, 0} }, /* none */
727 { 0, 0, 0x1, {0x0F0000, 64 * 1024} },
728 { 0, 0, 0x2, {0x0E0000, 128 * 1024} },
729 { 0, 0, 0x3, {0x0C0000, 256 * 1024} },
730 { 0, 0, 0x4, {0x080000, 512 * 1024} },
731 { 0, 1, 0x1, {0x000000, 64 * 1024} },
732 { 0, 1, 0x2, {0x000000, 128 * 1024} },
733 { 0, 1, 0x3, {0x000000, 256 * 1024} },
734 { 0, 1, 0x4, {0x000000, 512 * 1024} },
735 { 0, X, 0x5, {0x000000, 1024 * 1024} },
736 { 0, X, 0x6, {0x000000, 1024 * 1024} },
737 { 0, X, 0x7, {0x000000, 1024 * 1024} },
738};
739
Martin Rothf3c3d5f2017-04-28 14:56:41 -0600740static struct w25q_range gd25q40_cmp0_ranges[] = {
741 { X, X, 0, {0, 0} }, /* None */
742 { 0, 0, 0x1, {0x070000, 64 * 1024} },
743 { 0, 0, 0x2, {0x060000, 128 * 1024} },
744 { 0, 0, 0x3, {0x040000, 256 * 1024} },
745 { 0, 1, 0x1, {0x000000, 64 * 1024} },
746 { 0, 1, 0x2, {0x000000, 128 * 1024} },
747 { 0, 1, 0x3, {0x000000, 256 * 1024} },
748 { 0, X, 0x4, {0x000000, 512 * 1024} }, /* All */
749 { 0, X, 0x5, {0x000000, 512 * 1024} }, /* All */
750 { 0, X, 0x6, {0x000000, 512 * 1024} }, /* All */
751 { 0, X, 0x7, {0x000000, 512 * 1024} }, /* All */
752 { 1, 0, 0x1, {0x07F000, 4 * 1024} },
753 { 1, 0, 0x2, {0x07E000, 8 * 1024} },
754 { 1, 0, 0x3, {0x07C000, 16 * 1024} },
755 { 1, 0, 0x4, {0x078000, 32 * 1024} },
756 { 1, 0, 0x5, {0x078000, 32 * 1024} },
757 { 1, 0, 0x6, {0x078000, 32 * 1024} },
758 { 1, 1, 0x1, {0x000000, 4 * 1024} },
759 { 1, 1, 0x2, {0x000000, 8 * 1024} },
760 { 1, 1, 0x3, {0x000000, 16 * 1024} },
761 { 1, 1, 0x4, {0x000000, 32 * 1024} },
762 { 1, 1, 0x5, {0x000000, 32 * 1024} },
763 { 1, 1, 0x6, {0x000000, 32 * 1024} },
764 { 1, X, 0x7, {0x000000, 512 * 1024} }, /* All */
765};
766
767static struct w25q_range gd25q40_cmp1_ranges[] = {
768 { X, X, 0x0, {0x000000, 512 * 1024} }, /* ALL */
769 { 0, 0, 0x1, {0x000000, 448 * 1024} },
770 { 0, 0, 0x2, {0x000000, 384 * 1024} },
771 { 0, 0, 0x3, {0x000000, 256 * 1024} },
772
773 { 0, 1, 0x1, {0x010000, 448 * 1024} },
774 { 0, 1, 0x2, {0x020000, 384 * 1024} },
775 { 0, 1, 0x3, {0x040000, 256 * 1024} },
776
777 { 0, X, 0x4, {0x000000, 0} }, /* None */
778 { 0, X, 0x5, {0x000000, 0} }, /* None */
779 { 0, X, 0x6, {0x000000, 0} }, /* None */
780 { 0, X, 0x7, {0x000000, 0} }, /* None */
781
782 { 1, 0, 0x1, {0x000000, 508 * 1024} },
783 { 1, 0, 0x2, {0x000000, 504 * 1024} },
784 { 1, 0, 0x3, {0x000000, 496 * 1024} },
785 { 1, 0, 0x4, {0x000000, 480 * 1024} },
786 { 1, 0, 0x5, {0x000000, 480 * 1024} },
787 { 1, 0, 0x6, {0x000000, 480 * 1024} },
788
789 { 1, 1, 0x1, {0x001000, 508 * 1024} },
790 { 1, 1, 0x2, {0x002000, 504 * 1024} },
791 { 1, 1, 0x3, {0x004000, 496 * 1024} },
792 { 1, 1, 0x4, {0x008000, 480 * 1024} },
793 { 1, 1, 0x5, {0x008000, 480 * 1024} },
794 { 1, 1, 0x6, {0x008000, 480 * 1024} },
795
796 { 1, X, 0x7, {0x000000, 0} }, /* None */
797};
798
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -0700799static struct w25q_range gd25q64_ranges[] = {
800 { X, X, 0, {0, 0} }, /* none */
801 { 0, 0, 0x1, {0x7e0000, 128 * 1024} },
802 { 0, 0, 0x2, {0x7c0000, 256 * 1024} },
803 { 0, 0, 0x3, {0x780000, 512 * 1024} },
804 { 0, 0, 0x4, {0x700000, 1024 * 1024} },
805 { 0, 0, 0x5, {0x600000, 2048 * 1024} },
806 { 0, 0, 0x6, {0x400000, 4096 * 1024} },
807
808 { 0, 1, 0x1, {0x000000, 128 * 1024} },
809 { 0, 1, 0x2, {0x000000, 256 * 1024} },
810 { 0, 1, 0x3, {0x000000, 512 * 1024} },
811 { 0, 1, 0x4, {0x000000, 1024 * 1024} },
812 { 0, 1, 0x5, {0x000000, 2048 * 1024} },
813 { 0, 1, 0x6, {0x000000, 4096 * 1024} },
814 { X, X, 0x7, {0x000000, 8192 * 1024} },
815
816 { 1, 0, 0x1, {0x7ff000, 4 * 1024} },
817 { 1, 0, 0x2, {0x7fe000, 8 * 1024} },
818 { 1, 0, 0x3, {0x7fc000, 16 * 1024} },
819 { 1, 0, 0x4, {0x7f8000, 32 * 1024} },
820 { 1, 0, 0x5, {0x7f8000, 32 * 1024} },
821 { 1, 0, 0x6, {0x7f8000, 32 * 1024} },
822
823 { 1, 1, 0x1, {0x000000, 4 * 1024} },
824 { 1, 1, 0x2, {0x000000, 8 * 1024} },
825 { 1, 1, 0x3, {0x000000, 16 * 1024} },
826 { 1, 1, 0x4, {0x000000, 32 * 1024} },
827 { 1, 1, 0x5, {0x000000, 32 * 1024} },
828 { 1, 1, 0x6, {0x000000, 32 * 1024} },
829};
830
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +0800831static struct w25q_range a25l040_ranges[] = {
832 { X, X, 0x0, {0, 0} }, /* none */
833 { X, X, 0x1, {0x70000, 64 * 1024} },
834 { X, X, 0x2, {0x60000, 128 * 1024} },
835 { X, X, 0x3, {0x40000, 256 * 1024} },
836 { X, X, 0x4, {0x00000, 512 * 1024} },
837 { X, X, 0x5, {0x00000, 512 * 1024} },
838 { X, X, 0x6, {0x00000, 512 * 1024} },
839 { X, X, 0x7, {0x00000, 512 * 1024} },
840};
841
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700842static uint8_t do_read_status(const struct flashctx *flash)
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530843{
Patrick Georgif3fa2992017-02-02 16:24:44 +0100844 if (flash->chip->read_status)
845 return flash->chip->read_status(flash);
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530846 else
847 return spi_read_status_register(flash);
848}
849
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700850static int do_write_status(const struct flashctx *flash, int status)
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530851{
Patrick Georgif3fa2992017-02-02 16:24:44 +0100852 if (flash->chip->write_status)
853 return flash->chip->write_status(flash, status);
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530854 else
855 return spi_write_status_register(flash, status);
856}
857
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700858/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700859static uint8_t w25q_read_status_register_2(const struct flashctx *flash)
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700860{
861 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x35 };
862 unsigned char readarr[2];
863 int ret;
864
865 /* Read Status Register */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700866 ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700867 if (ret) {
868 /*
869 * FIXME: make this a benign failure for now in case we are
870 * unable to execute the opcode
871 */
872 msg_cdbg("RDSR2 failed!\n");
873 readarr[0] = 0x00;
874 }
875
876 return readarr[0];
877}
878
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600879/* FIXME: Move to spi25.c if it's a JEDEC standard opcode */
880uint8_t mx25l_read_config_register(const struct flashctx *flash)
881{
882 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x15 };
883 unsigned char readarr[2]; /* leave room for dummy byte */
884 int ret;
885
886 ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
887 if (ret) {
888 msg_cdbg("RDCR failed!\n");
889 readarr[0] = 0x00;
890 }
891
892 return readarr[0];
893}
894
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800895/* Given a flash chip, this function returns its range table. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700896static int w25_range_table(const struct flashctx *flash,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800897 struct w25q_range **w25q_ranges,
898 int *num_entries)
David Hendricksf7924d12010-06-10 21:26:44 -0700899{
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -0600900 uint8_t cr;
901
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800902 *w25q_ranges = 0;
903 *num_entries = 0;
David Hendricksf7924d12010-06-10 21:26:44 -0700904
Patrick Georgif3fa2992017-02-02 16:24:44 +0100905 switch (flash->chip->manufacture_id) {
David Hendricksd494b0a2010-08-16 16:28:50 -0700906 case WINBOND_NEX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +0100907 switch(flash->chip->model_id) {
David Hendricksc801adb2010-12-09 16:58:56 -0800908 case WINBOND_NEX_W25X10:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800909 *w25q_ranges = w25x10_ranges;
910 *num_entries = ARRAY_SIZE(w25x10_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800911 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800912 case WINBOND_NEX_W25X20:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800913 *w25q_ranges = w25x20_ranges;
914 *num_entries = ARRAY_SIZE(w25x20_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800915 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800916 case WINBOND_NEX_W25X40:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800917 *w25q_ranges = w25x40_ranges;
918 *num_entries = ARRAY_SIZE(w25x40_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700919 break;
David Hendricksc801adb2010-12-09 16:58:56 -0800920 case WINBOND_NEX_W25X80:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800921 *w25q_ranges = w25x80_ranges;
922 *num_entries = ARRAY_SIZE(w25x80_ranges);
Louis Yung-Chieh Lo232951f2010-09-16 11:30:00 +0800923 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100924 case WINBOND_NEX_W25Q80_V:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800925 *w25q_ranges = w25q80_ranges;
926 *num_entries = ARRAY_SIZE(w25q80_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700927 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100928 case WINBOND_NEX_W25Q16_V:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800929 *w25q_ranges = w25q16_ranges;
930 *num_entries = ARRAY_SIZE(w25q16_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700931 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100932 case WINBOND_NEX_W25Q32_V:
933 case WINBOND_NEX_W25Q32_W:
Edward O'Callaghand80cf712019-05-24 22:06:36 +1000934 case WINBOND_NEX_W25Q32JW:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800935 *w25q_ranges = w25q32_ranges;
936 *num_entries = ARRAY_SIZE(w25q32_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700937 break;
Patrick Georgicc04a452017-02-06 12:14:43 +0100938 case WINBOND_NEX_W25Q64_V:
939 case WINBOND_NEX_W25Q64_W:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800940 *w25q_ranges = w25q64_ranges;
941 *num_entries = ARRAY_SIZE(w25q64_ranges);
David Hendricksd494b0a2010-08-16 16:28:50 -0700942 break;
Edward O'Callaghan517cb822019-11-21 14:08:32 +1100943 case WINBOND_NEX_W25Q128_DTR:
Alan Green77a95de2019-07-01 16:40:39 +1000944 case WINBOND_NEX_W25Q128_V_M:
Patrick Georgicc04a452017-02-06 12:14:43 +0100945 case WINBOND_NEX_W25Q128_V:
946 case WINBOND_NEX_W25Q128_W:
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700947 if (w25q_read_status_register_2(flash) & (1 << 6)) {
Duncan Laurieed32d7b2015-05-27 11:28:18 -0700948 /* CMP == 1 */
949 *w25q_ranges = w25rq128_cmp1_ranges;
950 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
951 } else {
952 /* CMP == 0 */
953 *w25q_ranges = w25rq128_cmp0_ranges;
954 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
955 }
Ramya Vijaykumare6a7ca82015-05-12 14:27:29 +0530956 break;
Alan Green77a95de2019-07-01 16:40:39 +1000957 case WINBOND_NEX_W25Q256JV_M:
Duncan Laurie1801f7c2019-01-09 18:02:51 -0800958 if (w25q_read_status_register_2(flash) & (1 << 6)) {
959 /* CMP == 1 */
960 *w25q_ranges = w25rq256_cmp1_ranges;
961 *num_entries = ARRAY_SIZE(w25rq256_cmp1_ranges);
962 } else {
963 /* CMP == 0 */
964 *w25q_ranges = w25rq256_cmp0_ranges;
965 *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
966 }
967 break;
David Hendricksd494b0a2010-08-16 16:28:50 -0700968 default:
969 msg_cerr("%s() %d: WINBOND flash chip mismatch (0x%04x)"
970 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +0100971 flash->chip->model_id);
David Hendricksd494b0a2010-08-16 16:28:50 -0700972 return -1;
973 }
David Hendricks2c4a76c2010-06-28 14:00:43 -0700974 break;
David Hendricks57566ed2010-08-16 18:24:45 -0700975 case EON_ID_NOPREFIX:
Patrick Georgif3fa2992017-02-02 16:24:44 +0100976 switch (flash->chip->model_id) {
David Hendricksc801adb2010-12-09 16:58:56 -0800977 case EON_EN25F40:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +0800978 *w25q_ranges = en25f40_ranges;
979 *num_entries = ARRAY_SIZE(en25f40_ranges);
David Hendricks57566ed2010-08-16 18:24:45 -0700980 break;
David Hendrickse185bf22011-05-24 15:34:18 -0700981 case EON_EN25Q40:
982 *w25q_ranges = en25q40_ranges;
983 *num_entries = ARRAY_SIZE(en25q40_ranges);
984 break;
985 case EON_EN25Q80:
986 *w25q_ranges = en25q80_ranges;
987 *num_entries = ARRAY_SIZE(en25q80_ranges);
988 break;
989 case EON_EN25Q32:
990 *w25q_ranges = en25q32_ranges;
991 *num_entries = ARRAY_SIZE(en25q32_ranges);
992 break;
993 case EON_EN25Q64:
994 *w25q_ranges = en25q64_ranges;
995 *num_entries = ARRAY_SIZE(en25q64_ranges);
996 break;
997 case EON_EN25Q128:
998 *w25q_ranges = en25q128_ranges;
999 *num_entries = ARRAY_SIZE(en25q128_ranges);
1000 break;
Marc Jonesb2f90022014-04-29 17:37:23 -06001001 case EON_EN25S64:
1002 *w25q_ranges = en25s64_ranges;
1003 *num_entries = ARRAY_SIZE(en25s64_ranges);
1004 break;
David Hendricks57566ed2010-08-16 18:24:45 -07001005 default:
1006 msg_cerr("%s():%d: EON flash chip mismatch (0x%04x)"
1007 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001008 flash->chip->model_id);
David Hendricks57566ed2010-08-16 18:24:45 -07001009 return -1;
1010 }
1011 break;
David Hendricksc801adb2010-12-09 16:58:56 -08001012 case MACRONIX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001013 switch (flash->chip->model_id) {
David Hendricksf8f00c72011-02-01 12:39:46 -08001014 case MACRONIX_MX25L1005:
1015 *w25q_ranges = mx25l1005_ranges;
1016 *num_entries = ARRAY_SIZE(mx25l1005_ranges);
1017 break;
1018 case MACRONIX_MX25L2005:
1019 *w25q_ranges = mx25l2005_ranges;
1020 *num_entries = ARRAY_SIZE(mx25l2005_ranges);
1021 break;
1022 case MACRONIX_MX25L4005:
1023 *w25q_ranges = mx25l4005_ranges;
1024 *num_entries = ARRAY_SIZE(mx25l4005_ranges);
1025 break;
1026 case MACRONIX_MX25L8005:
1027 *w25q_ranges = mx25l8005_ranges;
1028 *num_entries = ARRAY_SIZE(mx25l8005_ranges);
1029 break;
1030 case MACRONIX_MX25L1605:
1031 /* FIXME: MX25L1605 and MX25L1605D have different write
1032 * protection capabilities, but share IDs */
1033 *w25q_ranges = mx25l1605d_ranges;
1034 *num_entries = ARRAY_SIZE(mx25l1605d_ranges);
1035 break;
David Hendricksc801adb2010-12-09 16:58:56 -08001036 case MACRONIX_MX25L3205:
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001037 *w25q_ranges = mx25l3205d_ranges;
1038 *num_entries = ARRAY_SIZE(mx25l3205d_ranges);
David Hendricksac72e362010-08-16 18:20:03 -07001039 break;
Vincent Palatin87e092a2013-02-28 15:46:14 -08001040 case MACRONIX_MX25U3235E:
1041 *w25q_ranges = mx25u3235e_ranges;
1042 *num_entries = ARRAY_SIZE(mx25u3235e_ranges);
1043 break;
Jongpil66a96492014-08-14 17:59:06 +09001044 case MACRONIX_MX25U6435E:
1045 *w25q_ranges = mx25u6435e_ranges;
1046 *num_entries = ARRAY_SIZE(mx25u6435e_ranges);
1047 break;
Alan Greendc0792e2019-07-01 15:01:34 +10001048 case MACRONIX_MX25U12835E:
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001049 cr = mx25l_read_config_register(flash);
1050 if (cr & MX25U12835E_TB) { /* T/B == 1 */
1051 *w25q_ranges = mx25u12835e_tb1_ranges;
1052 *num_entries = ARRAY_SIZE(mx25u12835e_tb1_ranges);
1053 } else { /* T/B == 0 */
1054 *w25q_ranges = mx25u12835e_tb0_ranges;
1055 *num_entries = ARRAY_SIZE(mx25u12835e_tb0_ranges);
1056 }
Alex Lu831c6092017-11-02 23:19:34 -07001057 break;
David Hendricksac72e362010-08-16 18:20:03 -07001058 default:
1059 msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
1060 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001061 flash->chip->model_id);
David Hendricksac72e362010-08-16 18:20:03 -07001062 return -1;
1063 }
1064 break;
David Hendricksbfa624b2012-07-24 12:47:59 -07001065 case ST_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001066 switch(flash->chip->model_id) {
David Hendricksbfa624b2012-07-24 12:47:59 -07001067 case ST_N25Q064__1E:
1068 case ST_N25Q064__3E:
1069 *w25q_ranges = n25q064_ranges;
1070 *num_entries = ARRAY_SIZE(n25q064_ranges);
1071 break;
1072 default:
1073 msg_cerr("%s() %d: Micron flash chip mismatch"
1074 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001075 flash->chip->model_id);
David Hendricksbfa624b2012-07-24 12:47:59 -07001076 return -1;
1077 }
1078 break;
Bryan Freed9a0051f2012-05-22 16:06:09 -07001079 case GIGADEVICE_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001080 switch(flash->chip->model_id) {
Bryan Freed9a0051f2012-05-22 16:06:09 -07001081 case GIGADEVICE_GD25LQ32:
1082 *w25q_ranges = w25q32_ranges;
1083 *num_entries = ARRAY_SIZE(w25q32_ranges);
1084 break;
Martin Rothf3c3d5f2017-04-28 14:56:41 -06001085 case GIGADEVICE_GD25Q40:
1086 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1087 /* CMP == 1 */
1088 *w25q_ranges = gd25q40_cmp1_ranges;
1089 *num_entries = ARRAY_SIZE(gd25q40_cmp1_ranges);
1090 } else {
1091 *w25q_ranges = gd25q40_cmp0_ranges;
1092 *num_entries = ARRAY_SIZE(gd25q40_cmp0_ranges);
1093 }
1094 break;
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -07001095 case GIGADEVICE_GD25Q64:
Marc Jonesb18734f2014-04-03 16:19:47 -06001096 case GIGADEVICE_GD25LQ64:
Shawn Nematbakhsh9e8ef492012-09-01 21:58:03 -07001097 *w25q_ranges = gd25q64_ranges;
1098 *num_entries = ARRAY_SIZE(gd25q64_ranges);
1099 break;
Martin Roth1fd87ed2017-02-27 20:50:50 -07001100 case GIGADEVICE_GD25Q128:
Aaron Durbin6c957d72018-08-20 09:31:01 -06001101 case GIGADEVICE_GD25LQ128CD:
Martin Roth1fd87ed2017-02-27 20:50:50 -07001102 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1103 /* CMP == 1 */
1104 *w25q_ranges = w25rq128_cmp1_ranges;
1105 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
1106 } else {
1107 /* CMP == 0 */
1108 *w25q_ranges = w25rq128_cmp0_ranges;
1109 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
1110 }
1111 break;
Duncan Laurie0c383552019-03-16 12:35:16 -07001112 case GIGADEVICE_GD25Q256D:
1113 *w25q_ranges = w25rq256_cmp0_ranges;
1114 *num_entries = ARRAY_SIZE(w25rq256_cmp0_ranges);
1115 break;
Bryan Freed9a0051f2012-05-22 16:06:09 -07001116 default:
1117 msg_cerr("%s() %d: GigaDevice flash chip mismatch"
1118 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001119 flash->chip->model_id);
Bryan Freed9a0051f2012-05-22 16:06:09 -07001120 return -1;
1121 }
1122 break;
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001123 case AMIC_ID_NOPREFIX:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001124 switch(flash->chip->model_id) {
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001125 case AMIC_A25L040:
1126 *w25q_ranges = a25l040_ranges;
1127 *num_entries = ARRAY_SIZE(a25l040_ranges);
1128 break;
1129 default:
1130 msg_cerr("%s() %d: AMIC flash chip mismatch"
1131 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001132 flash->chip->model_id);
Louis Yung-Chieh Loc8ec7152012-09-17 17:38:35 +08001133 return -1;
1134 }
1135 break;
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001136 case ATMEL_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01001137 switch(flash->chip->model_id) {
Edward O'Callaghan1fa87e02019-05-03 02:27:24 -04001138 case ATMEL_AT25SF128A:
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001139 case ATMEL_AT25SL128A:
1140 if (w25q_read_status_register_2(flash) & (1 << 6)) {
1141 /* CMP == 1 */
1142 *w25q_ranges = w25rq128_cmp1_ranges;
1143 *num_entries = ARRAY_SIZE(w25rq128_cmp1_ranges);
1144 } else {
1145 /* CMP == 0 */
1146 *w25q_ranges = w25rq128_cmp0_ranges;
1147 *num_entries = ARRAY_SIZE(w25rq128_cmp0_ranges);
1148 }
1149 break;
1150 default:
1151 msg_cerr("%s() %d: Atmel flash chip mismatch"
1152 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01001153 flash->chip->model_id);
Furquan Shaikhb4df8ef2017-01-05 15:05:35 -08001154 return -1;
1155 }
1156 break;
David Hendricksf7924d12010-06-10 21:26:44 -07001157 default:
David Hendricksd494b0a2010-08-16 16:28:50 -07001158 msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
Patrick Georgif3fa2992017-02-02 16:24:44 +01001159 __func__, flash->chip->manufacture_id);
David Hendricksf7924d12010-06-10 21:26:44 -07001160 return -1;
1161 }
1162
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001163 return 0;
1164}
1165
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001166int w25_range_to_status(const struct flashctx *flash,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001167 unsigned int start, unsigned int len,
1168 struct w25q_status *status)
1169{
1170 struct w25q_range *w25q_ranges;
1171 int i, range_found = 0;
1172 int num_entries;
1173
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001174 if (w25_range_table(flash, &w25q_ranges, &num_entries))
1175 return -1;
1176
David Hendricksf7924d12010-06-10 21:26:44 -07001177 for (i = 0; i < num_entries; i++) {
1178 struct wp_range *r = &w25q_ranges[i].range;
1179
1180 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
1181 start, len, r->start, r->len);
1182 if ((start == r->start) && (len == r->len)) {
David Hendricksd494b0a2010-08-16 16:28:50 -07001183 status->bp0 = w25q_ranges[i].bp & 1;
1184 status->bp1 = w25q_ranges[i].bp >> 1;
1185 status->bp2 = w25q_ranges[i].bp >> 2;
1186 status->tb = w25q_ranges[i].tb;
1187 status->sec = w25q_ranges[i].sec;
David Hendricksf7924d12010-06-10 21:26:44 -07001188
1189 range_found = 1;
1190 break;
1191 }
1192 }
1193
1194 if (!range_found) {
1195 msg_cerr("matching range not found\n");
1196 return -1;
1197 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001198
David Hendricksd494b0a2010-08-16 16:28:50 -07001199 return 0;
1200}
1201
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001202int w25_status_to_range(const struct flashctx *flash,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001203 const struct w25q_status *status,
1204 unsigned int *start, unsigned int *len)
1205{
1206 struct w25q_range *w25q_ranges;
1207 int i, status_found = 0;
1208 int num_entries;
1209
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001210 if (w25_range_table(flash, &w25q_ranges, &num_entries))
1211 return -1;
1212
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001213 for (i = 0; i < num_entries; i++) {
1214 int bp;
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +08001215 int table_bp, table_tb, table_sec;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001216
1217 bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2);
1218 msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x / 0x%x 0x%x\n",
1219 bp, w25q_ranges[i].bp,
1220 status->tb, w25q_ranges[i].tb,
1221 status->sec, w25q_ranges[i].sec);
Louis Yung-Chieh Loedd39302011-11-10 15:43:06 +08001222 table_bp = w25q_ranges[i].bp;
1223 table_tb = w25q_ranges[i].tb;
1224 table_sec = w25q_ranges[i].sec;
1225 if ((bp == table_bp || table_bp == X) &&
1226 (status->tb == table_tb || table_tb == X) &&
1227 (status->sec == table_sec || table_sec == X)) {
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001228 *start = w25q_ranges[i].range.start;
1229 *len = w25q_ranges[i].range.len;
1230
1231 status_found = 1;
1232 break;
1233 }
1234 }
1235
1236 if (!status_found) {
1237 msg_cerr("matching status not found\n");
1238 return -1;
1239 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001240
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001241 return 0;
1242}
1243
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001244/* Given a [start, len], this function calls w25_range_to_status() to convert
1245 * it to flash-chip-specific range bits, then sets into status register.
1246 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001247static int w25_set_range(const struct flashctx *flash,
David Hendricksd494b0a2010-08-16 16:28:50 -07001248 unsigned int start, unsigned int len)
1249{
1250 struct w25q_status status;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001251 int tmp = 0;
1252 int expected = 0;
David Hendricksd494b0a2010-08-16 16:28:50 -07001253
1254 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301255 tmp = do_read_status(flash);
David Hendricksd494b0a2010-08-16 16:28:50 -07001256 memcpy(&status, &tmp, 1);
1257 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1258
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001259 if (w25_range_to_status(flash, start, len, &status))
1260 return -1;
David Hendricksf7924d12010-06-10 21:26:44 -07001261
1262 msg_cdbg("status.busy: %x\n", status.busy);
1263 msg_cdbg("status.wel: %x\n", status.wel);
1264 msg_cdbg("status.bp0: %x\n", status.bp0);
1265 msg_cdbg("status.bp1: %x\n", status.bp1);
1266 msg_cdbg("status.bp2: %x\n", status.bp2);
1267 msg_cdbg("status.tb: %x\n", status.tb);
1268 msg_cdbg("status.sec: %x\n", status.sec);
1269 msg_cdbg("status.srp0: %x\n", status.srp0);
1270
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001271 memcpy(&expected, &status, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301272 do_write_status(flash, expected);
David Hendricksf7924d12010-06-10 21:26:44 -07001273
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301274 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001275 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
1276 if ((tmp & MASK_WP_AREA) == (expected & MASK_WP_AREA)) {
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001277 return 0;
1278 } else {
David Hendricksc801adb2010-12-09 16:58:56 -08001279 msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001280 expected, tmp);
1281 return 1;
1282 }
David Hendricksf7924d12010-06-10 21:26:44 -07001283}
1284
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001285/* Print out the current status register value with human-readable text. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001286static int w25_wp_status(const struct flashctx *flash)
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001287{
1288 struct w25q_status status;
1289 int tmp;
David Hendricksce8ded32010-10-08 11:23:38 -07001290 unsigned int start, len;
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001291 int ret = 0;
1292
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001293 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301294 tmp = do_read_status(flash);
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001295 memcpy(&status, &tmp, 1);
1296 msg_cinfo("WP: status: 0x%02x\n", tmp);
1297 msg_cinfo("WP: status.srp0: %x\n", status.srp0);
1298 msg_cinfo("WP: write protect is %s.\n",
1299 status.srp0 ? "enabled" : "disabled");
1300
1301 msg_cinfo("WP: write protect range: ");
1302 if (w25_status_to_range(flash, &status, &start, &len)) {
1303 msg_cinfo("(cannot resolve the range)\n");
1304 ret = -1;
1305 } else {
1306 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1307 }
1308
1309 return ret;
1310}
1311
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001312static int w25q_large_range_to_status(const struct flashctx *flash,
1313 unsigned int start, unsigned int len,
1314 struct w25q_status_large *status)
1315{
1316 struct w25q_range *w25q_ranges;
1317 int i, range_found = 0;
1318 int num_entries;
1319
1320 if (w25_range_table(flash, &w25q_ranges, &num_entries))
1321 return -1;
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001322
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001323 for (i = 0; i < num_entries; i++) {
1324 struct wp_range *r = &w25q_ranges[i].range;
1325
1326 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
1327 start, len, r->start, r->len);
1328 if ((start == r->start) && (len == r->len)) {
1329 status->bp0 = w25q_ranges[i].bp & 1;
1330 status->bp1 = w25q_ranges[i].bp >> 1;
1331 status->bp2 = w25q_ranges[i].bp >> 2;
1332 status->bp3 = w25q_ranges[i].bp >> 3;
Karthikeyan Ramasubramanianfb166b72019-06-24 12:38:55 -06001333 /*
1334 * For MX25U12835E chip, Top/Bottom (T/B) bit is not
1335 * part of status register and in that bit position is
1336 * Quad Enable (QE)
1337 */
1338 if (flash->chip->manufacture_id != MACRONIX_ID ||
1339 flash->chip->model_id != MACRONIX_MX25U12835E)
1340 status->tb = w25q_ranges[i].tb;
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001341
1342 range_found = 1;
1343 break;
1344 }
1345 }
1346
1347 if (!range_found) {
1348 msg_cerr("matching range not found\n");
1349 return -1;
1350 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001351
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001352 return 0;
1353}
1354
1355static int w25_large_status_to_range(const struct flashctx *flash,
1356 const struct w25q_status_large *status,
1357 unsigned int *start, unsigned int *len)
1358{
1359 struct w25q_range *w25q_ranges;
1360 int i, status_found = 0;
1361 int num_entries;
1362
1363 if (w25_range_table(flash, &w25q_ranges, &num_entries))
1364 return -1;
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001365
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001366 for (i = 0; i < num_entries; i++) {
1367 int bp;
1368 int table_bp, table_tb;
1369
1370 bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2) |
1371 (status->bp3 << 3);
1372 msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x\n",
1373 bp, w25q_ranges[i].bp,
1374 status->tb, w25q_ranges[i].tb);
1375 table_bp = w25q_ranges[i].bp;
1376 table_tb = w25q_ranges[i].tb;
1377 if ((bp == table_bp || table_bp == X) &&
1378 (status->tb == table_tb || table_tb == X)) {
1379 *start = w25q_ranges[i].range.start;
1380 *len = w25q_ranges[i].range.len;
1381
1382 status_found = 1;
1383 break;
1384 }
1385 }
1386
1387 if (!status_found) {
1388 msg_cerr("matching status not found\n");
1389 return -1;
1390 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001391
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001392 return 0;
1393}
1394
1395/* Given a [start, len], this function calls w25_range_to_status() to convert
1396 * it to flash-chip-specific range bits, then sets into status register.
1397 * Returns 0 if successful, -1 on error, and 1 if reading back was different.
1398 */
1399static int w25q_large_set_range(const struct flashctx *flash,
1400 unsigned int start, unsigned int len)
1401{
1402 struct w25q_status_large status;
1403 int tmp;
1404 int expected = 0;
1405
1406 memset(&status, 0, sizeof(status));
1407 tmp = do_read_status(flash);
1408 memcpy(&status, &tmp, 1);
1409 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1410
1411 if (w25q_large_range_to_status(flash, start, len, &status))
1412 return -1;
1413
1414 msg_cdbg("status.busy: %x\n", status.busy);
1415 msg_cdbg("status.wel: %x\n", status.wel);
1416 msg_cdbg("status.bp0: %x\n", status.bp0);
1417 msg_cdbg("status.bp1: %x\n", status.bp1);
1418 msg_cdbg("status.bp2: %x\n", status.bp2);
1419 msg_cdbg("status.bp3: %x\n", status.bp3);
1420 msg_cdbg("status.tb: %x\n", status.tb);
1421 msg_cdbg("status.srp0: %x\n", status.srp0);
1422
1423 memcpy(&expected, &status, sizeof(status));
1424 do_write_status(flash, expected);
1425
1426 tmp = do_read_status(flash);
1427 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
1428 if ((tmp & MASK_WP_AREA_LARGE) == (expected & MASK_WP_AREA_LARGE)) {
1429 return 0;
1430 } else {
1431 msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
1432 expected, tmp);
1433 return 1;
1434 }
1435}
1436
1437static int w25q_large_wp_status(const struct flashctx *flash)
1438{
1439 struct w25q_status_large sr1;
1440 struct w25q_status_2 sr2;
1441 uint8_t tmp[2];
1442 unsigned int start, len;
1443 int ret = 0;
1444
1445 memset(&sr1, 0, sizeof(sr1));
1446 tmp[0] = do_read_status(flash);
1447 memcpy(&sr1, &tmp[0], 1);
1448
1449 memset(&sr2, 0, sizeof(sr2));
1450 tmp[1] = w25q_read_status_register_2(flash);
1451 memcpy(&sr2, &tmp[1], 1);
1452
1453 msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
1454 msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
1455 msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
1456 msg_cinfo("WP: write protect is %s.\n",
1457 (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
1458
1459 msg_cinfo("WP: write protect range: ");
1460 if (w25_large_status_to_range(flash, &sr1, &start, &len)) {
1461 msg_cinfo("(cannot resolve the range)\n");
1462 ret = -1;
1463 } else {
1464 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1465 }
1466
1467 return ret;
1468}
1469
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001470/* Set/clear the SRP0 bit in the status register. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001471static int w25_set_srp0(const struct flashctx *flash, int enable)
David Hendricksf7924d12010-06-10 21:26:44 -07001472{
1473 struct w25q_status status;
1474 int tmp = 0;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001475 int expected = 0;
David Hendricksf7924d12010-06-10 21:26:44 -07001476
1477 memset(&status, 0, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301478 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001479 /* FIXME: this is NOT endian-free copy. */
David Hendricksf7924d12010-06-10 21:26:44 -07001480 memcpy(&status, &tmp, 1);
1481 msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp);
1482
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001483 status.srp0 = enable ? 1 : 0;
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001484 memcpy(&expected, &status, sizeof(status));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301485 do_write_status(flash, expected);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001486
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301487 tmp = do_read_status(flash);
Louis Yung-Chieh Lo165b4642010-11-26 16:35:26 +08001488 msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp);
1489 if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA))
1490 return 1;
David Hendricksf7924d12010-06-10 21:26:44 -07001491
1492 return 0;
1493}
1494
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001495static int w25_enable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001496 enum wp_mode wp_mode)
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001497{
1498 int ret;
1499
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11001500 if (wp_mode != WP_MODE_HARDWARE) {
David Hendricks1c09f802012-10-03 11:03:48 -07001501 msg_cerr("%s(): unsupported write-protect mode\n", __func__);
1502 return 1;
1503 }
1504
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11001505 ret = w25_set_srp0(flash, 1);
David Hendricksc801adb2010-12-09 16:58:56 -08001506 if (ret)
1507 msg_cerr("%s(): error=%d.\n", __func__, ret);
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001508 return ret;
1509}
1510
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001511static int w25_disable_writeprotect(const struct flashctx *flash)
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001512{
1513 int ret;
1514
1515 ret = w25_set_srp0(flash, 0);
David Hendricksc801adb2010-12-09 16:58:56 -08001516 if (ret)
1517 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001518
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001519 return ret;
1520}
1521
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001522static int w25_list_ranges(const struct flashctx *flash)
David Hendricks0f7f5382011-02-11 18:12:31 -08001523{
1524 struct w25q_range *w25q_ranges;
1525 int i, num_entries;
1526
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001527 if (w25_range_table(flash, &w25q_ranges, &num_entries))
1528 return -1;
1529
David Hendricks0f7f5382011-02-11 18:12:31 -08001530 for (i = 0; i < num_entries; i++) {
1531 msg_cinfo("start: 0x%06x, length: 0x%06x\n",
1532 w25q_ranges[i].range.start,
1533 w25q_ranges[i].range.len);
1534 }
1535
1536 return 0;
1537}
1538
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001539static int w25q_wp_status(const struct flashctx *flash)
David Hendricks1c09f802012-10-03 11:03:48 -07001540{
1541 struct w25q_status sr1;
1542 struct w25q_status_2 sr2;
David Hendricksf1bd8802012-10-30 11:37:57 -07001543 uint8_t tmp[2];
David Hendricks1c09f802012-10-03 11:03:48 -07001544 unsigned int start, len;
1545 int ret = 0;
1546
1547 memset(&sr1, 0, sizeof(sr1));
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301548 tmp[0] = do_read_status(flash);
David Hendricksf1bd8802012-10-30 11:37:57 -07001549 memcpy(&sr1, &tmp[0], 1);
David Hendricks1c09f802012-10-03 11:03:48 -07001550
David Hendricksf1bd8802012-10-30 11:37:57 -07001551 memset(&sr2, 0, sizeof(sr2));
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001552 tmp[1] = w25q_read_status_register_2(flash);
David Hendricksf1bd8802012-10-30 11:37:57 -07001553 memcpy(&sr2, &tmp[1], 1);
1554
1555 msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]);
David Hendricks1c09f802012-10-03 11:03:48 -07001556 msg_cinfo("WP: status.srp0: %x\n", sr1.srp0);
1557 msg_cinfo("WP: status.srp1: %x\n", sr2.srp1);
1558 msg_cinfo("WP: write protect is %s.\n",
1559 (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled");
1560
1561 msg_cinfo("WP: write protect range: ");
1562 if (w25_status_to_range(flash, &sr1, &start, &len)) {
1563 msg_cinfo("(cannot resolve the range)\n");
1564 ret = -1;
1565 } else {
1566 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
1567 }
1568
1569 return ret;
1570}
1571
1572/*
1573 * W25Q adds an optional byte to the standard WRSR opcode. If /CS is
1574 * de-asserted after the first byte, then it acts like a JEDEC-standard
1575 * WRSR command. if /CS is asserted, then the next data byte is written
1576 * into status register 2.
1577 */
1578#define W25Q_WRSR_OUTSIZE 0x03
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001579static int w25q_write_status_register_WREN(const struct flashctx *flash, uint8_t s1, uint8_t s2)
David Hendricks1c09f802012-10-03 11:03:48 -07001580{
1581 int result;
1582 struct spi_command cmds[] = {
1583 {
1584 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
1585 .writecnt = JEDEC_WREN_OUTSIZE,
1586 .writearr = (const unsigned char[]){ JEDEC_WREN },
1587 .readcnt = 0,
1588 .readarr = NULL,
1589 }, {
1590 .writecnt = W25Q_WRSR_OUTSIZE,
1591 .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 },
1592 .readcnt = 0,
1593 .readarr = NULL,
1594 }, {
1595 .writecnt = 0,
1596 .writearr = NULL,
1597 .readcnt = 0,
1598 .readarr = NULL,
1599 }};
1600
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001601 result = spi_send_multicommand(flash, cmds);
David Hendricks1c09f802012-10-03 11:03:48 -07001602 if (result) {
1603 msg_cerr("%s failed during command execution\n",
1604 __func__);
1605 }
1606
1607 /* WRSR performs a self-timed erase before the changes take effect. */
David Hendricks60824042014-12-11 17:22:06 -08001608 programmer_delay(100 * 1000);
David Hendricks1c09f802012-10-03 11:03:48 -07001609
1610 return result;
1611}
1612
1613/*
1614 * Set/clear the SRP1 bit in status register 2.
1615 * FIXME: make this more generic if other chips use the same SR2 layout
1616 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001617static int w25q_set_srp1(const struct flashctx *flash, int enable)
David Hendricks1c09f802012-10-03 11:03:48 -07001618{
1619 struct w25q_status sr1;
1620 struct w25q_status_2 sr2;
1621 uint8_t tmp, expected;
1622
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301623 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001624 memcpy(&sr1, &tmp, 1);
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001625 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001626 memcpy(&sr2, &tmp, 1);
1627
1628 msg_cdbg("%s: old status 2: 0x%02x\n", __func__, tmp);
1629
1630 sr2.srp1 = enable ? 1 : 0;
1631
1632 memcpy(&expected, &sr2, 1);
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001633 w25q_write_status_register_WREN(flash, *((uint8_t *)&sr1), *((uint8_t *)&sr2));
David Hendricks1c09f802012-10-03 11:03:48 -07001634
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001635 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001636 msg_cdbg("%s: new status 2: 0x%02x\n", __func__, tmp);
1637 if ((tmp & MASK_WP2_AREA) != (expected & MASK_WP2_AREA))
1638 return 1;
1639
1640 return 0;
1641}
1642
1643enum wp_mode get_wp_mode(const char *mode_str)
1644{
1645 enum wp_mode wp_mode = WP_MODE_UNKNOWN;
1646
1647 if (!strcasecmp(mode_str, "hardware"))
1648 wp_mode = WP_MODE_HARDWARE;
1649 else if (!strcasecmp(mode_str, "power_cycle"))
1650 wp_mode = WP_MODE_POWER_CYCLE;
1651 else if (!strcasecmp(mode_str, "permanent"))
1652 wp_mode = WP_MODE_PERMANENT;
1653
1654 return wp_mode;
1655}
1656
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001657static int w25q_disable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001658 enum wp_mode wp_mode)
1659{
1660 int ret = 1;
David Hendricks1c09f802012-10-03 11:03:48 -07001661 struct w25q_status_2 sr2;
1662 uint8_t tmp;
1663
1664 switch (wp_mode) {
1665 case WP_MODE_HARDWARE:
1666 ret = w25_set_srp0(flash, 0);
1667 break;
1668 case WP_MODE_POWER_CYCLE:
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001669 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001670 memcpy(&sr2, &tmp, 1);
1671 if (sr2.srp1) {
1672 msg_cerr("%s(): must disconnect power to disable "
1673 "write-protection\n", __func__);
1674 } else {
1675 ret = 0;
1676 }
1677 break;
1678 case WP_MODE_PERMANENT:
1679 msg_cerr("%s(): cannot disable permanent write-protection\n",
1680 __func__);
1681 break;
1682 default:
1683 msg_cerr("%s(): invalid mode specified\n", __func__);
1684 break;
1685 }
1686
1687 if (ret)
1688 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11001689
David Hendricks1c09f802012-10-03 11:03:48 -07001690 return ret;
1691}
1692
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001693static int w25q_disable_writeprotect_default(const struct flashctx *flash)
David Hendricks1c09f802012-10-03 11:03:48 -07001694{
1695 return w25q_disable_writeprotect(flash, WP_MODE_HARDWARE);
1696}
1697
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001698static int w25q_enable_writeprotect(const struct flashctx *flash,
David Hendricks1c09f802012-10-03 11:03:48 -07001699 enum wp_mode wp_mode)
1700{
1701 int ret = 1;
1702 struct w25q_status sr1;
1703 struct w25q_status_2 sr2;
1704 uint8_t tmp;
1705
1706 switch (wp_mode) {
1707 case WP_MODE_HARDWARE:
1708 if (w25q_disable_writeprotect(flash, WP_MODE_POWER_CYCLE)) {
1709 msg_cerr("%s(): cannot disable power cycle WP mode\n",
1710 __func__);
1711 break;
1712 }
1713
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301714 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001715 memcpy(&sr1, &tmp, 1);
1716 if (sr1.srp0)
1717 ret = 0;
1718 else
1719 ret = w25_set_srp0(flash, 1);
1720
1721 break;
1722 case WP_MODE_POWER_CYCLE:
1723 if (w25q_disable_writeprotect(flash, WP_MODE_HARDWARE)) {
1724 msg_cerr("%s(): cannot disable hardware WP mode\n",
1725 __func__);
1726 break;
1727 }
1728
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001729 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001730 memcpy(&sr2, &tmp, 1);
1731 if (sr2.srp1)
1732 ret = 0;
1733 else
1734 ret = w25q_set_srp1(flash, 1);
1735
1736 break;
1737 case WP_MODE_PERMANENT:
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05301738 tmp = do_read_status(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001739 memcpy(&sr1, &tmp, 1);
1740 if (sr1.srp0 == 0) {
1741 ret = w25_set_srp0(flash, 1);
1742 if (ret) {
David Hendricksf1bd8802012-10-30 11:37:57 -07001743 msg_perr("%s(): cannot enable SRP0 for "
David Hendricks1c09f802012-10-03 11:03:48 -07001744 "permanent WP\n", __func__);
1745 break;
1746 }
1747 }
1748
Souvik Ghoshd75cd672016-06-17 14:21:39 -07001749 tmp = w25q_read_status_register_2(flash);
David Hendricks1c09f802012-10-03 11:03:48 -07001750 memcpy(&sr2, &tmp, 1);
1751 if (sr2.srp1 == 0) {
1752 ret = w25q_set_srp1(flash, 1);
1753 if (ret) {
David Hendricksf1bd8802012-10-30 11:37:57 -07001754 msg_perr("%s(): cannot enable SRP1 for "
David Hendricks1c09f802012-10-03 11:03:48 -07001755 "permanent WP\n", __func__);
1756 break;
1757 }
1758 }
1759
1760 break;
David Hendricksf1bd8802012-10-30 11:37:57 -07001761 default:
1762 msg_perr("%s(): invalid mode %d\n", __func__, wp_mode);
1763 break;
David Hendricks1c09f802012-10-03 11:03:48 -07001764 }
1765
1766 if (ret)
1767 msg_cerr("%s(): error=%d.\n", __func__, ret);
1768 return ret;
1769}
1770
1771/* W25P, W25X, and many flash chips from various vendors */
David Hendricksf7924d12010-06-10 21:26:44 -07001772struct wp wp_w25 = {
David Hendricks0f7f5382011-02-11 18:12:31 -08001773 .list_ranges = w25_list_ranges,
David Hendricksf7924d12010-06-10 21:26:44 -07001774 .set_range = w25_set_range,
1775 .enable = w25_enable_writeprotect,
Louis Yung-Chieh Loc19d3c52010-10-08 11:59:16 +08001776 .disable = w25_disable_writeprotect,
Louis Yung-Chieh Loa92e8b22010-10-08 13:31:27 +08001777 .wp_status = w25_wp_status,
David Hendricks1c09f802012-10-03 11:03:48 -07001778
1779};
1780
1781/* W25Q series has features such as a second status register and SFDP */
1782struct wp wp_w25q = {
1783 .list_ranges = w25_list_ranges,
1784 .set_range = w25_set_range,
1785 .enable = w25q_enable_writeprotect,
1786 /*
1787 * By default, disable hardware write-protection. We may change
1788 * this later if we want to add fine-grained write-protect disable
1789 * as a command-line option.
1790 */
1791 .disable = w25q_disable_writeprotect_default,
1792 .wp_status = w25q_wp_status,
David Hendricksf7924d12010-06-10 21:26:44 -07001793};
David Hendrickse0512a72014-07-15 20:30:47 -07001794
Duncan Laurie1801f7c2019-01-09 18:02:51 -08001795/* W25Q large series has 4 block-protect bits */
1796struct wp wp_w25q_large = {
1797 .list_ranges = w25_list_ranges,
1798 .set_range = w25q_large_set_range,
1799 .enable = w25q_enable_writeprotect,
1800 /*
1801 * By default, disable hardware write-protection. We may change
1802 * this later if we want to add fine-grained write-protect disable
1803 * as a command-line option.
1804 */
1805 .disable = w25q_disable_writeprotect_default,
1806 .wp_status = w25q_large_wp_status,
1807};
1808
David Hendricksaf3944a2014-07-28 18:37:40 -07001809struct generic_range gd25q32_cmp0_ranges[] = {
1810 /* none, bp4 and bp3 => don't care */
David Hendricks148a4bf2015-03-13 21:02:42 -07001811 { { }, 0x00, {0, 0} },
1812 { { }, 0x08, {0, 0} },
1813 { { }, 0x10, {0, 0} },
1814 { { }, 0x18, {0, 0} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001815
David Hendricks148a4bf2015-03-13 21:02:42 -07001816 { { }, 0x01, {0x3f0000, 64 * 1024} },
1817 { { }, 0x02, {0x3e0000, 128 * 1024} },
1818 { { }, 0x03, {0x3c0000, 256 * 1024} },
1819 { { }, 0x04, {0x380000, 512 * 1024} },
1820 { { }, 0x05, {0x300000, 1024 * 1024} },
1821 { { }, 0x06, {0x200000, 2048 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001822
David Hendricks148a4bf2015-03-13 21:02:42 -07001823 { { }, 0x09, {0x000000, 64 * 1024} },
1824 { { }, 0x0a, {0x000000, 128 * 1024} },
1825 { { }, 0x0b, {0x000000, 256 * 1024} },
1826 { { }, 0x0c, {0x000000, 512 * 1024} },
1827 { { }, 0x0d, {0x000000, 1024 * 1024} },
1828 { { }, 0x0e, {0x000000, 2048 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001829
1830 /* all, bp4 and bp3 => don't care */
David Hendricks148a4bf2015-03-13 21:02:42 -07001831 { { }, 0x07, {0x000000, 4096 * 1024} },
1832 { { }, 0x0f, {0x000000, 4096 * 1024} },
1833 { { }, 0x17, {0x000000, 4096 * 1024} },
1834 { { }, 0x1f, {0x000000, 4096 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001835
David Hendricks148a4bf2015-03-13 21:02:42 -07001836 { { }, 0x11, {0x3ff000, 4 * 1024} },
1837 { { }, 0x12, {0x3fe000, 8 * 1024} },
1838 { { }, 0x13, {0x3fc000, 16 * 1024} },
1839 { { }, 0x14, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
1840 { { }, 0x15, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */
1841 { { }, 0x16, {0x3f8000, 32 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001842
David Hendricks148a4bf2015-03-13 21:02:42 -07001843 { { }, 0x19, {0x000000, 4 * 1024} },
1844 { { }, 0x1a, {0x000000, 8 * 1024} },
1845 { { }, 0x1b, {0x000000, 16 * 1024} },
1846 { { }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1847 { { }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1848 { { }, 0x1e, {0x000000, 32 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001849};
1850
1851struct generic_range gd25q32_cmp1_ranges[] = {
Martin Roth563a1fe2017-04-18 14:26:27 -06001852 /* All, bp4 and bp3 => don't care */
1853 { { }, 0x00, {0x000000, 4096 * 1024} }, /* All */
1854 { { }, 0x08, {0x000000, 4096 * 1024} },
1855 { { }, 0x10, {0x000000, 4096 * 1024} },
1856 { { }, 0x18, {0x000000, 4096 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001857
David Hendricks148a4bf2015-03-13 21:02:42 -07001858 { { }, 0x01, {0x000000, 4032 * 1024} },
1859 { { }, 0x02, {0x000000, 3968 * 1024} },
1860 { { }, 0x03, {0x000000, 3840 * 1024} },
1861 { { }, 0x04, {0x000000, 3584 * 1024} },
1862 { { }, 0x05, {0x000000, 3 * 1024 * 1024} },
1863 { { }, 0x06, {0x000000, 2 * 1024 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001864
David Hendricks148a4bf2015-03-13 21:02:42 -07001865 { { }, 0x09, {0x010000, 4032 * 1024} },
1866 { { }, 0x0a, {0x020000, 3968 * 1024} },
1867 { { }, 0x0b, {0x040000, 3840 * 1024} },
1868 { { }, 0x0c, {0x080000, 3584 * 1024} },
1869 { { }, 0x0d, {0x100000, 3 * 1024 * 1024} },
1870 { { }, 0x0e, {0x200000, 2 * 1024 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001871
Martin Roth563a1fe2017-04-18 14:26:27 -06001872 /* None, bp4 and bp3 => don't care */
1873 { { }, 0x07, {0, 0} }, /* None */
1874 { { }, 0x0f, {0, 0} },
1875 { { }, 0x17, {0, 0} },
1876 { { }, 0x1f, {0, 0} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001877
David Hendricks148a4bf2015-03-13 21:02:42 -07001878 { { }, 0x11, {0x000000, 4092 * 1024} },
1879 { { }, 0x12, {0x000000, 4088 * 1024} },
1880 { { }, 0x13, {0x000000, 4080 * 1024} },
1881 { { }, 0x14, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
1882 { { }, 0x15, {0x000000, 4064 * 1024} }, /* bp0 => don't care */
1883 { { }, 0x16, {0x000000, 4064 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001884
David Hendricks148a4bf2015-03-13 21:02:42 -07001885 { { }, 0x19, {0x001000, 4092 * 1024} },
1886 { { }, 0x1a, {0x002000, 4088 * 1024} },
1887 { { }, 0x1b, {0x040000, 4080 * 1024} },
1888 { { }, 0x1c, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
1889 { { }, 0x1d, {0x080000, 4064 * 1024} }, /* bp0 => don't care */
1890 { { }, 0x1e, {0x080000, 4064 * 1024} },
David Hendricksaf3944a2014-07-28 18:37:40 -07001891};
1892
1893static struct generic_wp gd25q32_wp = {
1894 /* TODO: map second status register */
1895 .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
1896};
1897
David Hendricks1e9d7ca2016-03-14 15:50:34 -07001898struct generic_range gd25q128_cmp0_ranges[] = {
1899 /* none, bp4 and bp3 => don't care, others = 0 */
1900 { { .tb = 0 }, 0x00, {0, 0} },
1901 { { .tb = 0 }, 0x08, {0, 0} },
1902 { { .tb = 0 }, 0x10, {0, 0} },
1903 { { .tb = 0 }, 0x18, {0, 0} },
1904
1905 { { .tb = 0 }, 0x01, {0xfc0000, 256 * 1024} },
1906 { { .tb = 0 }, 0x02, {0xf80000, 512 * 1024} },
1907 { { .tb = 0 }, 0x03, {0xf00000, 1024 * 1024} },
1908 { { .tb = 0 }, 0x04, {0xe00000, 2048 * 1024} },
1909 { { .tb = 0 }, 0x05, {0xc00000, 4096 * 1024} },
1910 { { .tb = 0 }, 0x06, {0x800000, 8192 * 1024} },
1911
1912 { { .tb = 0 }, 0x09, {0x000000, 256 * 1024} },
1913 { { .tb = 0 }, 0x0a, {0x000000, 512 * 1024} },
1914 { { .tb = 0 }, 0x0b, {0x000000, 1024 * 1024} },
1915 { { .tb = 0 }, 0x0c, {0x000000, 2048 * 1024} },
1916 { { .tb = 0 }, 0x0d, {0x000000, 4096 * 1024} },
1917 { { .tb = 0 }, 0x0e, {0x000000, 8192 * 1024} },
1918
1919 /* all, bp4 and bp3 => don't care, others = 1 */
1920 { { .tb = 0 }, 0x07, {0x000000, 16384 * 1024} },
1921 { { .tb = 0 }, 0x0f, {0x000000, 16384 * 1024} },
1922 { { .tb = 0 }, 0x17, {0x000000, 16384 * 1024} },
1923 { { .tb = 0 }, 0x1f, {0x000000, 16384 * 1024} },
1924
1925 { { .tb = 0 }, 0x11, {0xfff000, 4 * 1024} },
1926 { { .tb = 0 }, 0x12, {0xffe000, 8 * 1024} },
1927 { { .tb = 0 }, 0x13, {0xffc000, 16 * 1024} },
1928 { { .tb = 0 }, 0x14, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
1929 { { .tb = 0 }, 0x15, {0xff8000, 32 * 1024} }, /* bp0 => don't care */
1930
1931 { { .tb = 0 }, 0x19, {0x000000, 4 * 1024} },
1932 { { .tb = 0 }, 0x1a, {0x000000, 8 * 1024} },
1933 { { .tb = 0 }, 0x1b, {0x000000, 16 * 1024} },
1934 { { .tb = 0 }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1935 { { .tb = 0 }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */
1936 { { .tb = 0 }, 0x1e, {0x000000, 32 * 1024} },
1937};
1938
1939struct generic_range gd25q128_cmp1_ranges[] = {
1940 /* none, bp4 and bp3 => don't care, others = 0 */
1941 { { .tb = 1 }, 0x00, {0x000000, 16384 * 1024} },
1942 { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
1943 { { .tb = 1 }, 0x10, {0x000000, 16384 * 1024} },
1944 { { .tb = 1 }, 0x18, {0x000000, 16384 * 1024} },
1945
1946 { { .tb = 1 }, 0x01, {0x000000, 16128 * 1024} },
1947 { { .tb = 1 }, 0x02, {0x000000, 15872 * 1024} },
1948 { { .tb = 1 }, 0x03, {0x000000, 15360 * 1024} },
1949 { { .tb = 1 }, 0x04, {0x000000, 14336 * 1024} },
1950 { { .tb = 1 }, 0x05, {0x000000, 12288 * 1024} },
1951 { { .tb = 1 }, 0x06, {0x000000, 8192 * 1024} },
1952
1953 { { .tb = 1 }, 0x09, {0x000000, 16128 * 1024} },
1954 { { .tb = 1 }, 0x0a, {0x000000, 15872 * 1024} },
1955 { { .tb = 1 }, 0x0b, {0x000000, 15360 * 1024} },
1956 { { .tb = 1 }, 0x0c, {0x000000, 14336 * 1024} },
1957 { { .tb = 1 }, 0x0d, {0x000000, 12288 * 1024} },
1958 { { .tb = 1 }, 0x0e, {0x000000, 8192 * 1024} },
1959
1960 /* none, bp4 and bp3 => don't care, others = 1 */
1961 { { .tb = 1 }, 0x07, {0x000000, 16384 * 1024} },
1962 { { .tb = 1 }, 0x08, {0x000000, 16384 * 1024} },
1963 { { .tb = 1 }, 0x0f, {0x000000, 16384 * 1024} },
1964 { { .tb = 1 }, 0x17, {0x000000, 16384 * 1024} },
1965 { { .tb = 1 }, 0x1f, {0x000000, 16384 * 1024} },
1966
1967 { { .tb = 1 }, 0x11, {0x000000, 16380 * 1024} },
1968 { { .tb = 1 }, 0x12, {0x000000, 16376 * 1024} },
1969 { { .tb = 1 }, 0x13, {0x000000, 16368 * 1024} },
1970 { { .tb = 1 }, 0x14, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
1971 { { .tb = 1 }, 0x15, {0x000000, 16352 * 1024} }, /* bp0 => don't care */
1972
1973 { { .tb = 1 }, 0x19, {0x001000, 16380 * 1024} },
1974 { { .tb = 1 }, 0x1a, {0x002000, 16376 * 1024} },
1975 { { .tb = 1 }, 0x1b, {0x004000, 16368 * 1024} },
1976 { { .tb = 1 }, 0x1c, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
1977 { { .tb = 1 }, 0x1d, {0x008000, 16352 * 1024} }, /* bp0 => don't care */
1978 { { .tb = 1 }, 0x1e, {0x008000, 16352 * 1024} },
1979};
1980
1981static struct generic_wp gd25q128_wp = {
1982 /* TODO: map second and third status registers */
1983 .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 },
1984};
1985
David Hendricks83541d32014-07-15 20:58:21 -07001986#if 0
1987/* FIXME: MX25L6405D has same ID as MX25L6406 */
1988static struct w25q_range mx25l6405d_ranges[] = {
1989 { X, 0, 0, {0, 0} }, /* none */
1990 { X, 0, 0x1, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */
1991 { X, 0, 0x2, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */
1992 { X, 0, 0x3, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */
1993 { X, 0, 0x4, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */
1994 { X, 0, 0x5, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */
1995 { X, 0, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
1996 { X, 0, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */
1997
1998 { X, 1, 0x0, {0x000000, 8192 * 1024} },
1999 { X, 1, 0x1, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2000 { X, 1, 0x2, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */
2001 { X, 1, 0x3, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */
2002 { X, 1, 0x4, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */
2003 { X, 1, 0x5, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */
2004 { X, 1, 0x6, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */
2005 { X, 1, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */
2006};
2007#endif
2008
2009/* FIXME: MX25L6406 has same ID as MX25L6405D */
2010struct generic_range mx25l6406e_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002011 { { }, 0, {0, 0} }, /* none */
2012 { { }, 0x1, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
2013 { { }, 0x2, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
2014 { { }, 0x3, {0x7a0000, 64 * 8 * 1024} }, /* blocks 120-127 */
2015 { { }, 0x4, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
2016 { { }, 0x5, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
2017 { { }, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
David Hendricks83541d32014-07-15 20:58:21 -07002018
David Hendricks148a4bf2015-03-13 21:02:42 -07002019 { { }, 0x7, {0x000000, 64 * 128 * 1024} }, /* all */
2020 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2021 { { }, 0x9, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2022 { { }, 0xa, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */
2023 { { }, 0xb, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */
2024 { { }, 0xc, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */
2025 { { }, 0xd, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */
2026 { { }, 0xe, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */
2027 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricks83541d32014-07-15 20:58:21 -07002028};
2029
2030static struct generic_wp mx25l6406e_wp = {
2031 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
2032 .ranges = &mx25l6406e_ranges[0],
2033};
David Hendrickse0512a72014-07-15 20:30:47 -07002034
David Hendricksc3496092014-11-13 17:20:55 -08002035struct generic_range mx25l6495f_tb0_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002036 { { }, 0, {0, 0} }, /* none */
2037 { { }, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */
2038 { { }, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */
2039 { { }, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */
David Hendricksc3496092014-11-13 17:20:55 -08002040
David Hendricks148a4bf2015-03-13 21:02:42 -07002041 { { }, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */
2042 { { }, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */
2043 { { }, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */
2044 { { }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */
2045 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2046 { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
2047 { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
2048 { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
2049 { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
2050 { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
2051 { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
2052 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricksc3496092014-11-13 17:20:55 -08002053};
2054
2055struct generic_range mx25l6495f_tb1_ranges[] = {
David Hendricks148a4bf2015-03-13 21:02:42 -07002056 { { }, 0, {0, 0} }, /* none */
2057 { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
2058 { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
2059 { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
2060 { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
2061 { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
2062 { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
2063 { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2064 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */
2065 { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */
2066 { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */
2067 { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */
2068 { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */
2069 { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */
2070 { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */
2071 { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */
David Hendricksc3496092014-11-13 17:20:55 -08002072};
2073
2074static struct generic_wp mx25l6495f_wp = {
2075 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
2076};
2077
Vic Yang848bfd12018-03-23 10:24:07 -07002078struct generic_range mx25l25635f_tb0_ranges[] = {
2079 { { }, 0, {0, 0} }, /* none */
2080 { { }, 0x1, {0x1ff0000, 64 * 1 * 1024} }, /* block 511 */
2081 { { }, 0x2, {0x1fe0000, 64 * 2 * 1024} }, /* blocks 510-511 */
2082 { { }, 0x3, {0x1fc0000, 64 * 4 * 1024} }, /* blocks 508-511 */
2083 { { }, 0x4, {0x1f80000, 64 * 8 * 1024} }, /* blocks 504-511 */
2084 { { }, 0x5, {0x1f00000, 64 * 16 * 1024} }, /* blocks 496-511 */
2085 { { }, 0x6, {0x1e00000, 64 * 32 * 1024} }, /* blocks 480-511 */
2086 { { }, 0x7, {0x1c00000, 64 * 64 * 1024} }, /* blocks 448-511 */
2087 { { }, 0x8, {0x1800000, 64 * 128 * 1024} }, /* blocks 384-511 */
2088 { { }, 0x9, {0x1000000, 64 * 256 * 1024} }, /* blocks 256-511 */
2089 { { }, 0xa, {0x0000000, 64 * 512 * 1024} }, /* all */
2090 { { }, 0xb, {0x0000000, 64 * 512 * 1024} }, /* all */
2091 { { }, 0xc, {0x0000000, 64 * 512 * 1024} }, /* all */
2092 { { }, 0xd, {0x0000000, 64 * 512 * 1024} }, /* all */
2093 { { }, 0xe, {0x0000000, 64 * 512 * 1024} }, /* all */
2094 { { }, 0xf, {0x0000000, 64 * 512 * 1024} }, /* all */
2095};
2096
2097struct generic_range mx25l25635f_tb1_ranges[] = {
2098 { { }, 0, {0, 0} }, /* none */
2099 { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */
2100 { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */
2101 { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */
2102 { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */
2103 { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */
2104 { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */
2105 { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */
2106 { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */
2107 { { }, 0x9, {0x000000, 64 * 256 * 1024} }, /* blocks 0-255 */
2108 { { }, 0xa, {0x000000, 64 * 512 * 1024} }, /* all */
2109 { { }, 0xb, {0x000000, 64 * 512 * 1024} }, /* all */
2110 { { }, 0xc, {0x000000, 64 * 512 * 1024} }, /* all */
2111 { { }, 0xd, {0x000000, 64 * 512 * 1024} }, /* all */
2112 { { }, 0xe, {0x000000, 64 * 512 * 1024} }, /* all */
2113 { { }, 0xf, {0x000000, 64 * 512 * 1024} }, /* all */
2114};
2115
2116static struct generic_wp mx25l25635f_wp = {
2117 .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 },
2118};
2119
David Hendricks148a4bf2015-03-13 21:02:42 -07002120struct generic_range s25fs128s_ranges[] = {
2121 { { .tb = 1 }, 0, {0, 0} }, /* none */
2122 { { .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* lower 64th */
2123 { { .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* lower 32nd */
2124 { { .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* lower 16th */
2125 { { .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* lower 8th */
2126 { { .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* lower 4th */
2127 { { .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* lower half */
2128 { { .tb = 1 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
David Hendricksa9884852014-12-11 15:31:12 -08002129
David Hendricks148a4bf2015-03-13 21:02:42 -07002130 { { .tb = 0 }, 0, {0, 0} }, /* none */
2131 { { .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* upper 64th */
2132 { { .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* upper 32nd */
2133 { { .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* upper 16th */
2134 { { .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* upper 8th */
2135 { { .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* upper 4th */
2136 { { .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* upper half */
2137 { { .tb = 0 }, 0x7, {0x000000, 16384 * 1024} }, /* all */
David Hendricksa9884852014-12-11 15:31:12 -08002138};
2139
2140static struct generic_wp s25fs128s_wp = {
2141 .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
David Hendricks148a4bf2015-03-13 21:02:42 -07002142 .get_modifier_bits = s25f_get_modifier_bits,
2143 .set_modifier_bits = s25f_set_modifier_bits,
David Hendricksa9884852014-12-11 15:31:12 -08002144};
2145
David Hendricksc694bb82015-02-25 14:52:17 -08002146
David Hendricks148a4bf2015-03-13 21:02:42 -07002147struct generic_range s25fl256s_ranges[] = {
2148 { { .tb = 1 }, 0, {0, 0} }, /* none */
2149 { { .tb = 1 }, 0x1, {0x000000, 512 * 1024} }, /* lower 64th */
2150 { { .tb = 1 }, 0x2, {0x000000, 1024 * 1024} }, /* lower 32nd */
2151 { { .tb = 1 }, 0x3, {0x000000, 2048 * 1024} }, /* lower 16th */
2152 { { .tb = 1 }, 0x4, {0x000000, 4096 * 1024} }, /* lower 8th */
2153 { { .tb = 1 }, 0x5, {0x000000, 8192 * 1024} }, /* lower 4th */
2154 { { .tb = 1 }, 0x6, {0x000000, 16384 * 1024} }, /* lower half */
2155 { { .tb = 1 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
2156
2157 { { .tb = 0 }, 0, {0, 0} }, /* none */
2158 { { .tb = 0 }, 0x1, {0x1f80000, 512 * 1024} }, /* upper 64th */
2159 { { .tb = 0 }, 0x2, {0x1f00000, 1024 * 1024} }, /* upper 32nd */
2160 { { .tb = 0 }, 0x3, {0x1e00000, 2048 * 1024} }, /* upper 16th */
2161 { { .tb = 0 }, 0x4, {0x1c00000, 4096 * 1024} }, /* upper 8th */
2162 { { .tb = 0 }, 0x5, {0x1800000, 8192 * 1024} }, /* upper 4th */
2163 { { .tb = 0 }, 0x6, {0x1000000, 16384 * 1024} }, /* upper half */
2164 { { .tb = 0 }, 0x7, {0x000000, 32768 * 1024} }, /* all */
David Hendricksc694bb82015-02-25 14:52:17 -08002165};
2166
2167static struct generic_wp s25fl256s_wp = {
2168 .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 },
David Hendricks148a4bf2015-03-13 21:02:42 -07002169 .get_modifier_bits = s25f_get_modifier_bits,
2170 .set_modifier_bits = s25f_set_modifier_bits,
David Hendricksc694bb82015-02-25 14:52:17 -08002171};
2172
David Hendrickse0512a72014-07-15 20:30:47 -07002173/* Given a flash chip, this function returns its writeprotect info. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002174static int generic_range_table(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002175 struct generic_wp **wp,
2176 int *num_entries)
2177{
2178 *wp = NULL;
2179 *num_entries = 0;
2180
Patrick Georgif3fa2992017-02-02 16:24:44 +01002181 switch (flash->chip->manufacture_id) {
David Hendricksaf3944a2014-07-28 18:37:40 -07002182 case GIGADEVICE_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002183 switch(flash->chip->model_id) {
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002184
Martin Roth563a1fe2017-04-18 14:26:27 -06002185 case GIGADEVICE_GD25LQ32:
David Hendricksaf3944a2014-07-28 18:37:40 -07002186 case GIGADEVICE_GD25Q32: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002187 uint8_t sr1 = w25q_read_status_register_2(flash);
David Hendricksaf3944a2014-07-28 18:37:40 -07002188 *wp = &gd25q32_wp;
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002189
David Hendricksaf3944a2014-07-28 18:37:40 -07002190 if (!(sr1 & (1 << 6))) { /* CMP == 0 */
2191 (*wp)->ranges = &gd25q32_cmp0_ranges[0];
2192 *num_entries = ARRAY_SIZE(gd25q32_cmp0_ranges);
2193 } else { /* CMP == 1 */
2194 (*wp)->ranges = &gd25q32_cmp1_ranges[0];
2195 *num_entries = ARRAY_SIZE(gd25q32_cmp1_ranges);
2196 }
2197
2198 break;
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002199 }
Furquan Shaikh62cd8102016-07-17 23:04:06 -07002200 case GIGADEVICE_GD25Q128:
Aaron Durbin6c957d72018-08-20 09:31:01 -06002201 case GIGADEVICE_GD25LQ128CD: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002202 uint8_t sr1 = w25q_read_status_register_2(flash);
David Hendricks1e9d7ca2016-03-14 15:50:34 -07002203 *wp = &gd25q128_wp;
2204
2205 if (!(sr1 & (1 << 6))) { /* CMP == 0 */
2206 (*wp)->ranges = &gd25q128_cmp0_ranges[0];
2207 *num_entries = ARRAY_SIZE(gd25q128_cmp0_ranges);
2208 } else { /* CMP == 1 */
2209 (*wp)->ranges = &gd25q128_cmp1_ranges[0];
2210 *num_entries = ARRAY_SIZE(gd25q128_cmp1_ranges);
2211 }
2212
2213 break;
David Hendricksaf3944a2014-07-28 18:37:40 -07002214 }
2215 default:
2216 msg_cerr("%s() %d: GigaDevice flash chip mismatch"
2217 " (0x%04x), aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01002218 flash->chip->model_id);
David Hendricksaf3944a2014-07-28 18:37:40 -07002219 return -1;
2220 }
2221 break;
David Hendricks83541d32014-07-15 20:58:21 -07002222 case MACRONIX_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002223 switch (flash->chip->model_id) {
David Hendricks83541d32014-07-15 20:58:21 -07002224 case MACRONIX_MX25L6405:
2225 /* FIXME: MX25L64* chips have mixed capabilities and
2226 share IDs */
2227 *wp = &mx25l6406e_wp;
2228 *num_entries = ARRAY_SIZE(mx25l6406e_ranges);
2229 break;
David Hendricksc3496092014-11-13 17:20:55 -08002230 case MACRONIX_MX25L6495F: {
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002231 uint8_t cr = mx25l_read_config_register(flash);
David Hendricksc3496092014-11-13 17:20:55 -08002232
2233 *wp = &mx25l6495f_wp;
2234 if (!(cr & (1 << 3))) { /* T/B == 0 */
2235 (*wp)->ranges = &mx25l6495f_tb0_ranges[0];
2236 *num_entries = ARRAY_SIZE(mx25l6495f_tb0_ranges);
2237 } else { /* T/B == 1 */
2238 (*wp)->ranges = &mx25l6495f_tb1_ranges[0];
2239 *num_entries = ARRAY_SIZE(mx25l6495f_tb1_ranges);
2240 }
2241 break;
2242 }
Vic Yang848bfd12018-03-23 10:24:07 -07002243 case MACRONIX_MX25L25635F: {
2244 uint8_t cr = mx25l_read_config_register(flash);
2245
2246 *wp = &mx25l25635f_wp;
2247 if (!(cr & (1 << 3))) { /* T/B == 0 */
2248 (*wp)->ranges = &mx25l25635f_tb0_ranges[0];
2249 *num_entries = ARRAY_SIZE(mx25l25635f_tb0_ranges);
2250 } else { /* T/B == 1 */
2251 (*wp)->ranges = &mx25l25635f_tb1_ranges[0];
2252 *num_entries = ARRAY_SIZE(mx25l25635f_tb1_ranges);
2253 }
2254 break;
2255 }
David Hendricks83541d32014-07-15 20:58:21 -07002256 default:
2257 msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)"
2258 ", aborting\n", __func__, __LINE__,
Patrick Georgif3fa2992017-02-02 16:24:44 +01002259 flash->chip->model_id);
David Hendricks83541d32014-07-15 20:58:21 -07002260 return -1;
2261 }
2262 break;
David Hendricksa9884852014-12-11 15:31:12 -08002263 case SPANSION_ID:
Patrick Georgif3fa2992017-02-02 16:24:44 +01002264 switch (flash->chip->model_id) {
David Hendricksa9884852014-12-11 15:31:12 -08002265 case SPANSION_S25FS128S_L:
2266 case SPANSION_S25FS128S_S: {
David Hendricksa9884852014-12-11 15:31:12 -08002267 *wp = &s25fs128s_wp;
David Hendricks148a4bf2015-03-13 21:02:42 -07002268 (*wp)->ranges = s25fs128s_ranges;
2269 *num_entries = ARRAY_SIZE(s25fs128s_ranges);
David Hendricksa9884852014-12-11 15:31:12 -08002270 break;
2271 }
David Hendricksc694bb82015-02-25 14:52:17 -08002272 case SPANSION_S25FL256S_UL:
2273 case SPANSION_S25FL256S_US: {
David Hendricksc694bb82015-02-25 14:52:17 -08002274 *wp = &s25fl256s_wp;
David Hendricks148a4bf2015-03-13 21:02:42 -07002275 (*wp)->ranges = s25fl256s_ranges;
2276 *num_entries = ARRAY_SIZE(s25fl256s_ranges);
David Hendricksc694bb82015-02-25 14:52:17 -08002277 break;
2278 }
David Hendricksa9884852014-12-11 15:31:12 -08002279 default:
2280 msg_cerr("%s():%d Spansion flash chip mismatch (0x%04x)"
Patrick Georgif3fa2992017-02-02 16:24:44 +01002281 ", aborting\n", __func__, __LINE__,
2282 flash->chip->model_id);
David Hendricksa9884852014-12-11 15:31:12 -08002283 return -1;
2284 }
2285 break;
David Hendrickse0512a72014-07-15 20:30:47 -07002286 default:
2287 msg_cerr("%s: flash vendor (0x%x) not found, aborting\n",
Patrick Georgif3fa2992017-02-02 16:24:44 +01002288 __func__, flash->chip->manufacture_id);
David Hendrickse0512a72014-07-15 20:30:47 -07002289 return -1;
2290 }
2291
2292 return 0;
2293}
2294
2295/* Given a [start, len], this function finds a block protect bit combination
2296 * (if possible) and sets the corresponding bits in "status". Remaining bits
2297 * are preserved. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002298static int generic_range_to_status(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002299 unsigned int start, unsigned int len,
2300 uint8_t *status)
2301{
2302 struct generic_wp *wp;
2303 struct generic_range *r;
2304 int i, range_found = 0, num_entries;
2305 uint8_t bp_mask;
2306
2307 if (generic_range_table(flash, &wp, &num_entries))
2308 return -1;
2309
2310 bp_mask = ((1 << (wp->sr1.bp0_pos + wp->sr1.bp_bits)) - 1) - \
2311 ((1 << wp->sr1.bp0_pos) - 1);
2312
2313 for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) {
2314 msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n",
2315 start, len, r->range.start, r->range.len);
2316 if ((start == r->range.start) && (len == r->range.len)) {
2317 *status &= ~(bp_mask);
2318 *status |= r->bp << (wp->sr1.bp0_pos);
David Hendricks148a4bf2015-03-13 21:02:42 -07002319
2320 if (wp->set_modifier_bits) {
2321 if (wp->set_modifier_bits(flash, &r->m) < 0) {
2322 msg_cerr("error setting modifier "
2323 "bits for range.\n");
2324 return -1;
2325 }
2326 }
2327
David Hendrickse0512a72014-07-15 20:30:47 -07002328 range_found = 1;
2329 break;
2330 }
2331 }
2332
2333 if (!range_found) {
2334 msg_cerr("matching range not found\n");
2335 return -1;
2336 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002337
David Hendrickse0512a72014-07-15 20:30:47 -07002338 return 0;
2339}
2340
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002341static int generic_status_to_range(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002342 const uint8_t sr1, unsigned int *start, unsigned int *len)
2343{
2344 struct generic_wp *wp;
2345 struct generic_range *r;
Duncan Laurie04ca1172015-03-12 09:25:34 -07002346 int num_entries, i, status_found = 0;
David Hendrickse0512a72014-07-15 20:30:47 -07002347 uint8_t sr1_bp;
David Hendricks148a4bf2015-03-13 21:02:42 -07002348 struct generic_modifier_bits m;
David Hendrickse0512a72014-07-15 20:30:47 -07002349
2350 if (generic_range_table(flash, &wp, &num_entries))
2351 return -1;
2352
David Hendricks148a4bf2015-03-13 21:02:42 -07002353 /* modifier bits may be compared more than once, so get them here */
2354 if (wp->get_modifier_bits) {
2355 if (wp->get_modifier_bits(flash, &m) < 0)
2356 return -1;
2357 }
2358
David Hendrickse0512a72014-07-15 20:30:47 -07002359 sr1_bp = (sr1 >> wp->sr1.bp0_pos) & ((1 << wp->sr1.bp_bits) - 1);
2360
2361 for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) {
David Hendricks148a4bf2015-03-13 21:02:42 -07002362 if (wp->get_modifier_bits) {
2363 if (memcmp(&m, &r->m, sizeof(m)))
2364 continue;
2365 }
David Hendrickse0512a72014-07-15 20:30:47 -07002366 msg_cspew("comparing 0x%02x 0x%02x\n", sr1_bp, r->bp);
2367 if (sr1_bp == r->bp) {
2368 *start = r->range.start;
2369 *len = r->range.len;
2370 status_found = 1;
2371 break;
2372 }
2373 }
2374
2375 if (!status_found) {
2376 msg_cerr("matching status not found\n");
2377 return -1;
2378 }
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002379
David Hendrickse0512a72014-07-15 20:30:47 -07002380 return 0;
2381}
2382
2383/* Given a [start, len], this function calls generic_range_to_status() to
2384 * convert it to flash-chip-specific range bits, then sets into status register.
2385 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002386static int generic_set_range(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002387 unsigned int start, unsigned int len)
2388{
2389 uint8_t status, expected;
2390
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302391 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002392 msg_cdbg("%s: old status: 0x%02x\n", __func__, status);
2393
2394 expected = status; /* preserve non-bp bits */
2395 if (generic_range_to_status(flash, start, len, &expected))
2396 return -1;
2397
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302398 do_write_status(flash, expected);
David Hendrickse0512a72014-07-15 20:30:47 -07002399
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302400 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002401 msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
2402 if (status != expected) {
2403 msg_cerr("expected=0x%02x, but actual=0x%02x.\n",
2404 expected, status);
2405 return 1;
2406 }
2407
2408 return 0;
2409}
2410
2411/* Set/clear the status regsiter write protect bit in SR1. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002412static int generic_set_srp0(const struct flashctx *flash, int enable)
David Hendrickse0512a72014-07-15 20:30:47 -07002413{
2414 uint8_t status, expected;
2415 struct generic_wp *wp;
2416 int num_entries;
2417
2418 if (generic_range_table(flash, &wp, &num_entries))
2419 return -1;
2420
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302421 expected = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002422 msg_cdbg("%s: old status: 0x%02x\n", __func__, expected);
2423
2424 if (enable)
2425 expected |= 1 << wp->sr1.srp_pos;
2426 else
2427 expected &= ~(1 << wp->sr1.srp_pos);
2428
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302429 do_write_status(flash, expected);
David Hendrickse0512a72014-07-15 20:30:47 -07002430
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302431 status = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002432 msg_cdbg("%s: new status: 0x%02x\n", __func__, status);
2433 if (status != expected)
2434 return -1;
2435
2436 return 0;
2437}
2438
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002439static int generic_enable_writeprotect(const struct flashctx *flash,
David Hendrickse0512a72014-07-15 20:30:47 -07002440 enum wp_mode wp_mode)
2441{
2442 int ret;
2443
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002444 if (wp_mode != WP_MODE_HARDWARE) {
David Hendrickse0512a72014-07-15 20:30:47 -07002445 msg_cerr("%s(): unsupported write-protect mode\n", __func__);
2446 return 1;
2447 }
2448
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002449 ret = generic_set_srp0(flash, 1);
David Hendrickse0512a72014-07-15 20:30:47 -07002450 if (ret)
2451 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanca44e5c2019-12-04 14:23:54 +11002452
David Hendrickse0512a72014-07-15 20:30:47 -07002453 return ret;
2454}
2455
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002456static int generic_disable_writeprotect(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002457{
2458 int ret;
2459
2460 ret = generic_set_srp0(flash, 0);
2461 if (ret)
2462 msg_cerr("%s(): error=%d.\n", __func__, ret);
Edward O'Callaghanbea239e2019-12-04 14:42:54 +11002463
David Hendrickse0512a72014-07-15 20:30:47 -07002464 return ret;
2465}
2466
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002467static int generic_list_ranges(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002468{
2469 struct generic_wp *wp;
2470 struct generic_range *r;
2471 int i, num_entries;
2472
2473 if (generic_range_table(flash, &wp, &num_entries))
2474 return -1;
2475
2476 r = &wp->ranges[0];
2477 for (i = 0; i < num_entries; i++) {
2478 msg_cinfo("start: 0x%06x, length: 0x%06x\n",
2479 r->range.start, r->range.len);
2480 r++;
2481 }
2482
2483 return 0;
2484}
2485
Souvik Ghoshd75cd672016-06-17 14:21:39 -07002486static int generic_wp_status(const struct flashctx *flash)
David Hendrickse0512a72014-07-15 20:30:47 -07002487{
2488 uint8_t sr1;
2489 unsigned int start, len;
2490 int ret = 0;
2491 struct generic_wp *wp;
David Hendrickse0512a72014-07-15 20:30:47 -07002492 int num_entries, wp_en;
2493
2494 if (generic_range_table(flash, &wp, &num_entries))
2495 return -1;
2496
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +05302497 sr1 = do_read_status(flash);
David Hendrickse0512a72014-07-15 20:30:47 -07002498 wp_en = (sr1 >> wp->sr1.srp_pos) & 1;
2499
2500 msg_cinfo("WP: status: 0x%04x\n", sr1);
2501 msg_cinfo("WP: status.srp0: %x\n", wp_en);
2502 /* FIXME: SRP1 is not really generic, but we probably should print
2503 * it anyway to have consistent output. #legacycruft */
2504 msg_cinfo("WP: status.srp1: %x\n", 0);
2505 msg_cinfo("WP: write protect is %s.\n",
2506 wp_en ? "enabled" : "disabled");
2507
2508 msg_cinfo("WP: write protect range: ");
2509 if (generic_status_to_range(flash, sr1, &start, &len)) {
2510 msg_cinfo("(cannot resolve the range)\n");
2511 ret = -1;
2512 } else {
2513 msg_cinfo("start=0x%08x, len=0x%08x\n", start, len);
2514 }
2515
2516 return ret;
2517}
2518
2519struct wp wp_generic = {
2520 .list_ranges = generic_list_ranges,
2521 .set_range = generic_set_range,
2522 .enable = generic_enable_writeprotect,
2523 .disable = generic_disable_writeprotect,
2524 .wp_status = generic_wp_status,
2525};