bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 emulator main execution loop |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 19 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 20 | #include "config.h" |
| 21 | #ifdef TARGET_I386 |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 22 | #include "exec-i386.h" |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 23 | #endif |
| 24 | #ifdef TARGET_ARM |
| 25 | #include "exec-arm.h" |
| 26 | #endif |
| 27 | |
bellard | 956034d | 2003-04-29 20:40:53 +0000 | [diff] [blame] | 28 | #include "disas.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 29 | |
bellard | dc99065 | 2003-03-19 00:00:28 +0000 | [diff] [blame] | 30 | //#define DEBUG_EXEC |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 31 | //#define DEBUG_SIGNAL |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 32 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 33 | #if defined(TARGET_ARM) |
| 34 | /* XXX: unify with i386 target */ |
| 35 | void cpu_loop_exit(void) |
| 36 | { |
| 37 | longjmp(env->jmp_env, 1); |
| 38 | } |
| 39 | #endif |
| 40 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 41 | /* main execution loop */ |
| 42 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 43 | int cpu_exec(CPUState *env1) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 44 | { |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 45 | int saved_T0, saved_T1, saved_T2; |
| 46 | CPUState *saved_env; |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 47 | #ifdef reg_EAX |
| 48 | int saved_EAX; |
| 49 | #endif |
| 50 | #ifdef reg_ECX |
| 51 | int saved_ECX; |
| 52 | #endif |
| 53 | #ifdef reg_EDX |
| 54 | int saved_EDX; |
| 55 | #endif |
| 56 | #ifdef reg_EBX |
| 57 | int saved_EBX; |
| 58 | #endif |
| 59 | #ifdef reg_ESP |
| 60 | int saved_ESP; |
| 61 | #endif |
| 62 | #ifdef reg_EBP |
| 63 | int saved_EBP; |
| 64 | #endif |
| 65 | #ifdef reg_ESI |
| 66 | int saved_ESI; |
| 67 | #endif |
| 68 | #ifdef reg_EDI |
| 69 | int saved_EDI; |
| 70 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 71 | #ifdef __sparc__ |
| 72 | int saved_i7, tmp_T0; |
| 73 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 74 | int code_gen_size, ret, interrupt_request; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 75 | void (*gen_func)(void); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 76 | TranslationBlock *tb, **ptb; |
bellard | dab2ed9 | 2003-03-22 15:23:14 +0000 | [diff] [blame] | 77 | uint8_t *tc_ptr, *cs_base, *pc; |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 78 | unsigned int flags; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 79 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 80 | /* first we save global registers */ |
| 81 | saved_T0 = T0; |
| 82 | saved_T1 = T1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 83 | saved_T2 = T2; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 84 | saved_env = env; |
| 85 | env = env1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 86 | #ifdef __sparc__ |
| 87 | /* we also save i7 because longjmp may not restore it */ |
| 88 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
| 89 | #endif |
| 90 | |
| 91 | #if defined(TARGET_I386) |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 92 | #ifdef reg_EAX |
| 93 | saved_EAX = EAX; |
| 94 | EAX = env->regs[R_EAX]; |
| 95 | #endif |
| 96 | #ifdef reg_ECX |
| 97 | saved_ECX = ECX; |
| 98 | ECX = env->regs[R_ECX]; |
| 99 | #endif |
| 100 | #ifdef reg_EDX |
| 101 | saved_EDX = EDX; |
| 102 | EDX = env->regs[R_EDX]; |
| 103 | #endif |
| 104 | #ifdef reg_EBX |
| 105 | saved_EBX = EBX; |
| 106 | EBX = env->regs[R_EBX]; |
| 107 | #endif |
| 108 | #ifdef reg_ESP |
| 109 | saved_ESP = ESP; |
| 110 | ESP = env->regs[R_ESP]; |
| 111 | #endif |
| 112 | #ifdef reg_EBP |
| 113 | saved_EBP = EBP; |
| 114 | EBP = env->regs[R_EBP]; |
| 115 | #endif |
| 116 | #ifdef reg_ESI |
| 117 | saved_ESI = ESI; |
| 118 | ESI = env->regs[R_ESI]; |
| 119 | #endif |
| 120 | #ifdef reg_EDI |
| 121 | saved_EDI = EDI; |
| 122 | EDI = env->regs[R_EDI]; |
| 123 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 124 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 125 | /* put eflags in CPU temporary format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 126 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 127 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 128 | CC_OP = CC_OP_EFLAGS; |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 129 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 130 | #elif defined(TARGET_ARM) |
| 131 | { |
| 132 | unsigned int psr; |
| 133 | psr = env->cpsr; |
| 134 | env->CF = (psr >> 29) & 1; |
| 135 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
| 136 | env->VF = (psr << 3) & 0x80000000; |
| 137 | env->cpsr = psr & ~0xf0000000; |
| 138 | } |
| 139 | #else |
| 140 | #error unsupported target CPU |
| 141 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 142 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 143 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 144 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 145 | for(;;) { |
| 146 | if (setjmp(env->jmp_env) == 0) { |
| 147 | /* if an exception is pending, we execute it here */ |
| 148 | if (env->exception_index >= 0) { |
| 149 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 150 | /* exit request from the cpu execution loop */ |
| 151 | ret = env->exception_index; |
| 152 | break; |
| 153 | } else if (env->user_mode_only) { |
| 154 | /* if user mode only, we simulate a fake exception |
| 155 | which will be hanlded outside the cpu execution |
| 156 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 157 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 158 | do_interrupt_user(env->exception_index, |
| 159 | env->exception_is_int, |
| 160 | env->error_code, |
| 161 | env->exception_next_eip); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 162 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 163 | ret = env->exception_index; |
| 164 | break; |
| 165 | } else { |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 166 | #if defined(TARGET_I386) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 167 | /* simulate a real cpu exception. On i386, it can |
| 168 | trigger new exceptions, but we do not handle |
| 169 | double or triple faults yet. */ |
| 170 | do_interrupt(env->exception_index, |
| 171 | env->exception_is_int, |
| 172 | env->error_code, |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 173 | env->exception_next_eip, 0); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 174 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 175 | } |
| 176 | env->exception_index = -1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 177 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 178 | T0 = 0; /* force lookup of first TB */ |
| 179 | for(;;) { |
| 180 | #ifdef __sparc__ |
| 181 | /* g1 can be modified by some libc? functions */ |
| 182 | tmp_T0 = T0; |
| 183 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 184 | interrupt_request = env->interrupt_request; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 185 | if (__builtin_expect(interrupt_request, 0)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 186 | #if defined(TARGET_I386) |
| 187 | /* if hardware interrupt pending, we execute it */ |
| 188 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 189 | (env->eflags & IF_MASK) && |
| 190 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 191 | int intno; |
| 192 | intno = cpu_x86_get_pic_interrupt(env); |
| 193 | if (loglevel) { |
| 194 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
| 195 | } |
bellard | d05e66d | 2003-08-20 21:34:35 +0000 | [diff] [blame] | 196 | do_interrupt(intno, 0, 0, 0, 1); |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 197 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
bellard | 907a5b2 | 2003-06-30 23:18:22 +0000 | [diff] [blame] | 198 | /* ensure that no TB jump will be modified as |
| 199 | the program flow was changed */ |
| 200 | #ifdef __sparc__ |
| 201 | tmp_T0 = 0; |
| 202 | #else |
| 203 | T0 = 0; |
| 204 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 205 | } |
| 206 | #endif |
| 207 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
| 208 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
| 209 | env->exception_index = EXCP_INTERRUPT; |
| 210 | cpu_loop_exit(); |
| 211 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 212 | } |
| 213 | #ifdef DEBUG_EXEC |
| 214 | if (loglevel) { |
| 215 | #if defined(TARGET_I386) |
| 216 | /* restore flags in standard format */ |
| 217 | env->regs[R_EAX] = EAX; |
| 218 | env->regs[R_EBX] = EBX; |
| 219 | env->regs[R_ECX] = ECX; |
| 220 | env->regs[R_EDX] = EDX; |
| 221 | env->regs[R_ESI] = ESI; |
| 222 | env->regs[R_EDI] = EDI; |
| 223 | env->regs[R_EBP] = EBP; |
| 224 | env->regs[R_ESP] = ESP; |
| 225 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 226 | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 227 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 228 | #elif defined(TARGET_ARM) |
bellard | 1b21b62 | 2003-07-09 17:16:27 +0000 | [diff] [blame] | 229 | env->cpsr = compute_cpsr(); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 230 | cpu_arm_dump_state(env, logfile, 0); |
bellard | 1b21b62 | 2003-07-09 17:16:27 +0000 | [diff] [blame] | 231 | env->cpsr &= ~0xf0000000; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 232 | #else |
| 233 | #error unsupported target CPU |
| 234 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 235 | } |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 236 | #endif |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 237 | /* we record a subset of the CPU state. It will |
| 238 | always be the same before a given translated block |
| 239 | is executed. */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 240 | #if defined(TARGET_I386) |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 241 | flags = env->hflags; |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 242 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 243 | cs_base = env->segs[R_CS].base; |
| 244 | pc = cs_base + env->eip; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 245 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 246 | flags = 0; |
| 247 | cs_base = 0; |
| 248 | pc = (uint8_t *)env->regs[15]; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 249 | #else |
| 250 | #error unsupported CPU |
| 251 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 252 | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
| 253 | flags); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 254 | if (!tb) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 255 | spin_lock(&tb_lock); |
| 256 | /* if no translated code available, then translate it now */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 257 | tb = tb_alloc((unsigned long)pc); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 258 | if (!tb) { |
| 259 | /* flush must be done */ |
| 260 | tb_flush(); |
| 261 | /* cannot fail at this point */ |
| 262 | tb = tb_alloc((unsigned long)pc); |
| 263 | /* don't forget to invalidate previous TB info */ |
| 264 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
| 265 | T0 = 0; |
| 266 | } |
| 267 | tc_ptr = code_gen_ptr; |
| 268 | tb->tc_ptr = tc_ptr; |
| 269 | tb->cs_base = (unsigned long)cs_base; |
| 270 | tb->flags = flags; |
bellard | facc68b | 2003-09-17 22:51:18 +0000 | [diff] [blame] | 271 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 272 | *ptb = tb; |
| 273 | tb->hash_next = NULL; |
| 274 | tb_link(tb); |
| 275 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
| 276 | spin_unlock(&tb_lock); |
| 277 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 278 | #ifdef DEBUG_EXEC |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 279 | if (loglevel) { |
| 280 | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", |
| 281 | (long)tb->tc_ptr, (long)tb->pc, |
| 282 | lookup_symbol((void *)tb->pc)); |
| 283 | } |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 284 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 285 | #ifdef __sparc__ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 286 | T0 = tmp_T0; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 287 | #endif |
bellard | facc68b | 2003-09-17 22:51:18 +0000 | [diff] [blame] | 288 | /* see if we can patch the calling TB. */ |
| 289 | if (T0 != 0) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 290 | spin_lock(&tb_lock); |
| 291 | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
| 292 | spin_unlock(&tb_lock); |
| 293 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 294 | tc_ptr = tb->tc_ptr; |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 295 | env->current_tb = tb; |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 296 | /* execute the generated code */ |
| 297 | gen_func = (void *)tc_ptr; |
| 298 | #if defined(__sparc__) |
| 299 | __asm__ __volatile__("call %0\n\t" |
| 300 | "mov %%o7,%%i0" |
| 301 | : /* no outputs */ |
| 302 | : "r" (gen_func) |
| 303 | : "i0", "i1", "i2", "i3", "i4", "i5"); |
| 304 | #elif defined(__arm__) |
| 305 | asm volatile ("mov pc, %0\n\t" |
| 306 | ".global exec_loop\n\t" |
| 307 | "exec_loop:\n\t" |
| 308 | : /* no outputs */ |
| 309 | : "r" (gen_func) |
| 310 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
| 311 | #else |
| 312 | gen_func(); |
| 313 | #endif |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 314 | env->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 315 | /* reset soft MMU for next block (it can currently |
| 316 | only be set by a memory fault) */ |
| 317 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 318 | if (env->hflags & HF_SOFTMMU_MASK) { |
| 319 | env->hflags &= ~HF_SOFTMMU_MASK; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 320 | /* do not allow linking to another block */ |
| 321 | T0 = 0; |
| 322 | } |
| 323 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 324 | } |
| 325 | } else { |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 326 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 327 | } /* for(;;) */ |
| 328 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 329 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 330 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 331 | /* restore flags in standard format */ |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 332 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 333 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 334 | /* restore global registers */ |
bellard | 04369ff | 2003-03-20 22:33:23 +0000 | [diff] [blame] | 335 | #ifdef reg_EAX |
| 336 | EAX = saved_EAX; |
| 337 | #endif |
| 338 | #ifdef reg_ECX |
| 339 | ECX = saved_ECX; |
| 340 | #endif |
| 341 | #ifdef reg_EDX |
| 342 | EDX = saved_EDX; |
| 343 | #endif |
| 344 | #ifdef reg_EBX |
| 345 | EBX = saved_EBX; |
| 346 | #endif |
| 347 | #ifdef reg_ESP |
| 348 | ESP = saved_ESP; |
| 349 | #endif |
| 350 | #ifdef reg_EBP |
| 351 | EBP = saved_EBP; |
| 352 | #endif |
| 353 | #ifdef reg_ESI |
| 354 | ESI = saved_ESI; |
| 355 | #endif |
| 356 | #ifdef reg_EDI |
| 357 | EDI = saved_EDI; |
| 358 | #endif |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 359 | #elif defined(TARGET_ARM) |
bellard | 1b21b62 | 2003-07-09 17:16:27 +0000 | [diff] [blame] | 360 | env->cpsr = compute_cpsr(); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 361 | #else |
| 362 | #error unsupported target CPU |
| 363 | #endif |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 364 | #ifdef __sparc__ |
| 365 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
| 366 | #endif |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 367 | T0 = saved_T0; |
| 368 | T1 = saved_T1; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 369 | T2 = saved_T2; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 370 | env = saved_env; |
| 371 | return ret; |
| 372 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 373 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 374 | #if defined(TARGET_I386) |
| 375 | |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 376 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
| 377 | { |
| 378 | CPUX86State *saved_env; |
| 379 | |
| 380 | saved_env = env; |
| 381 | env = s; |
bellard | a412ac5 | 2003-07-26 18:01:40 +0000 | [diff] [blame] | 382 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 383 | selector &= 0xffff; |
bellard | 2e255c6 | 2003-08-21 23:25:21 +0000 | [diff] [blame] | 384 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 385 | (uint8_t *)(selector << 4), 0xffff, 0); |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 386 | } else { |
| 387 | load_seg(seg_reg, selector, 0); |
| 388 | } |
bellard | 6dbad63 | 2003-03-16 18:05:05 +0000 | [diff] [blame] | 389 | env = saved_env; |
| 390 | } |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 391 | |
bellard | d0a1ffc | 2003-05-29 20:04:28 +0000 | [diff] [blame] | 392 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
| 393 | { |
| 394 | CPUX86State *saved_env; |
| 395 | |
| 396 | saved_env = env; |
| 397 | env = s; |
| 398 | |
| 399 | helper_fsave(ptr, data32); |
| 400 | |
| 401 | env = saved_env; |
| 402 | } |
| 403 | |
| 404 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
| 405 | { |
| 406 | CPUX86State *saved_env; |
| 407 | |
| 408 | saved_env = env; |
| 409 | env = s; |
| 410 | |
| 411 | helper_frstor(ptr, data32); |
| 412 | |
| 413 | env = saved_env; |
| 414 | } |
| 415 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 416 | #endif /* TARGET_I386 */ |
| 417 | |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 418 | #undef EAX |
| 419 | #undef ECX |
| 420 | #undef EDX |
| 421 | #undef EBX |
| 422 | #undef ESP |
| 423 | #undef EBP |
| 424 | #undef ESI |
| 425 | #undef EDI |
| 426 | #undef EIP |
| 427 | #include <signal.h> |
| 428 | #include <sys/ucontext.h> |
| 429 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 430 | #if defined(TARGET_I386) |
| 431 | |
bellard | b56dad1 | 2003-05-08 15:38:04 +0000 | [diff] [blame] | 432 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 433 | the effective address of the memory exception. 'is_write' is 1 if a |
| 434 | write caused the exception and otherwise 0'. 'old_set' is the |
| 435 | signal set which should be restored */ |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 436 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 437 | int is_write, sigset_t *old_set) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 438 | { |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 439 | TranslationBlock *tb; |
| 440 | int ret; |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 441 | |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 442 | if (cpu_single_env) |
| 443 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 444 | #if defined(DEBUG_SIGNAL) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 445 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 446 | pc, address, is_write, *(unsigned long *)old_set); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 447 | #endif |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 448 | /* XXX: locking issue */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 449 | if (is_write && page_unprotect(address)) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 450 | return 1; |
| 451 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 452 | /* see if it is an MMU fault */ |
| 453 | ret = cpu_x86_handle_mmu_fault(env, address, is_write); |
| 454 | if (ret < 0) |
| 455 | return 0; /* not an MMU fault */ |
| 456 | if (ret == 0) |
| 457 | return 1; /* the MMU fault was handled without causing real CPU fault */ |
| 458 | /* now we have a real cpu fault */ |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 459 | tb = tb_find_pc(pc); |
| 460 | if (tb) { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 461 | /* the PC is inside the translated code. It means that we have |
| 462 | a virtual CPU fault */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 463 | cpu_restore_state(tb, env, pc); |
| 464 | } |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 465 | if (ret == 1) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 466 | #if 0 |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 467 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
| 468 | env->eip, env->cr[2], env->error_code); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 469 | #endif |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 470 | /* we restore the process signal mask as the sigreturn should |
| 471 | do it (XXX: use sigsetjmp) */ |
| 472 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 473 | raise_exception_err(EXCP0E_PAGE, env->error_code); |
| 474 | } else { |
| 475 | /* activate soft MMU for this block */ |
bellard | 3f33731 | 2003-08-20 23:02:09 +0000 | [diff] [blame] | 476 | env->hflags |= HF_SOFTMMU_MASK; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 477 | sigprocmask(SIG_SETMASK, old_set, NULL); |
| 478 | cpu_loop_exit(); |
| 479 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 480 | /* never comes here */ |
| 481 | return 1; |
| 482 | } |
| 483 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 484 | #elif defined(TARGET_ARM) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 485 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
| 486 | int is_write, sigset_t *old_set) |
| 487 | { |
| 488 | /* XXX: do more */ |
| 489 | return 0; |
| 490 | } |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 491 | #else |
| 492 | #error unsupported target CPU |
| 493 | #endif |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 494 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 495 | #if defined(__i386__) |
| 496 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 497 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 498 | void *puc) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 499 | { |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 500 | struct ucontext *uc = puc; |
| 501 | unsigned long pc; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 502 | |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 503 | #ifndef REG_EIP |
| 504 | /* for glibc 2.1 */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 505 | #define REG_EIP EIP |
| 506 | #define REG_ERR ERR |
| 507 | #define REG_TRAPNO TRAPNO |
bellard | d691f66 | 2003-03-24 21:58:34 +0000 | [diff] [blame] | 508 | #endif |
bellard | fc2b4c4 | 2003-03-29 16:52:44 +0000 | [diff] [blame] | 509 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 510 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 511 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
| 512 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 513 | &uc->uc_sigmask); |
| 514 | } |
| 515 | |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 516 | #elif defined(__powerpc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 517 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 518 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 519 | void *puc) |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 520 | { |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 521 | struct ucontext *uc = puc; |
| 522 | struct pt_regs *regs = uc->uc_mcontext.regs; |
| 523 | unsigned long pc; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 524 | int is_write; |
| 525 | |
| 526 | pc = regs->nip; |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 527 | is_write = 0; |
| 528 | #if 0 |
| 529 | /* ppc 4xx case */ |
| 530 | if (regs->dsisr & 0x00800000) |
| 531 | is_write = 1; |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 532 | #else |
bellard | 25eb448 | 2003-05-14 21:50:54 +0000 | [diff] [blame] | 533 | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
| 534 | is_write = 1; |
| 535 | #endif |
| 536 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 537 | is_write, &uc->uc_sigmask); |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 538 | } |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 539 | |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 540 | #elif defined(__alpha__) |
| 541 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 542 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 543 | void *puc) |
| 544 | { |
| 545 | struct ucontext *uc = puc; |
| 546 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
| 547 | uint32_t insn = *pc; |
| 548 | int is_write = 0; |
| 549 | |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 550 | /* XXX: need kernel patch to get write flag faster */ |
bellard | 2f87c60 | 2003-06-02 20:38:09 +0000 | [diff] [blame] | 551 | switch (insn >> 26) { |
| 552 | case 0x0d: // stw |
| 553 | case 0x0e: // stb |
| 554 | case 0x0f: // stq_u |
| 555 | case 0x24: // stf |
| 556 | case 0x25: // stg |
| 557 | case 0x26: // sts |
| 558 | case 0x27: // stt |
| 559 | case 0x2c: // stl |
| 560 | case 0x2d: // stq |
| 561 | case 0x2e: // stl_c |
| 562 | case 0x2f: // stq_c |
| 563 | is_write = 1; |
| 564 | } |
| 565 | |
| 566 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 567 | is_write, &uc->uc_sigmask); |
| 568 | } |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 569 | #elif defined(__sparc__) |
| 570 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 571 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 572 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 573 | { |
| 574 | uint32_t *regs = (uint32_t *)(info + 1); |
| 575 | void *sigmask = (regs + 20); |
| 576 | unsigned long pc; |
| 577 | int is_write; |
| 578 | uint32_t insn; |
| 579 | |
| 580 | /* XXX: is there a standard glibc define ? */ |
| 581 | pc = regs[1]; |
| 582 | /* XXX: need kernel patch to get write flag faster */ |
| 583 | is_write = 0; |
| 584 | insn = *(uint32_t *)pc; |
| 585 | if ((insn >> 30) == 3) { |
| 586 | switch((insn >> 19) & 0x3f) { |
| 587 | case 0x05: // stb |
| 588 | case 0x06: // sth |
| 589 | case 0x04: // st |
| 590 | case 0x07: // std |
| 591 | case 0x24: // stf |
| 592 | case 0x27: // stdf |
| 593 | case 0x25: // stfsr |
| 594 | is_write = 1; |
| 595 | break; |
| 596 | } |
| 597 | } |
| 598 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 599 | is_write, sigmask); |
| 600 | } |
| 601 | |
| 602 | #elif defined(__arm__) |
| 603 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 604 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 605 | void *puc) |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 606 | { |
| 607 | struct ucontext *uc = puc; |
| 608 | unsigned long pc; |
| 609 | int is_write; |
| 610 | |
| 611 | pc = uc->uc_mcontext.gregs[R15]; |
| 612 | /* XXX: compute is_write */ |
| 613 | is_write = 0; |
| 614 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 615 | is_write, |
| 616 | &uc->uc_sigmask); |
| 617 | } |
| 618 | |
bellard | 38e584a | 2003-08-10 22:14:22 +0000 | [diff] [blame] | 619 | #elif defined(__mc68000) |
| 620 | |
| 621 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
| 622 | void *puc) |
| 623 | { |
| 624 | struct ucontext *uc = puc; |
| 625 | unsigned long pc; |
| 626 | int is_write; |
| 627 | |
| 628 | pc = uc->uc_mcontext.gregs[16]; |
| 629 | /* XXX: compute is_write */ |
| 630 | is_write = 0; |
| 631 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
| 632 | is_write, |
| 633 | &uc->uc_sigmask); |
| 634 | } |
| 635 | |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 636 | #else |
| 637 | |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 638 | #error host CPU specific signal handler needed |
bellard | 2b41314 | 2003-05-14 23:01:10 +0000 | [diff] [blame] | 639 | |
| 640 | #endif |