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bellardb4608c02003-06-27 17:34:32 +00001/*
2 * gdb server stub
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard34751872005-07-02 14:31:34 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellardb4608c02003-06-27 17:34:32 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
pbrook978efd62006-06-17 18:30:42 +000020#include "config.h"
bellard1fddef42005-04-17 19:16:13 +000021#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
pbrook978efd62006-06-17 18:30:42 +000028#include <fcntl.h>
bellard1fddef42005-04-17 19:16:13 +000029
30#include "qemu.h"
31#else
pbrook87ecb682007-11-17 17:14:51 +000032#include "qemu-common.h"
33#include "qemu-char.h"
34#include "sysemu.h"
35#include "gdbstub.h"
bellard1fddef42005-04-17 19:16:13 +000036#endif
bellard67b915a2004-03-31 23:37:16 +000037
bellard8f447cc2006-06-14 15:21:14 +000038#include "qemu_socket.h"
39#ifdef _WIN32
40/* XXX: these constants may be independent of the host ones even for Unix */
41#ifndef SIGTRAP
42#define SIGTRAP 5
43#endif
44#ifndef SIGINT
45#define SIGINT 2
46#endif
47#else
bellardb4608c02003-06-27 17:34:32 +000048#include <signal.h>
bellard8f447cc2006-06-14 15:21:14 +000049#endif
bellardb4608c02003-06-27 17:34:32 +000050
bellard4abe6152003-07-26 18:01:58 +000051//#define DEBUG_GDB
bellardb4608c02003-06-27 17:34:32 +000052
bellard858693c2004-03-31 18:52:07 +000053enum RSState {
54 RS_IDLE,
55 RS_GETLINE,
56 RS_CHKSUM1,
57 RS_CHKSUM2,
pbrooka2d1eba2007-01-28 03:10:55 +000058 RS_SYSCALL,
bellard858693c2004-03-31 18:52:07 +000059};
bellard858693c2004-03-31 18:52:07 +000060typedef struct GDBState {
bellard6a00d602005-11-21 23:25:50 +000061 CPUState *env; /* current CPU */
bellard41625032005-04-24 10:07:11 +000062 enum RSState state; /* parsing state */
bellard858693c2004-03-31 18:52:07 +000063 char line_buf[4096];
64 int line_buf_index;
65 int line_csum;
ths60fe76f2007-12-16 03:02:09 +000066 uint8_t last_packet[4100];
pbrook4046d912007-01-28 01:53:16 +000067 int last_packet_len;
bellard41625032005-04-24 10:07:11 +000068#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +000069 int fd;
bellard41625032005-04-24 10:07:11 +000070 int running_state;
pbrook4046d912007-01-28 01:53:16 +000071#else
72 CharDriverState *chr;
bellard41625032005-04-24 10:07:11 +000073#endif
bellard858693c2004-03-31 18:52:07 +000074} GDBState;
bellardb4608c02003-06-27 17:34:32 +000075
edgar_igl60897d32008-05-09 08:25:14 +000076/* By default use no IRQs and no timers while single stepping so as to
77 * make single stepping like an ICE HW step.
78 */
79static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
80
bellard1fddef42005-04-17 19:16:13 +000081#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +000082/* XXX: This is not thread safe. Do we care? */
83static int gdbserver_fd = -1;
84
bellard1fddef42005-04-17 19:16:13 +000085/* XXX: remove this hack. */
86static GDBState gdbserver_state;
bellard1fddef42005-04-17 19:16:13 +000087
bellard858693c2004-03-31 18:52:07 +000088static int get_char(GDBState *s)
bellardb4608c02003-06-27 17:34:32 +000089{
90 uint8_t ch;
91 int ret;
92
93 for(;;) {
bellard8f447cc2006-06-14 15:21:14 +000094 ret = recv(s->fd, &ch, 1, 0);
bellardb4608c02003-06-27 17:34:32 +000095 if (ret < 0) {
96 if (errno != EINTR && errno != EAGAIN)
97 return -1;
98 } else if (ret == 0) {
99 return -1;
100 } else {
101 break;
102 }
103 }
104 return ch;
105}
pbrook4046d912007-01-28 01:53:16 +0000106#endif
bellardb4608c02003-06-27 17:34:32 +0000107
pbrooka2d1eba2007-01-28 03:10:55 +0000108/* GDB stub state for use by semihosting syscalls. */
109static GDBState *gdb_syscall_state;
110static gdb_syscall_complete_cb gdb_current_syscall_cb;
111
112enum {
113 GDB_SYS_UNKNOWN,
114 GDB_SYS_ENABLED,
115 GDB_SYS_DISABLED,
116} gdb_syscall_mode;
117
118/* If gdb is connected when the first semihosting syscall occurs then use
119 remote gdb syscalls. Otherwise use native file IO. */
120int use_gdb_syscalls(void)
121{
122 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
123 gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
124 : GDB_SYS_DISABLED);
125 }
126 return gdb_syscall_mode == GDB_SYS_ENABLED;
127}
128
edgar_iglba70a622008-03-14 06:10:42 +0000129/* Resume execution. */
130static inline void gdb_continue(GDBState *s)
131{
132#ifdef CONFIG_USER_ONLY
133 s->running_state = 1;
134#else
135 vm_start();
136#endif
137}
138
bellard858693c2004-03-31 18:52:07 +0000139static void put_buffer(GDBState *s, const uint8_t *buf, int len)
bellardb4608c02003-06-27 17:34:32 +0000140{
pbrook4046d912007-01-28 01:53:16 +0000141#ifdef CONFIG_USER_ONLY
bellardb4608c02003-06-27 17:34:32 +0000142 int ret;
143
144 while (len > 0) {
bellard8f447cc2006-06-14 15:21:14 +0000145 ret = send(s->fd, buf, len, 0);
bellardb4608c02003-06-27 17:34:32 +0000146 if (ret < 0) {
147 if (errno != EINTR && errno != EAGAIN)
148 return;
149 } else {
150 buf += ret;
151 len -= ret;
152 }
153 }
pbrook4046d912007-01-28 01:53:16 +0000154#else
155 qemu_chr_write(s->chr, buf, len);
156#endif
bellardb4608c02003-06-27 17:34:32 +0000157}
158
159static inline int fromhex(int v)
160{
161 if (v >= '0' && v <= '9')
162 return v - '0';
163 else if (v >= 'A' && v <= 'F')
164 return v - 'A' + 10;
165 else if (v >= 'a' && v <= 'f')
166 return v - 'a' + 10;
167 else
168 return 0;
169}
170
171static inline int tohex(int v)
172{
173 if (v < 10)
174 return v + '0';
175 else
176 return v - 10 + 'a';
177}
178
179static void memtohex(char *buf, const uint8_t *mem, int len)
180{
181 int i, c;
182 char *q;
183 q = buf;
184 for(i = 0; i < len; i++) {
185 c = mem[i];
186 *q++ = tohex(c >> 4);
187 *q++ = tohex(c & 0xf);
188 }
189 *q = '\0';
190}
191
192static void hextomem(uint8_t *mem, const char *buf, int len)
193{
194 int i;
195
196 for(i = 0; i < len; i++) {
197 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
198 buf += 2;
199 }
200}
201
bellardb4608c02003-06-27 17:34:32 +0000202/* return -1 if error, 0 if OK */
bellard858693c2004-03-31 18:52:07 +0000203static int put_packet(GDBState *s, char *buf)
bellardb4608c02003-06-27 17:34:32 +0000204{
pbrook4046d912007-01-28 01:53:16 +0000205 int len, csum, i;
ths60fe76f2007-12-16 03:02:09 +0000206 uint8_t *p;
bellardb4608c02003-06-27 17:34:32 +0000207
208#ifdef DEBUG_GDB
209 printf("reply='%s'\n", buf);
210#endif
211
212 for(;;) {
pbrook4046d912007-01-28 01:53:16 +0000213 p = s->last_packet;
214 *(p++) = '$';
bellardb4608c02003-06-27 17:34:32 +0000215 len = strlen(buf);
pbrook4046d912007-01-28 01:53:16 +0000216 memcpy(p, buf, len);
217 p += len;
bellardb4608c02003-06-27 17:34:32 +0000218 csum = 0;
219 for(i = 0; i < len; i++) {
220 csum += buf[i];
221 }
pbrook4046d912007-01-28 01:53:16 +0000222 *(p++) = '#';
223 *(p++) = tohex((csum >> 4) & 0xf);
224 *(p++) = tohex((csum) & 0xf);
bellardb4608c02003-06-27 17:34:32 +0000225
pbrook4046d912007-01-28 01:53:16 +0000226 s->last_packet_len = p - s->last_packet;
thsffe8ab82007-12-16 03:16:05 +0000227 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
bellardb4608c02003-06-27 17:34:32 +0000228
pbrook4046d912007-01-28 01:53:16 +0000229#ifdef CONFIG_USER_ONLY
230 i = get_char(s);
231 if (i < 0)
bellardb4608c02003-06-27 17:34:32 +0000232 return -1;
pbrook4046d912007-01-28 01:53:16 +0000233 if (i == '+')
bellardb4608c02003-06-27 17:34:32 +0000234 break;
pbrook4046d912007-01-28 01:53:16 +0000235#else
236 break;
237#endif
bellardb4608c02003-06-27 17:34:32 +0000238 }
239 return 0;
240}
241
edgar_iglfde3fd62008-05-09 08:50:01 +0000242#if defined(TARGET_I386)
balrog5ad265e2007-10-31 00:21:35 +0000243
244#ifdef TARGET_X86_64
bellard79808572008-05-09 14:40:22 +0000245static const uint8_t gdb_x86_64_regs[16] = {
246 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
247 8, 9, 10, 11, 12, 13, 14, 15,
248};
balrog5ad265e2007-10-31 00:21:35 +0000249#endif
bellard6da41ea2004-01-04 15:48:38 +0000250
bellard79808572008-05-09 14:40:22 +0000251static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
252{
253 int i, fpus, nb_regs;
254 uint8_t *p;
ths3b46e622007-09-17 08:09:54 +0000255
bellard79808572008-05-09 14:40:22 +0000256 p = mem_buf;
257#ifdef TARGET_X86_64
258 if (env->hflags & HF_CS64_MASK) {
259 nb_regs = 16;
260 for(i = 0; i < 16; i++) {
261 *(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]);
262 p += 8;
263 }
264 *(uint64_t *)p = tswap64(env->eip);
265 p += 8;
266 } else
267#endif
268 {
269 nb_regs = 8;
270 for(i = 0; i < 8; i++) {
271 *(uint32_t *)p = tswap32(env->regs[i]);
272 p += 4;
273 }
274 *(uint32_t *)p = tswap32(env->eip);
275 p += 4;
276 }
277
278 *(uint32_t *)p = tswap32(env->eflags);
279 p += 4;
280 *(uint32_t *)p = tswap32(env->segs[R_CS].selector);
281 p += 4;
282 *(uint32_t *)p = tswap32(env->segs[R_SS].selector);
283 p += 4;
284 *(uint32_t *)p = tswap32(env->segs[R_DS].selector);
285 p += 4;
286 *(uint32_t *)p = tswap32(env->segs[R_ES].selector);
287 p += 4;
288 *(uint32_t *)p = tswap32(env->segs[R_FS].selector);
289 p += 4;
290 *(uint32_t *)p = tswap32(env->segs[R_GS].selector);
291 p += 4;
292 for(i = 0; i < 8; i++) {
293 /* XXX: convert floats */
294#ifdef USE_X86LDOUBLE
295 memcpy(p, &env->fpregs[i], 10);
296#else
297 memset(p, 0, 10);
298#endif
299 p += 10;
300 }
301 *(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
302 p += 4;
303 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
304 *(uint32_t *)p = tswap32(fpus); /* fstat */
305 p += 4;
306 *(uint32_t *)p = 0; /* ftag */
307 p += 4;
308 *(uint32_t *)p = 0; /* fiseg */
309 p += 4;
310 *(uint32_t *)p = 0; /* fioff */
311 p += 4;
312 *(uint32_t *)p = 0; /* foseg */
313 p += 4;
314 *(uint32_t *)p = 0; /* fooff */
315 p += 4;
316 *(uint32_t *)p = 0; /* fop */
317 p += 4;
318 for(i = 0; i < nb_regs; i++) {
319 *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
320 p += 8;
321 *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
322 p += 8;
323 }
324 *(uint32_t *)p = tswap32(env->mxcsr);
325 p += 4;
326 return p - mem_buf;
327}
328
329static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp,
330 int sreg)
331{
332 const uint8_t *p;
333 uint32_t sel;
334 p = *pp;
335 sel = tswap32(*(uint32_t *)p);
336 p += 4;
337 if (sel != env->segs[sreg].selector) {
338#if defined(CONFIG_USER_ONLY)
339 cpu_x86_load_seg(env, sreg, sel);
340#else
341 /* XXX: do it with a debug function which does not raise an
342 exception */
343#endif
344 }
345 *pp = p;
bellard6da41ea2004-01-04 15:48:38 +0000346}
347
348static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
349{
bellard79808572008-05-09 14:40:22 +0000350 const uint8_t *p = mem_buf;
351 int i, nb_regs;
352 uint16_t fpus;
bellard6da41ea2004-01-04 15:48:38 +0000353
bellard79808572008-05-09 14:40:22 +0000354#ifdef TARGET_X86_64
355 if (env->hflags & HF_CS64_MASK) {
356 nb_regs = 16;
357 for(i = 0; i < 16; i++) {
358 env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p);
359 p += 8;
360 }
361 env->eip = tswap64(*(uint64_t *)p);
362 p += 8;
363 } else
bellard6da41ea2004-01-04 15:48:38 +0000364#endif
bellard79808572008-05-09 14:40:22 +0000365 {
366 nb_regs = 8;
367 for(i = 0; i < 8; i++) {
368 env->regs[i] = tswap32(*(uint32_t *)p);
369 p += 4;
370 }
371 env->eip = tswap32(*(uint32_t *)p);
372 p += 4;
373 }
374 env->eflags = tswap32(*(uint32_t *)p);
375 p += 4;
376 cpu_gdb_load_seg(env, &p, R_CS);
377 cpu_gdb_load_seg(env, &p, R_SS);
378 cpu_gdb_load_seg(env, &p, R_DS);
379 cpu_gdb_load_seg(env, &p, R_ES);
380 cpu_gdb_load_seg(env, &p, R_FS);
381 cpu_gdb_load_seg(env, &p, R_GS);
382
383 /* FPU state */
384 for(i = 0; i < 8; i++) {
385 /* XXX: convert floats */
386#ifdef USE_X86LDOUBLE
387 memcpy(&env->fpregs[i], p, 10);
388#endif
389 p += 10;
390 }
391 env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
392 p += 4;
393 fpus = tswap32(*(uint32_t *)p);
394 p += 4;
395 env->fpstt = (fpus >> 11) & 7;
396 env->fpus = fpus & ~0x3800;
397 p += 4 * 6;
398
399 if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
400 /* SSE state */
401 for(i = 0; i < nb_regs; i++) {
402 env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
403 p += 8;
404 env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
405 p += 8;
406 }
407 env->mxcsr = tswap32(*(uint32_t *)p);
408 p += 4;
409 }
bellard6da41ea2004-01-04 15:48:38 +0000410}
411
bellard9e62fd72004-01-05 22:49:06 +0000412#elif defined (TARGET_PPC)
bellard9e62fd72004-01-05 22:49:06 +0000413static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
414{
bellarda541f292004-04-12 20:39:29 +0000415 uint32_t *registers = (uint32_t *)mem_buf, tmp;
bellard9e62fd72004-01-05 22:49:06 +0000416 int i;
417
418 /* fill in gprs */
bellarda541f292004-04-12 20:39:29 +0000419 for(i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000420 registers[i] = tswapl(env->gpr[i]);
bellard9e62fd72004-01-05 22:49:06 +0000421 }
422 /* fill in fprs */
423 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000424 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
425 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
bellard9e62fd72004-01-05 22:49:06 +0000426 }
427 /* nip, msr, ccr, lnk, ctr, xer, mq */
bellarde95c8d52004-09-30 22:22:08 +0000428 registers[96] = tswapl(env->nip);
j_mayer0411a972007-10-25 21:35:50 +0000429 registers[97] = tswapl(env->msr);
bellard9e62fd72004-01-05 22:49:06 +0000430 tmp = 0;
431 for (i = 0; i < 8; i++)
bellarda541f292004-04-12 20:39:29 +0000432 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
bellarde95c8d52004-09-30 22:22:08 +0000433 registers[98] = tswapl(tmp);
434 registers[99] = tswapl(env->lr);
435 registers[100] = tswapl(env->ctr);
j_mayer76a66252007-03-07 08:32:30 +0000436 registers[101] = tswapl(ppc_load_xer(env));
bellarde95c8d52004-09-30 22:22:08 +0000437 registers[102] = 0;
bellard9e62fd72004-01-05 22:49:06 +0000438
bellarda541f292004-04-12 20:39:29 +0000439 return 103 * 4;
bellard9e62fd72004-01-05 22:49:06 +0000440}
441
442static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
443{
444 uint32_t *registers = (uint32_t *)mem_buf;
445 int i;
446
447 /* fill in gprs */
448 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000449 env->gpr[i] = tswapl(registers[i]);
bellard9e62fd72004-01-05 22:49:06 +0000450 }
451 /* fill in fprs */
452 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000453 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
454 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
bellard9e62fd72004-01-05 22:49:06 +0000455 }
456 /* nip, msr, ccr, lnk, ctr, xer, mq */
bellarde95c8d52004-09-30 22:22:08 +0000457 env->nip = tswapl(registers[96]);
j_mayer0411a972007-10-25 21:35:50 +0000458 ppc_store_msr(env, tswapl(registers[97]));
bellarde95c8d52004-09-30 22:22:08 +0000459 registers[98] = tswapl(registers[98]);
bellard9e62fd72004-01-05 22:49:06 +0000460 for (i = 0; i < 8; i++)
bellarda541f292004-04-12 20:39:29 +0000461 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
bellarde95c8d52004-09-30 22:22:08 +0000462 env->lr = tswapl(registers[99]);
463 env->ctr = tswapl(registers[100]);
j_mayer76a66252007-03-07 08:32:30 +0000464 ppc_store_xer(env, tswapl(registers[101]));
bellarde95c8d52004-09-30 22:22:08 +0000465}
466#elif defined (TARGET_SPARC)
467static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
468{
bellard34751872005-07-02 14:31:34 +0000469 target_ulong *registers = (target_ulong *)mem_buf;
bellarde95c8d52004-09-30 22:22:08 +0000470 int i;
471
472 /* fill in g0..g7 */
bellard48b2c192005-10-30 16:08:23 +0000473 for(i = 0; i < 8; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000474 registers[i] = tswapl(env->gregs[i]);
475 }
476 /* fill in register window */
477 for(i = 0; i < 24; i++) {
478 registers[i + 8] = tswapl(env->regwptr[i]);
479 }
bellard9d9754a2006-06-25 15:32:37 +0000480#ifndef TARGET_SPARC64
bellarde95c8d52004-09-30 22:22:08 +0000481 /* fill in fprs */
482 for (i = 0; i < 32; i++) {
483 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
484 }
485 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
486 registers[64] = tswapl(env->y);
bellard34751872005-07-02 14:31:34 +0000487 {
488 target_ulong tmp;
489
490 tmp = GET_PSR(env);
491 registers[65] = tswapl(tmp);
492 }
bellarde95c8d52004-09-30 22:22:08 +0000493 registers[66] = tswapl(env->wim);
494 registers[67] = tswapl(env->tbr);
495 registers[68] = tswapl(env->pc);
496 registers[69] = tswapl(env->npc);
497 registers[70] = tswapl(env->fsr);
498 registers[71] = 0; /* csr */
499 registers[72] = 0;
bellard34751872005-07-02 14:31:34 +0000500 return 73 * sizeof(target_ulong);
501#else
bellard9d9754a2006-06-25 15:32:37 +0000502 /* fill in fprs */
503 for (i = 0; i < 64; i += 2) {
504 uint64_t tmp;
505
blueswir189795962007-04-14 16:15:48 +0000506 tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
507 tmp |= *(uint32_t *)&env->fpr[i + 1];
508 registers[i / 2 + 32] = tswap64(tmp);
bellard34751872005-07-02 14:31:34 +0000509 }
bellard9d9754a2006-06-25 15:32:37 +0000510 registers[64] = tswapl(env->pc);
511 registers[65] = tswapl(env->npc);
blueswir117d996e2007-07-07 20:53:22 +0000512 registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
513 ((env->asi & 0xff) << 24) |
514 ((env->pstate & 0xfff) << 8) |
515 GET_CWP64(env));
bellard9d9754a2006-06-25 15:32:37 +0000516 registers[67] = tswapl(env->fsr);
517 registers[68] = tswapl(env->fprs);
518 registers[69] = tswapl(env->y);
519 return 70 * sizeof(target_ulong);
bellard34751872005-07-02 14:31:34 +0000520#endif
bellarde95c8d52004-09-30 22:22:08 +0000521}
522
523static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
524{
bellard34751872005-07-02 14:31:34 +0000525 target_ulong *registers = (target_ulong *)mem_buf;
bellarde95c8d52004-09-30 22:22:08 +0000526 int i;
527
528 /* fill in g0..g7 */
529 for(i = 0; i < 7; i++) {
530 env->gregs[i] = tswapl(registers[i]);
531 }
532 /* fill in register window */
533 for(i = 0; i < 24; i++) {
bellard34751872005-07-02 14:31:34 +0000534 env->regwptr[i] = tswapl(registers[i + 8]);
bellarde95c8d52004-09-30 22:22:08 +0000535 }
bellard9d9754a2006-06-25 15:32:37 +0000536#ifndef TARGET_SPARC64
bellarde95c8d52004-09-30 22:22:08 +0000537 /* fill in fprs */
538 for (i = 0; i < 32; i++) {
539 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
540 }
541 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
542 env->y = tswapl(registers[64]);
bellarde80cfcf2004-12-19 23:18:01 +0000543 PUT_PSR(env, tswapl(registers[65]));
bellarde95c8d52004-09-30 22:22:08 +0000544 env->wim = tswapl(registers[66]);
545 env->tbr = tswapl(registers[67]);
546 env->pc = tswapl(registers[68]);
547 env->npc = tswapl(registers[69]);
548 env->fsr = tswapl(registers[70]);
bellard34751872005-07-02 14:31:34 +0000549#else
bellard9d9754a2006-06-25 15:32:37 +0000550 for (i = 0; i < 64; i += 2) {
blueswir189795962007-04-14 16:15:48 +0000551 uint64_t tmp;
552
553 tmp = tswap64(registers[i / 2 + 32]);
554 *((uint32_t *)&env->fpr[i]) = tmp >> 32;
555 *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
bellard34751872005-07-02 14:31:34 +0000556 }
bellard9d9754a2006-06-25 15:32:37 +0000557 env->pc = tswapl(registers[64]);
558 env->npc = tswapl(registers[65]);
blueswir117d996e2007-07-07 20:53:22 +0000559 {
560 uint64_t tmp = tswapl(registers[66]);
561
562 PUT_CCR(env, tmp >> 32);
563 env->asi = (tmp >> 24) & 0xff;
564 env->pstate = (tmp >> 8) & 0xfff;
565 PUT_CWP64(env, tmp & 0xff);
566 }
bellard9d9754a2006-06-25 15:32:37 +0000567 env->fsr = tswapl(registers[67]);
568 env->fprs = tswapl(registers[68]);
569 env->y = tswapl(registers[69]);
bellard34751872005-07-02 14:31:34 +0000570#endif
bellard9e62fd72004-01-05 22:49:06 +0000571}
bellard1fddef42005-04-17 19:16:13 +0000572#elif defined (TARGET_ARM)
573static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
574{
575 int i;
576 uint8_t *ptr;
bellard6da41ea2004-01-04 15:48:38 +0000577
bellard1fddef42005-04-17 19:16:13 +0000578 ptr = mem_buf;
579 /* 16 core integer registers (4 bytes each). */
580 for (i = 0; i < 16; i++)
581 {
582 *(uint32_t *)ptr = tswapl(env->regs[i]);
583 ptr += 4;
584 }
585 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
586 Not yet implemented. */
587 memset (ptr, 0, 8 * 12 + 4);
588 ptr += 8 * 12 + 4;
589 /* CPSR (4 bytes). */
bellardb5ff1b32005-11-26 10:38:39 +0000590 *(uint32_t *)ptr = tswapl (cpsr_read(env));
bellard1fddef42005-04-17 19:16:13 +0000591 ptr += 4;
592
593 return ptr - mem_buf;
594}
595
596static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
597{
598 int i;
599 uint8_t *ptr;
600
601 ptr = mem_buf;
602 /* Core integer registers. */
603 for (i = 0; i < 16; i++)
604 {
605 env->regs[i] = tswapl(*(uint32_t *)ptr);
606 ptr += 4;
607 }
608 /* Ignore FPA regs and scr. */
609 ptr += 8 * 12 + 4;
bellardb5ff1b32005-11-26 10:38:39 +0000610 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
bellard1fddef42005-04-17 19:16:13 +0000611}
pbrooke6e59062006-10-22 00:18:54 +0000612#elif defined (TARGET_M68K)
613static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
614{
615 int i;
616 uint8_t *ptr;
617 CPU_DoubleU u;
618
619 ptr = mem_buf;
620 /* D0-D7 */
621 for (i = 0; i < 8; i++) {
622 *(uint32_t *)ptr = tswapl(env->dregs[i]);
623 ptr += 4;
624 }
625 /* A0-A7 */
626 for (i = 0; i < 8; i++) {
627 *(uint32_t *)ptr = tswapl(env->aregs[i]);
628 ptr += 4;
629 }
630 *(uint32_t *)ptr = tswapl(env->sr);
631 ptr += 4;
632 *(uint32_t *)ptr = tswapl(env->pc);
633 ptr += 4;
634 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
635 ColdFire has 8-bit double precision registers. */
636 for (i = 0; i < 8; i++) {
637 u.d = env->fregs[i];
638 *(uint32_t *)ptr = tswap32(u.l.upper);
639 *(uint32_t *)ptr = tswap32(u.l.lower);
640 }
641 /* FP control regs (not implemented). */
642 memset (ptr, 0, 3 * 4);
643 ptr += 3 * 4;
644
645 return ptr - mem_buf;
646}
647
648static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
649{
650 int i;
651 uint8_t *ptr;
652 CPU_DoubleU u;
653
654 ptr = mem_buf;
655 /* D0-D7 */
656 for (i = 0; i < 8; i++) {
657 env->dregs[i] = tswapl(*(uint32_t *)ptr);
658 ptr += 4;
659 }
660 /* A0-A7 */
661 for (i = 0; i < 8; i++) {
662 env->aregs[i] = tswapl(*(uint32_t *)ptr);
663 ptr += 4;
664 }
665 env->sr = tswapl(*(uint32_t *)ptr);
666 ptr += 4;
667 env->pc = tswapl(*(uint32_t *)ptr);
668 ptr += 4;
669 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
670 ColdFire has 8-bit double precision registers. */
671 for (i = 0; i < 8; i++) {
ths5fafdf22007-09-16 21:08:06 +0000672 u.l.upper = tswap32(*(uint32_t *)ptr);
pbrooke6e59062006-10-22 00:18:54 +0000673 u.l.lower = tswap32(*(uint32_t *)ptr);
674 env->fregs[i] = u.d;
675 }
676 /* FP control regs (not implemented). */
677 ptr += 3 * 4;
678}
bellard6f970bd2005-12-05 19:55:19 +0000679#elif defined (TARGET_MIPS)
680static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
681{
682 int i;
683 uint8_t *ptr;
684
685 ptr = mem_buf;
686 for (i = 0; i < 32; i++)
687 {
thsd0dc7dc2008-02-12 21:01:26 +0000688 *(target_ulong *)ptr = tswapl(env->gpr[env->current_tc][i]);
ths2052caa2007-06-01 13:18:19 +0000689 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000690 }
691
ths7ac256b2007-10-25 21:30:37 +0000692 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
ths2052caa2007-06-01 13:18:19 +0000693 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000694
thsd0dc7dc2008-02-12 21:01:26 +0000695 *(target_ulong *)ptr = tswapl(env->LO[env->current_tc][0]);
ths2052caa2007-06-01 13:18:19 +0000696 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000697
thsd0dc7dc2008-02-12 21:01:26 +0000698 *(target_ulong *)ptr = tswapl(env->HI[env->current_tc][0]);
ths2052caa2007-06-01 13:18:19 +0000699 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000700
ths2052caa2007-06-01 13:18:19 +0000701 *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
702 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000703
ths7ac256b2007-10-25 21:30:37 +0000704 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
ths2052caa2007-06-01 13:18:19 +0000705 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000706
thsead93602007-09-06 00:18:15 +0000707 *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
ths2052caa2007-06-01 13:18:19 +0000708 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000709
ths36d23952007-02-28 22:37:42 +0000710 if (env->CP0_Config1 & (1 << CP0C1_FP))
ths8e33c082006-12-11 19:22:27 +0000711 {
ths36d23952007-02-28 22:37:42 +0000712 for (i = 0; i < 32; i++)
713 {
ths7ac256b2007-10-25 21:30:37 +0000714 if (env->CP0_Status & (1 << CP0St_FR))
715 *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
716 else
717 *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
ths2052caa2007-06-01 13:18:19 +0000718 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000719 }
720
ths7ac256b2007-10-25 21:30:37 +0000721 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
ths2052caa2007-06-01 13:18:19 +0000722 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000723
ths7ac256b2007-10-25 21:30:37 +0000724 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
ths2052caa2007-06-01 13:18:19 +0000725 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000726 }
727
ths7ac256b2007-10-25 21:30:37 +0000728 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
729 *(target_ulong *)ptr = 0;
730 ptr += sizeof(target_ulong);
731
732 /* Registers for embedded use, we just pad them. */
733 for (i = 0; i < 16; i++)
734 {
735 *(target_ulong *)ptr = 0;
736 ptr += sizeof(target_ulong);
737 }
738
739 /* Processor ID. */
740 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
741 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000742
743 return ptr - mem_buf;
744}
745
ths8e33c082006-12-11 19:22:27 +0000746/* convert MIPS rounding mode in FCR31 to IEEE library */
747static unsigned int ieee_rm[] =
748 {
749 float_round_nearest_even,
750 float_round_to_zero,
751 float_round_up,
752 float_round_down
753 };
754#define RESTORE_ROUNDING_MODE \
thsead93602007-09-06 00:18:15 +0000755 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
ths8e33c082006-12-11 19:22:27 +0000756
bellard6f970bd2005-12-05 19:55:19 +0000757static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
758{
759 int i;
760 uint8_t *ptr;
761
762 ptr = mem_buf;
763 for (i = 0; i < 32; i++)
764 {
thsd0dc7dc2008-02-12 21:01:26 +0000765 env->gpr[env->current_tc][i] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000766 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000767 }
768
ths2052caa2007-06-01 13:18:19 +0000769 env->CP0_Status = tswapl(*(target_ulong *)ptr);
770 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000771
thsd0dc7dc2008-02-12 21:01:26 +0000772 env->LO[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000773 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000774
thsd0dc7dc2008-02-12 21:01:26 +0000775 env->HI[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000776 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000777
ths2052caa2007-06-01 13:18:19 +0000778 env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
779 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000780
ths2052caa2007-06-01 13:18:19 +0000781 env->CP0_Cause = tswapl(*(target_ulong *)ptr);
782 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000783
thsead93602007-09-06 00:18:15 +0000784 env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000785 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000786
ths36d23952007-02-28 22:37:42 +0000787 if (env->CP0_Config1 & (1 << CP0C1_FP))
ths8e33c082006-12-11 19:22:27 +0000788 {
ths36d23952007-02-28 22:37:42 +0000789 for (i = 0; i < 32; i++)
790 {
ths7ac256b2007-10-25 21:30:37 +0000791 if (env->CP0_Status & (1 << CP0St_FR))
792 env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
793 else
794 env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000795 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000796 }
797
ths7ac256b2007-10-25 21:30:37 +0000798 env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
ths2052caa2007-06-01 13:18:19 +0000799 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000800
ths7ac256b2007-10-25 21:30:37 +0000801 /* The remaining registers are assumed to be read-only. */
ths8e33c082006-12-11 19:22:27 +0000802
ths36d23952007-02-28 22:37:42 +0000803 /* set rounding mode */
804 RESTORE_ROUNDING_MODE;
ths8e33c082006-12-11 19:22:27 +0000805
806#ifndef CONFIG_SOFTFLOAT
ths36d23952007-02-28 22:37:42 +0000807 /* no floating point exception for native float */
808 SET_FP_ENABLE(env->fcr31, 0);
ths8e33c082006-12-11 19:22:27 +0000809#endif
ths36d23952007-02-28 22:37:42 +0000810 }
bellard6f970bd2005-12-05 19:55:19 +0000811}
bellardfdf9b3e2006-04-27 21:07:38 +0000812#elif defined (TARGET_SH4)
ths6ef99fc2007-05-13 16:36:24 +0000813
814/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
815
bellardfdf9b3e2006-04-27 21:07:38 +0000816static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
817{
818 uint32_t *ptr = (uint32_t *)mem_buf;
819 int i;
820
821#define SAVE(x) *ptr++=tswapl(x)
pbrook9c2a9ea2006-06-18 19:12:54 +0000822 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
823 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
824 } else {
825 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
826 }
827 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
bellardfdf9b3e2006-04-27 21:07:38 +0000828 SAVE (env->pc);
829 SAVE (env->pr);
830 SAVE (env->gbr);
831 SAVE (env->vbr);
832 SAVE (env->mach);
833 SAVE (env->macl);
834 SAVE (env->sr);
ths6ef99fc2007-05-13 16:36:24 +0000835 SAVE (env->fpul);
836 SAVE (env->fpscr);
837 for (i = 0; i < 16; i++)
838 SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
839 SAVE (env->ssr);
840 SAVE (env->spc);
841 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
842 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
bellardfdf9b3e2006-04-27 21:07:38 +0000843 return ((uint8_t *)ptr - mem_buf);
844}
845
846static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
847{
848 uint32_t *ptr = (uint32_t *)mem_buf;
849 int i;
850
851#define LOAD(x) (x)=*ptr++;
pbrook9c2a9ea2006-06-18 19:12:54 +0000852 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
853 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
854 } else {
855 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
856 }
857 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
bellardfdf9b3e2006-04-27 21:07:38 +0000858 LOAD (env->pc);
859 LOAD (env->pr);
860 LOAD (env->gbr);
861 LOAD (env->vbr);
862 LOAD (env->mach);
863 LOAD (env->macl);
864 LOAD (env->sr);
ths6ef99fc2007-05-13 16:36:24 +0000865 LOAD (env->fpul);
866 LOAD (env->fpscr);
867 for (i = 0; i < 16; i++)
868 LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
869 LOAD (env->ssr);
870 LOAD (env->spc);
871 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
872 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
bellardfdf9b3e2006-04-27 21:07:38 +0000873}
thsf1ccf902007-10-08 13:16:14 +0000874#elif defined (TARGET_CRIS)
875
876static int cris_save_32 (unsigned char *d, uint32_t value)
877{
878 *d++ = (value);
879 *d++ = (value >>= 8);
880 *d++ = (value >>= 8);
881 *d++ = (value >>= 8);
882 return 4;
883}
884static int cris_save_16 (unsigned char *d, uint32_t value)
885{
886 *d++ = (value);
887 *d++ = (value >>= 8);
888 return 2;
889}
890static int cris_save_8 (unsigned char *d, uint32_t value)
891{
892 *d++ = (value);
893 return 1;
894}
895
896/* FIXME: this will bug on archs not supporting unaligned word accesses. */
897static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
898{
899 uint8_t *ptr = mem_buf;
900 uint8_t srs;
901 int i;
902
903 for (i = 0; i < 16; i++)
904 ptr += cris_save_32 (ptr, env->regs[i]);
905
edgar_igl90046272008-02-28 08:28:32 +0000906 srs = env->pregs[PR_SRS];
thsf1ccf902007-10-08 13:16:14 +0000907
908 ptr += cris_save_8 (ptr, env->pregs[0]);
909 ptr += cris_save_8 (ptr, env->pregs[1]);
910 ptr += cris_save_32 (ptr, env->pregs[2]);
911 ptr += cris_save_8 (ptr, srs);
912 ptr += cris_save_16 (ptr, env->pregs[4]);
913
914 for (i = 5; i < 16; i++)
915 ptr += cris_save_32 (ptr, env->pregs[i]);
916
917 ptr += cris_save_32 (ptr, env->pc);
918
919 for (i = 0; i < 16; i++)
920 ptr += cris_save_32 (ptr, env->sregs[srs][i]);
921
922 return ((uint8_t *)ptr - mem_buf);
923}
924
925static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
926{
927 uint32_t *ptr = (uint32_t *)mem_buf;
928 int i;
929
930#define LOAD(x) (x)=*ptr++;
931 for (i = 0; i < 16; i++) LOAD(env->regs[i]);
932 LOAD (env->pc);
933}
bellard1fddef42005-04-17 19:16:13 +0000934#else
bellard6da41ea2004-01-04 15:48:38 +0000935static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
936{
937 return 0;
938}
939
940static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
941{
942}
943
944#endif
bellardb4608c02003-06-27 17:34:32 +0000945
bellard1fddef42005-04-17 19:16:13 +0000946static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
bellardb4608c02003-06-27 17:34:32 +0000947{
bellardb4608c02003-06-27 17:34:32 +0000948 const char *p;
bellard858693c2004-03-31 18:52:07 +0000949 int ch, reg_size, type;
bellardb4608c02003-06-27 17:34:32 +0000950 char buf[4096];
thsf1ccf902007-10-08 13:16:14 +0000951 uint8_t mem_buf[4096];
bellardb4608c02003-06-27 17:34:32 +0000952 uint32_t *registers;
bellard9d9754a2006-06-25 15:32:37 +0000953 target_ulong addr, len;
ths3b46e622007-09-17 08:09:54 +0000954
bellard858693c2004-03-31 18:52:07 +0000955#ifdef DEBUG_GDB
956 printf("command='%s'\n", line_buf);
bellard4c3a88a2003-07-26 12:06:08 +0000957#endif
bellard858693c2004-03-31 18:52:07 +0000958 p = line_buf;
959 ch = *p++;
960 switch(ch) {
961 case '?':
bellard1fddef42005-04-17 19:16:13 +0000962 /* TODO: Make this return the correct value for user-mode. */
bellard858693c2004-03-31 18:52:07 +0000963 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
964 put_packet(s, buf);
edgar_igl7d03f822008-05-17 18:58:29 +0000965 /* Remove all the breakpoints when this query is issued,
966 * because gdb is doing and initial connect and the state
967 * should be cleaned up.
968 */
969 cpu_breakpoint_remove_all(env);
970 cpu_watchpoint_remove_all(env);
bellard858693c2004-03-31 18:52:07 +0000971 break;
972 case 'c':
973 if (*p != '\0') {
bellard9d9754a2006-06-25 15:32:37 +0000974 addr = strtoull(p, (char **)&p, 16);
bellardc33a3462003-07-29 20:50:33 +0000975#if defined(TARGET_I386)
bellard858693c2004-03-31 18:52:07 +0000976 env->eip = addr;
bellard5be1a8e2004-01-04 23:51:58 +0000977#elif defined (TARGET_PPC)
bellard858693c2004-03-31 18:52:07 +0000978 env->nip = addr;
bellard8d5f07f2004-10-04 21:23:09 +0000979#elif defined (TARGET_SPARC)
980 env->pc = addr;
981 env->npc = addr + 4;
bellardb5ff1b32005-11-26 10:38:39 +0000982#elif defined (TARGET_ARM)
983 env->regs[15] = addr;
bellardfdf9b3e2006-04-27 21:07:38 +0000984#elif defined (TARGET_SH4)
ths8fac5802007-07-12 10:05:07 +0000985 env->pc = addr;
986#elif defined (TARGET_MIPS)
thsead93602007-09-06 00:18:15 +0000987 env->PC[env->current_tc] = addr;
thsf1ccf902007-10-08 13:16:14 +0000988#elif defined (TARGET_CRIS)
989 env->pc = addr;
bellardc33a3462003-07-29 20:50:33 +0000990#endif
bellard858693c2004-03-31 18:52:07 +0000991 }
edgar_iglba70a622008-03-14 06:10:42 +0000992 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +0000993 return RS_IDLE;
edgar_igl7d03f822008-05-17 18:58:29 +0000994 case 'k':
995 /* Kill the target */
996 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
997 exit(0);
998 case 'D':
999 /* Detach packet */
1000 cpu_breakpoint_remove_all(env);
1001 cpu_watchpoint_remove_all(env);
1002 gdb_continue(s);
1003 put_packet(s, "OK");
1004 break;
bellard858693c2004-03-31 18:52:07 +00001005 case 's':
1006 if (*p != '\0') {
ths8fac5802007-07-12 10:05:07 +00001007 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001008#if defined(TARGET_I386)
1009 env->eip = addr;
1010#elif defined (TARGET_PPC)
1011 env->nip = addr;
bellard8d5f07f2004-10-04 21:23:09 +00001012#elif defined (TARGET_SPARC)
1013 env->pc = addr;
1014 env->npc = addr + 4;
bellardb5ff1b32005-11-26 10:38:39 +00001015#elif defined (TARGET_ARM)
1016 env->regs[15] = addr;
bellardfdf9b3e2006-04-27 21:07:38 +00001017#elif defined (TARGET_SH4)
ths8fac5802007-07-12 10:05:07 +00001018 env->pc = addr;
1019#elif defined (TARGET_MIPS)
thsead93602007-09-06 00:18:15 +00001020 env->PC[env->current_tc] = addr;
thsf1ccf902007-10-08 13:16:14 +00001021#elif defined (TARGET_CRIS)
1022 env->pc = addr;
bellard858693c2004-03-31 18:52:07 +00001023#endif
1024 }
edgar_igl60897d32008-05-09 08:25:14 +00001025 cpu_single_step(env, sstep_flags);
edgar_iglba70a622008-03-14 06:10:42 +00001026 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +00001027 return RS_IDLE;
pbrooka2d1eba2007-01-28 03:10:55 +00001028 case 'F':
1029 {
1030 target_ulong ret;
1031 target_ulong err;
1032
1033 ret = strtoull(p, (char **)&p, 16);
1034 if (*p == ',') {
1035 p++;
1036 err = strtoull(p, (char **)&p, 16);
1037 } else {
1038 err = 0;
1039 }
1040 if (*p == ',')
1041 p++;
1042 type = *p;
1043 if (gdb_current_syscall_cb)
1044 gdb_current_syscall_cb(s->env, ret, err);
1045 if (type == 'C') {
1046 put_packet(s, "T02");
1047 } else {
edgar_iglba70a622008-03-14 06:10:42 +00001048 gdb_continue(s);
pbrooka2d1eba2007-01-28 03:10:55 +00001049 }
1050 }
1051 break;
bellard858693c2004-03-31 18:52:07 +00001052 case 'g':
1053 reg_size = cpu_gdb_read_registers(env, mem_buf);
1054 memtohex(buf, mem_buf, reg_size);
1055 put_packet(s, buf);
1056 break;
1057 case 'G':
1058 registers = (void *)mem_buf;
1059 len = strlen(p) / 2;
1060 hextomem((uint8_t *)registers, p, len);
1061 cpu_gdb_write_registers(env, mem_buf, len);
1062 put_packet(s, "OK");
1063 break;
1064 case 'm':
bellard9d9754a2006-06-25 15:32:37 +00001065 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001066 if (*p == ',')
1067 p++;
bellard9d9754a2006-06-25 15:32:37 +00001068 len = strtoull(p, NULL, 16);
bellard6f970bd2005-12-05 19:55:19 +00001069 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
1070 put_packet (s, "E14");
1071 } else {
1072 memtohex(buf, mem_buf, len);
1073 put_packet(s, buf);
1074 }
bellard858693c2004-03-31 18:52:07 +00001075 break;
1076 case 'M':
bellard9d9754a2006-06-25 15:32:37 +00001077 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001078 if (*p == ',')
1079 p++;
bellard9d9754a2006-06-25 15:32:37 +00001080 len = strtoull(p, (char **)&p, 16);
bellardb328f872005-01-17 22:03:16 +00001081 if (*p == ':')
bellard858693c2004-03-31 18:52:07 +00001082 p++;
1083 hextomem(mem_buf, p, len);
1084 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
bellard905f20b2005-04-26 21:09:55 +00001085 put_packet(s, "E14");
bellard858693c2004-03-31 18:52:07 +00001086 else
1087 put_packet(s, "OK");
1088 break;
1089 case 'Z':
1090 type = strtoul(p, (char **)&p, 16);
1091 if (*p == ',')
1092 p++;
bellard9d9754a2006-06-25 15:32:37 +00001093 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001094 if (*p == ',')
1095 p++;
bellard9d9754a2006-06-25 15:32:37 +00001096 len = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001097 if (type == 0 || type == 1) {
1098 if (cpu_breakpoint_insert(env, addr) < 0)
bellard4c3a88a2003-07-26 12:06:08 +00001099 goto breakpoint_error;
bellard858693c2004-03-31 18:52:07 +00001100 put_packet(s, "OK");
pbrook6658ffb2007-03-16 23:58:11 +00001101#ifndef CONFIG_USER_ONLY
1102 } else if (type == 2) {
1103 if (cpu_watchpoint_insert(env, addr) < 0)
1104 goto breakpoint_error;
1105 put_packet(s, "OK");
1106#endif
bellard858693c2004-03-31 18:52:07 +00001107 } else {
1108 breakpoint_error:
bellard905f20b2005-04-26 21:09:55 +00001109 put_packet(s, "E22");
bellard858693c2004-03-31 18:52:07 +00001110 }
1111 break;
1112 case 'z':
1113 type = strtoul(p, (char **)&p, 16);
1114 if (*p == ',')
1115 p++;
bellard9d9754a2006-06-25 15:32:37 +00001116 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001117 if (*p == ',')
1118 p++;
bellard9d9754a2006-06-25 15:32:37 +00001119 len = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001120 if (type == 0 || type == 1) {
1121 cpu_breakpoint_remove(env, addr);
1122 put_packet(s, "OK");
pbrook6658ffb2007-03-16 23:58:11 +00001123#ifndef CONFIG_USER_ONLY
1124 } else if (type == 2) {
1125 cpu_watchpoint_remove(env, addr);
1126 put_packet(s, "OK");
1127#endif
bellard858693c2004-03-31 18:52:07 +00001128 } else {
1129 goto breakpoint_error;
1130 }
1131 break;
pbrook978efd62006-06-17 18:30:42 +00001132 case 'q':
edgar_igl60897d32008-05-09 08:25:14 +00001133 case 'Q':
1134 /* parse any 'q' packets here */
1135 if (!strcmp(p,"qemu.sstepbits")) {
1136 /* Query Breakpoint bit definitions */
1137 sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1138 SSTEP_ENABLE,
1139 SSTEP_NOIRQ,
1140 SSTEP_NOTIMER);
1141 put_packet(s, buf);
1142 break;
1143 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1144 /* Display or change the sstep_flags */
1145 p += 10;
1146 if (*p != '=') {
1147 /* Display current setting */
1148 sprintf(buf,"0x%x", sstep_flags);
1149 put_packet(s, buf);
1150 break;
1151 }
1152 p++;
1153 type = strtoul(p, (char **)&p, 16);
1154 sstep_flags = type;
1155 put_packet(s, "OK");
1156 break;
1157 }
1158#ifdef CONFIG_LINUX_USER
1159 else if (strncmp(p, "Offsets", 7) == 0) {
pbrook978efd62006-06-17 18:30:42 +00001160 TaskState *ts = env->opaque;
1161
thsfe834d02007-06-03 17:08:32 +00001162 sprintf(buf,
pbrookcd041682007-11-11 14:52:02 +00001163 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1164 ";Bss=" TARGET_ABI_FMT_lx,
thsfe834d02007-06-03 17:08:32 +00001165 ts->info->code_offset,
1166 ts->info->data_offset,
1167 ts->info->data_offset);
pbrook978efd62006-06-17 18:30:42 +00001168 put_packet(s, buf);
1169 break;
1170 }
pbrook978efd62006-06-17 18:30:42 +00001171#endif
edgar_igl60897d32008-05-09 08:25:14 +00001172 /* Fall through. */
bellard858693c2004-03-31 18:52:07 +00001173 default:
bellard858693c2004-03-31 18:52:07 +00001174 /* put empty packet */
1175 buf[0] = '\0';
1176 put_packet(s, buf);
1177 break;
1178 }
1179 return RS_IDLE;
1180}
1181
bellard612458f2005-01-03 23:34:06 +00001182extern void tb_flush(CPUState *env);
1183
bellard1fddef42005-04-17 19:16:13 +00001184#ifndef CONFIG_USER_ONLY
bellard858693c2004-03-31 18:52:07 +00001185static void gdb_vm_stopped(void *opaque, int reason)
1186{
1187 GDBState *s = opaque;
1188 char buf[256];
1189 int ret;
1190
pbrooka2d1eba2007-01-28 03:10:55 +00001191 if (s->state == RS_SYSCALL)
1192 return;
1193
bellard858693c2004-03-31 18:52:07 +00001194 /* disable single step if it was enable */
bellard6a00d602005-11-21 23:25:50 +00001195 cpu_single_step(s->env, 0);
bellard858693c2004-03-31 18:52:07 +00001196
bellarde80cfcf2004-12-19 23:18:01 +00001197 if (reason == EXCP_DEBUG) {
pbrook6658ffb2007-03-16 23:58:11 +00001198 if (s->env->watchpoint_hit) {
pbrookaa6290b2007-04-14 22:35:50 +00001199 snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1200 SIGTRAP,
pbrook6658ffb2007-03-16 23:58:11 +00001201 s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1202 put_packet(s, buf);
1203 s->env->watchpoint_hit = 0;
1204 return;
1205 }
bellard6a00d602005-11-21 23:25:50 +00001206 tb_flush(s->env);
bellard858693c2004-03-31 18:52:07 +00001207 ret = SIGTRAP;
bellardbbeb7b52006-04-23 18:42:15 +00001208 } else if (reason == EXCP_INTERRUPT) {
1209 ret = SIGINT;
1210 } else {
bellard858693c2004-03-31 18:52:07 +00001211 ret = 0;
bellardbbeb7b52006-04-23 18:42:15 +00001212 }
bellard858693c2004-03-31 18:52:07 +00001213 snprintf(buf, sizeof(buf), "S%02x", ret);
1214 put_packet(s, buf);
1215}
bellard1fddef42005-04-17 19:16:13 +00001216#endif
bellard858693c2004-03-31 18:52:07 +00001217
pbrooka2d1eba2007-01-28 03:10:55 +00001218/* Send a gdb syscall request.
1219 This accepts limited printf-style format specifiers, specifically:
pbrooka87295e2007-05-26 15:09:38 +00001220 %x - target_ulong argument printed in hex.
1221 %lx - 64-bit argument printed in hex.
1222 %s - string pointer (target_ulong) and length (int) pair. */
pbrooka2d1eba2007-01-28 03:10:55 +00001223void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1224{
1225 va_list va;
1226 char buf[256];
1227 char *p;
1228 target_ulong addr;
pbrooka87295e2007-05-26 15:09:38 +00001229 uint64_t i64;
pbrooka2d1eba2007-01-28 03:10:55 +00001230 GDBState *s;
1231
1232 s = gdb_syscall_state;
1233 if (!s)
1234 return;
1235 gdb_current_syscall_cb = cb;
1236 s->state = RS_SYSCALL;
1237#ifndef CONFIG_USER_ONLY
1238 vm_stop(EXCP_DEBUG);
1239#endif
1240 s->state = RS_IDLE;
1241 va_start(va, fmt);
1242 p = buf;
1243 *(p++) = 'F';
1244 while (*fmt) {
1245 if (*fmt == '%') {
1246 fmt++;
1247 switch (*fmt++) {
1248 case 'x':
1249 addr = va_arg(va, target_ulong);
1250 p += sprintf(p, TARGET_FMT_lx, addr);
1251 break;
pbrooka87295e2007-05-26 15:09:38 +00001252 case 'l':
1253 if (*(fmt++) != 'x')
1254 goto bad_format;
1255 i64 = va_arg(va, uint64_t);
1256 p += sprintf(p, "%" PRIx64, i64);
1257 break;
pbrooka2d1eba2007-01-28 03:10:55 +00001258 case 's':
1259 addr = va_arg(va, target_ulong);
1260 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1261 break;
1262 default:
pbrooka87295e2007-05-26 15:09:38 +00001263 bad_format:
pbrooka2d1eba2007-01-28 03:10:55 +00001264 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1265 fmt - 1);
1266 break;
1267 }
1268 } else {
1269 *(p++) = *(fmt++);
1270 }
1271 }
pbrook8a93e022007-08-06 13:19:15 +00001272 *p = 0;
pbrooka2d1eba2007-01-28 03:10:55 +00001273 va_end(va);
1274 put_packet(s, buf);
1275#ifdef CONFIG_USER_ONLY
1276 gdb_handlesig(s->env, 0);
1277#else
1278 cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1279#endif
1280}
1281
bellard6a00d602005-11-21 23:25:50 +00001282static void gdb_read_byte(GDBState *s, int ch)
bellard858693c2004-03-31 18:52:07 +00001283{
bellard6a00d602005-11-21 23:25:50 +00001284 CPUState *env = s->env;
bellard858693c2004-03-31 18:52:07 +00001285 int i, csum;
ths60fe76f2007-12-16 03:02:09 +00001286 uint8_t reply;
bellard858693c2004-03-31 18:52:07 +00001287
bellard1fddef42005-04-17 19:16:13 +00001288#ifndef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +00001289 if (s->last_packet_len) {
1290 /* Waiting for a response to the last packet. If we see the start
1291 of a new command then abandon the previous response. */
1292 if (ch == '-') {
1293#ifdef DEBUG_GDB
1294 printf("Got NACK, retransmitting\n");
1295#endif
thsffe8ab82007-12-16 03:16:05 +00001296 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
pbrook4046d912007-01-28 01:53:16 +00001297 }
1298#ifdef DEBUG_GDB
1299 else if (ch == '+')
1300 printf("Got ACK\n");
1301 else
1302 printf("Got '%c' when expecting ACK/NACK\n", ch);
1303#endif
1304 if (ch == '+' || ch == '$')
1305 s->last_packet_len = 0;
1306 if (ch != '$')
1307 return;
1308 }
bellard858693c2004-03-31 18:52:07 +00001309 if (vm_running) {
1310 /* when the CPU is running, we cannot do anything except stop
1311 it when receiving a char */
1312 vm_stop(EXCP_INTERRUPT);
ths5fafdf22007-09-16 21:08:06 +00001313 } else
bellard1fddef42005-04-17 19:16:13 +00001314#endif
bellard41625032005-04-24 10:07:11 +00001315 {
bellard858693c2004-03-31 18:52:07 +00001316 switch(s->state) {
1317 case RS_IDLE:
1318 if (ch == '$') {
1319 s->line_buf_index = 0;
1320 s->state = RS_GETLINE;
bellard4c3a88a2003-07-26 12:06:08 +00001321 }
1322 break;
bellard858693c2004-03-31 18:52:07 +00001323 case RS_GETLINE:
1324 if (ch == '#') {
1325 s->state = RS_CHKSUM1;
1326 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1327 s->state = RS_IDLE;
1328 } else {
1329 s->line_buf[s->line_buf_index++] = ch;
1330 }
1331 break;
1332 case RS_CHKSUM1:
1333 s->line_buf[s->line_buf_index] = '\0';
1334 s->line_csum = fromhex(ch) << 4;
1335 s->state = RS_CHKSUM2;
1336 break;
1337 case RS_CHKSUM2:
1338 s->line_csum |= fromhex(ch);
1339 csum = 0;
1340 for(i = 0; i < s->line_buf_index; i++) {
1341 csum += s->line_buf[i];
1342 }
1343 if (s->line_csum != (csum & 0xff)) {
ths60fe76f2007-12-16 03:02:09 +00001344 reply = '-';
1345 put_buffer(s, &reply, 1);
bellard858693c2004-03-31 18:52:07 +00001346 s->state = RS_IDLE;
1347 } else {
ths60fe76f2007-12-16 03:02:09 +00001348 reply = '+';
1349 put_buffer(s, &reply, 1);
bellard1fddef42005-04-17 19:16:13 +00001350 s->state = gdb_handle_packet(s, env, s->line_buf);
bellard858693c2004-03-31 18:52:07 +00001351 }
bellardb4608c02003-06-27 17:34:32 +00001352 break;
pbrooka2d1eba2007-01-28 03:10:55 +00001353 default:
1354 abort();
bellardb4608c02003-06-27 17:34:32 +00001355 }
1356 }
bellard858693c2004-03-31 18:52:07 +00001357}
1358
bellard1fddef42005-04-17 19:16:13 +00001359#ifdef CONFIG_USER_ONLY
1360int
1361gdb_handlesig (CPUState *env, int sig)
1362{
1363 GDBState *s;
1364 char buf[256];
1365 int n;
1366
1367 if (gdbserver_fd < 0)
1368 return sig;
1369
1370 s = &gdbserver_state;
1371
1372 /* disable single step if it was enabled */
1373 cpu_single_step(env, 0);
1374 tb_flush(env);
1375
1376 if (sig != 0)
1377 {
1378 snprintf(buf, sizeof(buf), "S%02x", sig);
1379 put_packet(s, buf);
1380 }
1381
bellard1fddef42005-04-17 19:16:13 +00001382 sig = 0;
1383 s->state = RS_IDLE;
bellard41625032005-04-24 10:07:11 +00001384 s->running_state = 0;
1385 while (s->running_state == 0) {
bellard1fddef42005-04-17 19:16:13 +00001386 n = read (s->fd, buf, 256);
1387 if (n > 0)
1388 {
1389 int i;
1390
1391 for (i = 0; i < n; i++)
bellard6a00d602005-11-21 23:25:50 +00001392 gdb_read_byte (s, buf[i]);
bellard1fddef42005-04-17 19:16:13 +00001393 }
1394 else if (n == 0 || errno != EAGAIN)
1395 {
1396 /* XXX: Connection closed. Should probably wait for annother
1397 connection before continuing. */
1398 return sig;
1399 }
bellard41625032005-04-24 10:07:11 +00001400 }
bellard1fddef42005-04-17 19:16:13 +00001401 return sig;
1402}
bellarde9009672005-04-26 20:42:36 +00001403
1404/* Tell the remote gdb that the process has exited. */
1405void gdb_exit(CPUState *env, int code)
1406{
1407 GDBState *s;
1408 char buf[4];
1409
1410 if (gdbserver_fd < 0)
1411 return;
1412
1413 s = &gdbserver_state;
1414
1415 snprintf(buf, sizeof(buf), "W%02x", code);
1416 put_packet(s, buf);
1417}
1418
bellard1fddef42005-04-17 19:16:13 +00001419
bellard7c9d8e02005-11-15 22:16:05 +00001420static void gdb_accept(void *opaque)
bellard858693c2004-03-31 18:52:07 +00001421{
1422 GDBState *s;
1423 struct sockaddr_in sockaddr;
1424 socklen_t len;
1425 int val, fd;
1426
1427 for(;;) {
1428 len = sizeof(sockaddr);
1429 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1430 if (fd < 0 && errno != EINTR) {
1431 perror("accept");
1432 return;
1433 } else if (fd >= 0) {
1434 break;
1435 }
1436 }
1437
1438 /* set short latency */
1439 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00001440 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
ths3b46e622007-09-17 08:09:54 +00001441
bellard1fddef42005-04-17 19:16:13 +00001442 s = &gdbserver_state;
1443 memset (s, 0, sizeof (GDBState));
bellard6a00d602005-11-21 23:25:50 +00001444 s->env = first_cpu; /* XXX: allow to change CPU */
bellard858693c2004-03-31 18:52:07 +00001445 s->fd = fd;
1446
pbrooka2d1eba2007-01-28 03:10:55 +00001447 gdb_syscall_state = s;
1448
bellard858693c2004-03-31 18:52:07 +00001449 fcntl(fd, F_SETFL, O_NONBLOCK);
bellard858693c2004-03-31 18:52:07 +00001450}
1451
1452static int gdbserver_open(int port)
1453{
1454 struct sockaddr_in sockaddr;
1455 int fd, val, ret;
1456
1457 fd = socket(PF_INET, SOCK_STREAM, 0);
1458 if (fd < 0) {
1459 perror("socket");
1460 return -1;
1461 }
1462
1463 /* allow fast reuse */
1464 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00001465 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
bellard858693c2004-03-31 18:52:07 +00001466
1467 sockaddr.sin_family = AF_INET;
1468 sockaddr.sin_port = htons(port);
1469 sockaddr.sin_addr.s_addr = 0;
1470 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1471 if (ret < 0) {
1472 perror("bind");
1473 return -1;
1474 }
1475 ret = listen(fd, 0);
1476 if (ret < 0) {
1477 perror("listen");
1478 return -1;
1479 }
bellard858693c2004-03-31 18:52:07 +00001480 return fd;
1481}
1482
1483int gdbserver_start(int port)
1484{
1485 gdbserver_fd = gdbserver_open(port);
1486 if (gdbserver_fd < 0)
1487 return -1;
1488 /* accept connections */
bellard7c9d8e02005-11-15 22:16:05 +00001489 gdb_accept (NULL);
bellardb4608c02003-06-27 17:34:32 +00001490 return 0;
1491}
pbrook4046d912007-01-28 01:53:16 +00001492#else
thsaa1f17c2007-07-11 22:48:58 +00001493static int gdb_chr_can_receive(void *opaque)
pbrook4046d912007-01-28 01:53:16 +00001494{
1495 return 1;
1496}
1497
thsaa1f17c2007-07-11 22:48:58 +00001498static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
pbrook4046d912007-01-28 01:53:16 +00001499{
1500 GDBState *s = opaque;
1501 int i;
1502
1503 for (i = 0; i < size; i++) {
1504 gdb_read_byte(s, buf[i]);
1505 }
1506}
1507
1508static void gdb_chr_event(void *opaque, int event)
1509{
1510 switch (event) {
1511 case CHR_EVENT_RESET:
1512 vm_stop(EXCP_INTERRUPT);
pbrooka2d1eba2007-01-28 03:10:55 +00001513 gdb_syscall_state = opaque;
pbrook4046d912007-01-28 01:53:16 +00001514 break;
1515 default:
1516 break;
1517 }
1518}
1519
pbrookcfc34752007-02-22 01:48:01 +00001520int gdbserver_start(const char *port)
pbrook4046d912007-01-28 01:53:16 +00001521{
1522 GDBState *s;
pbrookcfc34752007-02-22 01:48:01 +00001523 char gdbstub_port_name[128];
1524 int port_num;
1525 char *p;
1526 CharDriverState *chr;
pbrook4046d912007-01-28 01:53:16 +00001527
pbrookcfc34752007-02-22 01:48:01 +00001528 if (!port || !*port)
1529 return -1;
1530
1531 port_num = strtol(port, &p, 10);
1532 if (*p == 0) {
1533 /* A numeric value is interpreted as a port number. */
1534 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1535 "tcp::%d,nowait,nodelay,server", port_num);
1536 port = gdbstub_port_name;
1537 }
1538
1539 chr = qemu_chr_open(port);
pbrook4046d912007-01-28 01:53:16 +00001540 if (!chr)
1541 return -1;
1542
1543 s = qemu_mallocz(sizeof(GDBState));
1544 if (!s) {
1545 return -1;
1546 }
1547 s->env = first_cpu; /* XXX: allow to change CPU */
1548 s->chr = chr;
thsaa1f17c2007-07-11 22:48:58 +00001549 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
pbrook4046d912007-01-28 01:53:16 +00001550 gdb_chr_event, s);
1551 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1552 return 0;
1553}
1554#endif