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bellardb4608c02003-06-27 17:34:32 +00001/*
2 * gdb server stub
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard34751872005-07-02 14:31:34 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellardb4608c02003-06-27 17:34:32 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
pbrook978efd62006-06-17 18:30:42 +000020#include "config.h"
bellard1fddef42005-04-17 19:16:13 +000021#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
pbrook978efd62006-06-17 18:30:42 +000028#include <fcntl.h>
bellard1fddef42005-04-17 19:16:13 +000029
30#include "qemu.h"
31#else
pbrook87ecb682007-11-17 17:14:51 +000032#include "qemu-common.h"
33#include "qemu-char.h"
34#include "sysemu.h"
35#include "gdbstub.h"
bellard1fddef42005-04-17 19:16:13 +000036#endif
bellard67b915a2004-03-31 23:37:16 +000037
bellard8f447cc2006-06-14 15:21:14 +000038#include "qemu_socket.h"
39#ifdef _WIN32
40/* XXX: these constants may be independent of the host ones even for Unix */
41#ifndef SIGTRAP
42#define SIGTRAP 5
43#endif
44#ifndef SIGINT
45#define SIGINT 2
46#endif
47#else
bellardb4608c02003-06-27 17:34:32 +000048#include <signal.h>
bellard8f447cc2006-06-14 15:21:14 +000049#endif
bellardb4608c02003-06-27 17:34:32 +000050
bellard4abe6152003-07-26 18:01:58 +000051//#define DEBUG_GDB
bellardb4608c02003-06-27 17:34:32 +000052
bellard858693c2004-03-31 18:52:07 +000053enum RSState {
54 RS_IDLE,
55 RS_GETLINE,
56 RS_CHKSUM1,
57 RS_CHKSUM2,
pbrooka2d1eba2007-01-28 03:10:55 +000058 RS_SYSCALL,
bellard858693c2004-03-31 18:52:07 +000059};
bellard858693c2004-03-31 18:52:07 +000060typedef struct GDBState {
bellard6a00d602005-11-21 23:25:50 +000061 CPUState *env; /* current CPU */
bellard41625032005-04-24 10:07:11 +000062 enum RSState state; /* parsing state */
bellard858693c2004-03-31 18:52:07 +000063 char line_buf[4096];
64 int line_buf_index;
65 int line_csum;
ths60fe76f2007-12-16 03:02:09 +000066 uint8_t last_packet[4100];
pbrook4046d912007-01-28 01:53:16 +000067 int last_packet_len;
bellard41625032005-04-24 10:07:11 +000068#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +000069 int fd;
bellard41625032005-04-24 10:07:11 +000070 int running_state;
pbrook4046d912007-01-28 01:53:16 +000071#else
72 CharDriverState *chr;
bellard41625032005-04-24 10:07:11 +000073#endif
bellard858693c2004-03-31 18:52:07 +000074} GDBState;
bellardb4608c02003-06-27 17:34:32 +000075
edgar_igl60897d32008-05-09 08:25:14 +000076/* By default use no IRQs and no timers while single stepping so as to
77 * make single stepping like an ICE HW step.
78 */
79static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
80
bellard1fddef42005-04-17 19:16:13 +000081#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +000082/* XXX: This is not thread safe. Do we care? */
83static int gdbserver_fd = -1;
84
bellard1fddef42005-04-17 19:16:13 +000085/* XXX: remove this hack. */
86static GDBState gdbserver_state;
bellard1fddef42005-04-17 19:16:13 +000087
bellard858693c2004-03-31 18:52:07 +000088static int get_char(GDBState *s)
bellardb4608c02003-06-27 17:34:32 +000089{
90 uint8_t ch;
91 int ret;
92
93 for(;;) {
bellard8f447cc2006-06-14 15:21:14 +000094 ret = recv(s->fd, &ch, 1, 0);
bellardb4608c02003-06-27 17:34:32 +000095 if (ret < 0) {
96 if (errno != EINTR && errno != EAGAIN)
97 return -1;
98 } else if (ret == 0) {
99 return -1;
100 } else {
101 break;
102 }
103 }
104 return ch;
105}
pbrook4046d912007-01-28 01:53:16 +0000106#endif
bellardb4608c02003-06-27 17:34:32 +0000107
pbrooka2d1eba2007-01-28 03:10:55 +0000108/* GDB stub state for use by semihosting syscalls. */
109static GDBState *gdb_syscall_state;
110static gdb_syscall_complete_cb gdb_current_syscall_cb;
111
112enum {
113 GDB_SYS_UNKNOWN,
114 GDB_SYS_ENABLED,
115 GDB_SYS_DISABLED,
116} gdb_syscall_mode;
117
118/* If gdb is connected when the first semihosting syscall occurs then use
119 remote gdb syscalls. Otherwise use native file IO. */
120int use_gdb_syscalls(void)
121{
122 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
123 gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
124 : GDB_SYS_DISABLED);
125 }
126 return gdb_syscall_mode == GDB_SYS_ENABLED;
127}
128
edgar_iglba70a622008-03-14 06:10:42 +0000129/* Resume execution. */
130static inline void gdb_continue(GDBState *s)
131{
132#ifdef CONFIG_USER_ONLY
133 s->running_state = 1;
134#else
135 vm_start();
136#endif
137}
138
bellard858693c2004-03-31 18:52:07 +0000139static void put_buffer(GDBState *s, const uint8_t *buf, int len)
bellardb4608c02003-06-27 17:34:32 +0000140{
pbrook4046d912007-01-28 01:53:16 +0000141#ifdef CONFIG_USER_ONLY
bellardb4608c02003-06-27 17:34:32 +0000142 int ret;
143
144 while (len > 0) {
bellard8f447cc2006-06-14 15:21:14 +0000145 ret = send(s->fd, buf, len, 0);
bellardb4608c02003-06-27 17:34:32 +0000146 if (ret < 0) {
147 if (errno != EINTR && errno != EAGAIN)
148 return;
149 } else {
150 buf += ret;
151 len -= ret;
152 }
153 }
pbrook4046d912007-01-28 01:53:16 +0000154#else
155 qemu_chr_write(s->chr, buf, len);
156#endif
bellardb4608c02003-06-27 17:34:32 +0000157}
158
159static inline int fromhex(int v)
160{
161 if (v >= '0' && v <= '9')
162 return v - '0';
163 else if (v >= 'A' && v <= 'F')
164 return v - 'A' + 10;
165 else if (v >= 'a' && v <= 'f')
166 return v - 'a' + 10;
167 else
168 return 0;
169}
170
171static inline int tohex(int v)
172{
173 if (v < 10)
174 return v + '0';
175 else
176 return v - 10 + 'a';
177}
178
179static void memtohex(char *buf, const uint8_t *mem, int len)
180{
181 int i, c;
182 char *q;
183 q = buf;
184 for(i = 0; i < len; i++) {
185 c = mem[i];
186 *q++ = tohex(c >> 4);
187 *q++ = tohex(c & 0xf);
188 }
189 *q = '\0';
190}
191
192static void hextomem(uint8_t *mem, const char *buf, int len)
193{
194 int i;
195
196 for(i = 0; i < len; i++) {
197 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
198 buf += 2;
199 }
200}
201
bellardb4608c02003-06-27 17:34:32 +0000202/* return -1 if error, 0 if OK */
bellard858693c2004-03-31 18:52:07 +0000203static int put_packet(GDBState *s, char *buf)
bellardb4608c02003-06-27 17:34:32 +0000204{
pbrook4046d912007-01-28 01:53:16 +0000205 int len, csum, i;
ths60fe76f2007-12-16 03:02:09 +0000206 uint8_t *p;
bellardb4608c02003-06-27 17:34:32 +0000207
208#ifdef DEBUG_GDB
209 printf("reply='%s'\n", buf);
210#endif
211
212 for(;;) {
pbrook4046d912007-01-28 01:53:16 +0000213 p = s->last_packet;
214 *(p++) = '$';
bellardb4608c02003-06-27 17:34:32 +0000215 len = strlen(buf);
pbrook4046d912007-01-28 01:53:16 +0000216 memcpy(p, buf, len);
217 p += len;
bellardb4608c02003-06-27 17:34:32 +0000218 csum = 0;
219 for(i = 0; i < len; i++) {
220 csum += buf[i];
221 }
pbrook4046d912007-01-28 01:53:16 +0000222 *(p++) = '#';
223 *(p++) = tohex((csum >> 4) & 0xf);
224 *(p++) = tohex((csum) & 0xf);
bellardb4608c02003-06-27 17:34:32 +0000225
pbrook4046d912007-01-28 01:53:16 +0000226 s->last_packet_len = p - s->last_packet;
thsffe8ab82007-12-16 03:16:05 +0000227 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
bellardb4608c02003-06-27 17:34:32 +0000228
pbrook4046d912007-01-28 01:53:16 +0000229#ifdef CONFIG_USER_ONLY
230 i = get_char(s);
231 if (i < 0)
bellardb4608c02003-06-27 17:34:32 +0000232 return -1;
pbrook4046d912007-01-28 01:53:16 +0000233 if (i == '+')
bellardb4608c02003-06-27 17:34:32 +0000234 break;
pbrook4046d912007-01-28 01:53:16 +0000235#else
236 break;
237#endif
bellardb4608c02003-06-27 17:34:32 +0000238 }
239 return 0;
240}
edgar_iglc5841162008-05-09 08:23:19 +0000241#if defined(TARGET_X86_64)
bellardb4608c02003-06-27 17:34:32 +0000242
edgar_iglc5841162008-05-09 08:23:19 +0000243static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
244{
245 uint8_t *p = mem_buf;
246 int i, fpus;
bellard6da41ea2004-01-04 15:48:38 +0000247
edgar_iglc5841162008-05-09 08:23:19 +0000248#define PUTREG(x) do { \
249 target_ulong reg = tswapl(x); \
250 memcpy(p, &reg, sizeof reg); \
251 p += sizeof reg; \
252 } while (0)
253#define PUTREG32(x) do { \
254 uint32_t reg = tswap32(x); \
255 memcpy(p, &reg, sizeof reg); \
256 p += sizeof reg; \
257 } while (0)
258#define PUTREGF(x) do { \
259 memcpy(p, &(x), 10); \
260 p += sizeof (x); \
261 } while (0)
262
263 PUTREG(env->regs[R_EAX]);
264 PUTREG(env->regs[R_EBX]);
265 PUTREG(env->regs[R_ECX]);
266 PUTREG(env->regs[R_EDX]);
267 PUTREG(env->regs[R_ESI]);
268 PUTREG(env->regs[R_EDI]);
269 PUTREG(env->regs[R_EBP]);
270 PUTREG(env->regs[R_ESP]);
271 PUTREG(env->regs[8]);
272 PUTREG(env->regs[9]);
273 PUTREG(env->regs[10]);
274 PUTREG(env->regs[11]);
275 PUTREG(env->regs[12]);
276 PUTREG(env->regs[13]);
277 PUTREG(env->regs[14]);
278 PUTREG(env->regs[15]);
279
280 PUTREG(env->eip);
281 PUTREG32(env->eflags);
282 PUTREG32(env->segs[R_CS].selector);
283 PUTREG32(env->segs[R_SS].selector);
284 PUTREG32(env->segs[R_DS].selector);
285 PUTREG32(env->segs[R_ES].selector);
286 PUTREG32(env->segs[R_FS].selector);
287 PUTREG32(env->segs[R_GS].selector);
288 /* XXX: convert floats */
289 for(i = 0; i < 8; i++) {
290 PUTREGF(env->fpregs[i]);
291 }
292 PUTREG32(env->fpuc);
293 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
294 PUTREG32(fpus);
295 PUTREG32(0); /* XXX: convert tags */
296 PUTREG32(0); /* fiseg */
297 PUTREG32(0); /* fioff */
298 PUTREG32(0); /* foseg */
299 PUTREG32(0); /* fooff */
300 PUTREG32(0); /* fop */
301
302#undef PUTREG
303#undef PUTREG32
304#undef PUTREGF
305
306 return p - mem_buf;
307}
308
309static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
310{
311 uint8_t *p = mem_buf;
312 uint32_t junk;
313 int i, fpus;
314
315#define GETREG(x) do { \
316 target_ulong reg; \
317 memcpy(&reg, p, sizeof reg); \
318 x = tswapl(reg); \
319 p += sizeof reg; \
320 } while (0)
321#define GETREG32(x) do { \
322 uint32_t reg; \
323 memcpy(&reg, p, sizeof reg); \
324 x = tswap32(reg); \
325 p += sizeof reg; \
326 } while (0)
327#define GETREGF(x) do { \
328 memcpy(&(x), p, 10); \
329 p += 10; \
330 } while (0)
331
332 GETREG(env->regs[R_EAX]);
333 GETREG(env->regs[R_EBX]);
334 GETREG(env->regs[R_ECX]);
335 GETREG(env->regs[R_EDX]);
336 GETREG(env->regs[R_ESI]);
337 GETREG(env->regs[R_EDI]);
338 GETREG(env->regs[R_EBP]);
339 GETREG(env->regs[R_ESP]);
340 GETREG(env->regs[8]);
341 GETREG(env->regs[9]);
342 GETREG(env->regs[10]);
343 GETREG(env->regs[11]);
344 GETREG(env->regs[12]);
345 GETREG(env->regs[13]);
346 GETREG(env->regs[14]);
347 GETREG(env->regs[15]);
348
349 GETREG(env->eip);
350 GETREG32(env->eflags);
351 GETREG32(env->segs[R_CS].selector);
352 GETREG32(env->segs[R_SS].selector);
353 GETREG32(env->segs[R_DS].selector);
354 GETREG32(env->segs[R_ES].selector);
355 GETREG32(env->segs[R_FS].selector);
356 GETREG32(env->segs[R_GS].selector);
357 /* XXX: convert floats */
358 for(i = 0; i < 8; i++) {
359 GETREGF(env->fpregs[i]);
360 }
361 GETREG32(env->fpuc);
362 GETREG32(fpus); /* XXX: convert fpus */
363 GETREG32(junk); /* XXX: convert tags */
364 GETREG32(junk); /* fiseg */
365 GETREG32(junk); /* fioff */
366 GETREG32(junk); /* foseg */
367 GETREG32(junk); /* fooff */
368 GETREG32(junk); /* fop */
369
370#undef GETREG
371#undef GETREG32
372#undef GETREGF
373}
374
375#elif defined(TARGET_I386)
bellard6da41ea2004-01-04 15:48:38 +0000376static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
377{
378 int i, fpus;
balrog5ad265e2007-10-31 00:21:35 +0000379 uint32_t *registers = (uint32_t *)mem_buf;
380
381#ifdef TARGET_X86_64
382 /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
383 uint64_t *registers64 = (uint64_t *)mem_buf;
384
385 if (env->hflags & HF_CS64_MASK) {
386 registers64[0] = tswap64(env->regs[R_EAX]);
387 registers64[1] = tswap64(env->regs[R_EBX]);
388 registers64[2] = tswap64(env->regs[R_ECX]);
389 registers64[3] = tswap64(env->regs[R_EDX]);
390 registers64[4] = tswap64(env->regs[R_ESI]);
391 registers64[5] = tswap64(env->regs[R_EDI]);
392 registers64[6] = tswap64(env->regs[R_EBP]);
393 registers64[7] = tswap64(env->regs[R_ESP]);
394 for(i = 8; i < 16; i++) {
395 registers64[i] = tswap64(env->regs[i]);
396 }
397 registers64[16] = tswap64(env->eip);
398
399 registers = (uint32_t *)&registers64[17];
400 registers[0] = tswap32(env->eflags);
401 registers[1] = tswap32(env->segs[R_CS].selector);
402 registers[2] = tswap32(env->segs[R_SS].selector);
403 registers[3] = tswap32(env->segs[R_DS].selector);
404 registers[4] = tswap32(env->segs[R_ES].selector);
405 registers[5] = tswap32(env->segs[R_FS].selector);
406 registers[6] = tswap32(env->segs[R_GS].selector);
407 /* XXX: convert floats */
408 for(i = 0; i < 8; i++) {
409 memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10);
410 }
411 registers[27] = tswap32(env->fpuc); /* fctrl */
412 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
413 registers[28] = tswap32(fpus); /* fstat */
414 registers[29] = 0; /* ftag */
415 registers[30] = 0; /* fiseg */
416 registers[31] = 0; /* fioff */
417 registers[32] = 0; /* foseg */
418 registers[33] = 0; /* fooff */
419 registers[34] = 0; /* fop */
420 for(i = 0; i < 16; i++) {
421 memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], 16);
422 }
423 registers[99] = tswap32(env->mxcsr);
424
425 return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
426 }
427#endif
bellard6da41ea2004-01-04 15:48:38 +0000428
429 for(i = 0; i < 8; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000430 registers[i] = env->regs[i];
bellard6da41ea2004-01-04 15:48:38 +0000431 }
bellarde95c8d52004-09-30 22:22:08 +0000432 registers[8] = env->eip;
433 registers[9] = env->eflags;
434 registers[10] = env->segs[R_CS].selector;
435 registers[11] = env->segs[R_SS].selector;
436 registers[12] = env->segs[R_DS].selector;
437 registers[13] = env->segs[R_ES].selector;
438 registers[14] = env->segs[R_FS].selector;
439 registers[15] = env->segs[R_GS].selector;
bellard6da41ea2004-01-04 15:48:38 +0000440 /* XXX: convert floats */
441 for(i = 0; i < 8; i++) {
442 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
443 }
bellarde95c8d52004-09-30 22:22:08 +0000444 registers[36] = env->fpuc;
bellard6da41ea2004-01-04 15:48:38 +0000445 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
bellarde95c8d52004-09-30 22:22:08 +0000446 registers[37] = fpus;
447 registers[38] = 0; /* XXX: convert tags */
448 registers[39] = 0; /* fiseg */
449 registers[40] = 0; /* fioff */
450 registers[41] = 0; /* foseg */
451 registers[42] = 0; /* fooff */
452 registers[43] = 0; /* fop */
ths3b46e622007-09-17 08:09:54 +0000453
bellarde95c8d52004-09-30 22:22:08 +0000454 for(i = 0; i < 16; i++)
455 tswapls(&registers[i]);
456 for(i = 36; i < 44; i++)
457 tswapls(&registers[i]);
bellard6da41ea2004-01-04 15:48:38 +0000458 return 44 * 4;
459}
460
461static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
462{
463 uint32_t *registers = (uint32_t *)mem_buf;
464 int i;
465
466 for(i = 0; i < 8; i++) {
467 env->regs[i] = tswapl(registers[i]);
468 }
bellarde95c8d52004-09-30 22:22:08 +0000469 env->eip = tswapl(registers[8]);
470 env->eflags = tswapl(registers[9]);
bellard6da41ea2004-01-04 15:48:38 +0000471#if defined(CONFIG_USER_ONLY)
472#define LOAD_SEG(index, sreg)\
473 if (tswapl(registers[index]) != env->segs[sreg].selector)\
474 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
475 LOAD_SEG(10, R_CS);
476 LOAD_SEG(11, R_SS);
477 LOAD_SEG(12, R_DS);
478 LOAD_SEG(13, R_ES);
479 LOAD_SEG(14, R_FS);
480 LOAD_SEG(15, R_GS);
481#endif
482}
483
bellard9e62fd72004-01-05 22:49:06 +0000484#elif defined (TARGET_PPC)
bellard9e62fd72004-01-05 22:49:06 +0000485static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
486{
bellarda541f292004-04-12 20:39:29 +0000487 uint32_t *registers = (uint32_t *)mem_buf, tmp;
bellard9e62fd72004-01-05 22:49:06 +0000488 int i;
489
490 /* fill in gprs */
bellarda541f292004-04-12 20:39:29 +0000491 for(i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000492 registers[i] = tswapl(env->gpr[i]);
bellard9e62fd72004-01-05 22:49:06 +0000493 }
494 /* fill in fprs */
495 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000496 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
497 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
bellard9e62fd72004-01-05 22:49:06 +0000498 }
499 /* nip, msr, ccr, lnk, ctr, xer, mq */
bellarde95c8d52004-09-30 22:22:08 +0000500 registers[96] = tswapl(env->nip);
j_mayer0411a972007-10-25 21:35:50 +0000501 registers[97] = tswapl(env->msr);
bellard9e62fd72004-01-05 22:49:06 +0000502 tmp = 0;
503 for (i = 0; i < 8; i++)
bellarda541f292004-04-12 20:39:29 +0000504 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
bellarde95c8d52004-09-30 22:22:08 +0000505 registers[98] = tswapl(tmp);
506 registers[99] = tswapl(env->lr);
507 registers[100] = tswapl(env->ctr);
j_mayer76a66252007-03-07 08:32:30 +0000508 registers[101] = tswapl(ppc_load_xer(env));
bellarde95c8d52004-09-30 22:22:08 +0000509 registers[102] = 0;
bellard9e62fd72004-01-05 22:49:06 +0000510
bellarda541f292004-04-12 20:39:29 +0000511 return 103 * 4;
bellard9e62fd72004-01-05 22:49:06 +0000512}
513
514static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
515{
516 uint32_t *registers = (uint32_t *)mem_buf;
517 int i;
518
519 /* fill in gprs */
520 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000521 env->gpr[i] = tswapl(registers[i]);
bellard9e62fd72004-01-05 22:49:06 +0000522 }
523 /* fill in fprs */
524 for (i = 0; i < 32; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000525 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
526 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
bellard9e62fd72004-01-05 22:49:06 +0000527 }
528 /* nip, msr, ccr, lnk, ctr, xer, mq */
bellarde95c8d52004-09-30 22:22:08 +0000529 env->nip = tswapl(registers[96]);
j_mayer0411a972007-10-25 21:35:50 +0000530 ppc_store_msr(env, tswapl(registers[97]));
bellarde95c8d52004-09-30 22:22:08 +0000531 registers[98] = tswapl(registers[98]);
bellard9e62fd72004-01-05 22:49:06 +0000532 for (i = 0; i < 8; i++)
bellarda541f292004-04-12 20:39:29 +0000533 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
bellarde95c8d52004-09-30 22:22:08 +0000534 env->lr = tswapl(registers[99]);
535 env->ctr = tswapl(registers[100]);
j_mayer76a66252007-03-07 08:32:30 +0000536 ppc_store_xer(env, tswapl(registers[101]));
bellarde95c8d52004-09-30 22:22:08 +0000537}
538#elif defined (TARGET_SPARC)
539static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
540{
bellard34751872005-07-02 14:31:34 +0000541 target_ulong *registers = (target_ulong *)mem_buf;
bellarde95c8d52004-09-30 22:22:08 +0000542 int i;
543
544 /* fill in g0..g7 */
bellard48b2c192005-10-30 16:08:23 +0000545 for(i = 0; i < 8; i++) {
bellarde95c8d52004-09-30 22:22:08 +0000546 registers[i] = tswapl(env->gregs[i]);
547 }
548 /* fill in register window */
549 for(i = 0; i < 24; i++) {
550 registers[i + 8] = tswapl(env->regwptr[i]);
551 }
bellard9d9754a2006-06-25 15:32:37 +0000552#ifndef TARGET_SPARC64
bellarde95c8d52004-09-30 22:22:08 +0000553 /* fill in fprs */
554 for (i = 0; i < 32; i++) {
555 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
556 }
557 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
558 registers[64] = tswapl(env->y);
bellard34751872005-07-02 14:31:34 +0000559 {
560 target_ulong tmp;
561
562 tmp = GET_PSR(env);
563 registers[65] = tswapl(tmp);
564 }
bellarde95c8d52004-09-30 22:22:08 +0000565 registers[66] = tswapl(env->wim);
566 registers[67] = tswapl(env->tbr);
567 registers[68] = tswapl(env->pc);
568 registers[69] = tswapl(env->npc);
569 registers[70] = tswapl(env->fsr);
570 registers[71] = 0; /* csr */
571 registers[72] = 0;
bellard34751872005-07-02 14:31:34 +0000572 return 73 * sizeof(target_ulong);
573#else
bellard9d9754a2006-06-25 15:32:37 +0000574 /* fill in fprs */
575 for (i = 0; i < 64; i += 2) {
576 uint64_t tmp;
577
blueswir189795962007-04-14 16:15:48 +0000578 tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
579 tmp |= *(uint32_t *)&env->fpr[i + 1];
580 registers[i / 2 + 32] = tswap64(tmp);
bellard34751872005-07-02 14:31:34 +0000581 }
bellard9d9754a2006-06-25 15:32:37 +0000582 registers[64] = tswapl(env->pc);
583 registers[65] = tswapl(env->npc);
blueswir117d996e2007-07-07 20:53:22 +0000584 registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
585 ((env->asi & 0xff) << 24) |
586 ((env->pstate & 0xfff) << 8) |
587 GET_CWP64(env));
bellard9d9754a2006-06-25 15:32:37 +0000588 registers[67] = tswapl(env->fsr);
589 registers[68] = tswapl(env->fprs);
590 registers[69] = tswapl(env->y);
591 return 70 * sizeof(target_ulong);
bellard34751872005-07-02 14:31:34 +0000592#endif
bellarde95c8d52004-09-30 22:22:08 +0000593}
594
595static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
596{
bellard34751872005-07-02 14:31:34 +0000597 target_ulong *registers = (target_ulong *)mem_buf;
bellarde95c8d52004-09-30 22:22:08 +0000598 int i;
599
600 /* fill in g0..g7 */
601 for(i = 0; i < 7; i++) {
602 env->gregs[i] = tswapl(registers[i]);
603 }
604 /* fill in register window */
605 for(i = 0; i < 24; i++) {
bellard34751872005-07-02 14:31:34 +0000606 env->regwptr[i] = tswapl(registers[i + 8]);
bellarde95c8d52004-09-30 22:22:08 +0000607 }
bellard9d9754a2006-06-25 15:32:37 +0000608#ifndef TARGET_SPARC64
bellarde95c8d52004-09-30 22:22:08 +0000609 /* fill in fprs */
610 for (i = 0; i < 32; i++) {
611 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
612 }
613 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
614 env->y = tswapl(registers[64]);
bellarde80cfcf2004-12-19 23:18:01 +0000615 PUT_PSR(env, tswapl(registers[65]));
bellarde95c8d52004-09-30 22:22:08 +0000616 env->wim = tswapl(registers[66]);
617 env->tbr = tswapl(registers[67]);
618 env->pc = tswapl(registers[68]);
619 env->npc = tswapl(registers[69]);
620 env->fsr = tswapl(registers[70]);
bellard34751872005-07-02 14:31:34 +0000621#else
bellard9d9754a2006-06-25 15:32:37 +0000622 for (i = 0; i < 64; i += 2) {
blueswir189795962007-04-14 16:15:48 +0000623 uint64_t tmp;
624
625 tmp = tswap64(registers[i / 2 + 32]);
626 *((uint32_t *)&env->fpr[i]) = tmp >> 32;
627 *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
bellard34751872005-07-02 14:31:34 +0000628 }
bellard9d9754a2006-06-25 15:32:37 +0000629 env->pc = tswapl(registers[64]);
630 env->npc = tswapl(registers[65]);
blueswir117d996e2007-07-07 20:53:22 +0000631 {
632 uint64_t tmp = tswapl(registers[66]);
633
634 PUT_CCR(env, tmp >> 32);
635 env->asi = (tmp >> 24) & 0xff;
636 env->pstate = (tmp >> 8) & 0xfff;
637 PUT_CWP64(env, tmp & 0xff);
638 }
bellard9d9754a2006-06-25 15:32:37 +0000639 env->fsr = tswapl(registers[67]);
640 env->fprs = tswapl(registers[68]);
641 env->y = tswapl(registers[69]);
bellard34751872005-07-02 14:31:34 +0000642#endif
bellard9e62fd72004-01-05 22:49:06 +0000643}
bellard1fddef42005-04-17 19:16:13 +0000644#elif defined (TARGET_ARM)
645static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
646{
647 int i;
648 uint8_t *ptr;
bellard6da41ea2004-01-04 15:48:38 +0000649
bellard1fddef42005-04-17 19:16:13 +0000650 ptr = mem_buf;
651 /* 16 core integer registers (4 bytes each). */
652 for (i = 0; i < 16; i++)
653 {
654 *(uint32_t *)ptr = tswapl(env->regs[i]);
655 ptr += 4;
656 }
657 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
658 Not yet implemented. */
659 memset (ptr, 0, 8 * 12 + 4);
660 ptr += 8 * 12 + 4;
661 /* CPSR (4 bytes). */
bellardb5ff1b32005-11-26 10:38:39 +0000662 *(uint32_t *)ptr = tswapl (cpsr_read(env));
bellard1fddef42005-04-17 19:16:13 +0000663 ptr += 4;
664
665 return ptr - mem_buf;
666}
667
668static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
669{
670 int i;
671 uint8_t *ptr;
672
673 ptr = mem_buf;
674 /* Core integer registers. */
675 for (i = 0; i < 16; i++)
676 {
677 env->regs[i] = tswapl(*(uint32_t *)ptr);
678 ptr += 4;
679 }
680 /* Ignore FPA regs and scr. */
681 ptr += 8 * 12 + 4;
bellardb5ff1b32005-11-26 10:38:39 +0000682 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
bellard1fddef42005-04-17 19:16:13 +0000683}
pbrooke6e59062006-10-22 00:18:54 +0000684#elif defined (TARGET_M68K)
685static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
686{
687 int i;
688 uint8_t *ptr;
689 CPU_DoubleU u;
690
691 ptr = mem_buf;
692 /* D0-D7 */
693 for (i = 0; i < 8; i++) {
694 *(uint32_t *)ptr = tswapl(env->dregs[i]);
695 ptr += 4;
696 }
697 /* A0-A7 */
698 for (i = 0; i < 8; i++) {
699 *(uint32_t *)ptr = tswapl(env->aregs[i]);
700 ptr += 4;
701 }
702 *(uint32_t *)ptr = tswapl(env->sr);
703 ptr += 4;
704 *(uint32_t *)ptr = tswapl(env->pc);
705 ptr += 4;
706 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
707 ColdFire has 8-bit double precision registers. */
708 for (i = 0; i < 8; i++) {
709 u.d = env->fregs[i];
710 *(uint32_t *)ptr = tswap32(u.l.upper);
711 *(uint32_t *)ptr = tswap32(u.l.lower);
712 }
713 /* FP control regs (not implemented). */
714 memset (ptr, 0, 3 * 4);
715 ptr += 3 * 4;
716
717 return ptr - mem_buf;
718}
719
720static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
721{
722 int i;
723 uint8_t *ptr;
724 CPU_DoubleU u;
725
726 ptr = mem_buf;
727 /* D0-D7 */
728 for (i = 0; i < 8; i++) {
729 env->dregs[i] = tswapl(*(uint32_t *)ptr);
730 ptr += 4;
731 }
732 /* A0-A7 */
733 for (i = 0; i < 8; i++) {
734 env->aregs[i] = tswapl(*(uint32_t *)ptr);
735 ptr += 4;
736 }
737 env->sr = tswapl(*(uint32_t *)ptr);
738 ptr += 4;
739 env->pc = tswapl(*(uint32_t *)ptr);
740 ptr += 4;
741 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
742 ColdFire has 8-bit double precision registers. */
743 for (i = 0; i < 8; i++) {
ths5fafdf22007-09-16 21:08:06 +0000744 u.l.upper = tswap32(*(uint32_t *)ptr);
pbrooke6e59062006-10-22 00:18:54 +0000745 u.l.lower = tswap32(*(uint32_t *)ptr);
746 env->fregs[i] = u.d;
747 }
748 /* FP control regs (not implemented). */
749 ptr += 3 * 4;
750}
bellard6f970bd2005-12-05 19:55:19 +0000751#elif defined (TARGET_MIPS)
752static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
753{
754 int i;
755 uint8_t *ptr;
756
757 ptr = mem_buf;
758 for (i = 0; i < 32; i++)
759 {
thsd0dc7dc2008-02-12 21:01:26 +0000760 *(target_ulong *)ptr = tswapl(env->gpr[env->current_tc][i]);
ths2052caa2007-06-01 13:18:19 +0000761 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000762 }
763
ths7ac256b2007-10-25 21:30:37 +0000764 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
ths2052caa2007-06-01 13:18:19 +0000765 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000766
thsd0dc7dc2008-02-12 21:01:26 +0000767 *(target_ulong *)ptr = tswapl(env->LO[env->current_tc][0]);
ths2052caa2007-06-01 13:18:19 +0000768 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000769
thsd0dc7dc2008-02-12 21:01:26 +0000770 *(target_ulong *)ptr = tswapl(env->HI[env->current_tc][0]);
ths2052caa2007-06-01 13:18:19 +0000771 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000772
ths2052caa2007-06-01 13:18:19 +0000773 *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
774 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000775
ths7ac256b2007-10-25 21:30:37 +0000776 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
ths2052caa2007-06-01 13:18:19 +0000777 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000778
thsead93602007-09-06 00:18:15 +0000779 *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
ths2052caa2007-06-01 13:18:19 +0000780 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000781
ths36d23952007-02-28 22:37:42 +0000782 if (env->CP0_Config1 & (1 << CP0C1_FP))
ths8e33c082006-12-11 19:22:27 +0000783 {
ths36d23952007-02-28 22:37:42 +0000784 for (i = 0; i < 32; i++)
785 {
ths7ac256b2007-10-25 21:30:37 +0000786 if (env->CP0_Status & (1 << CP0St_FR))
787 *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
788 else
789 *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
ths2052caa2007-06-01 13:18:19 +0000790 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000791 }
792
ths7ac256b2007-10-25 21:30:37 +0000793 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
ths2052caa2007-06-01 13:18:19 +0000794 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000795
ths7ac256b2007-10-25 21:30:37 +0000796 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
ths2052caa2007-06-01 13:18:19 +0000797 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000798 }
799
ths7ac256b2007-10-25 21:30:37 +0000800 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
801 *(target_ulong *)ptr = 0;
802 ptr += sizeof(target_ulong);
803
804 /* Registers for embedded use, we just pad them. */
805 for (i = 0; i < 16; i++)
806 {
807 *(target_ulong *)ptr = 0;
808 ptr += sizeof(target_ulong);
809 }
810
811 /* Processor ID. */
812 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
813 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000814
815 return ptr - mem_buf;
816}
817
ths8e33c082006-12-11 19:22:27 +0000818/* convert MIPS rounding mode in FCR31 to IEEE library */
819static unsigned int ieee_rm[] =
820 {
821 float_round_nearest_even,
822 float_round_to_zero,
823 float_round_up,
824 float_round_down
825 };
826#define RESTORE_ROUNDING_MODE \
thsead93602007-09-06 00:18:15 +0000827 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
ths8e33c082006-12-11 19:22:27 +0000828
bellard6f970bd2005-12-05 19:55:19 +0000829static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
830{
831 int i;
832 uint8_t *ptr;
833
834 ptr = mem_buf;
835 for (i = 0; i < 32; i++)
836 {
thsd0dc7dc2008-02-12 21:01:26 +0000837 env->gpr[env->current_tc][i] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000838 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000839 }
840
ths2052caa2007-06-01 13:18:19 +0000841 env->CP0_Status = tswapl(*(target_ulong *)ptr);
842 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000843
thsd0dc7dc2008-02-12 21:01:26 +0000844 env->LO[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000845 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000846
thsd0dc7dc2008-02-12 21:01:26 +0000847 env->HI[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000848 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000849
ths2052caa2007-06-01 13:18:19 +0000850 env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
851 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000852
ths2052caa2007-06-01 13:18:19 +0000853 env->CP0_Cause = tswapl(*(target_ulong *)ptr);
854 ptr += sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +0000855
thsead93602007-09-06 00:18:15 +0000856 env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000857 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000858
ths36d23952007-02-28 22:37:42 +0000859 if (env->CP0_Config1 & (1 << CP0C1_FP))
ths8e33c082006-12-11 19:22:27 +0000860 {
ths36d23952007-02-28 22:37:42 +0000861 for (i = 0; i < 32; i++)
862 {
ths7ac256b2007-10-25 21:30:37 +0000863 if (env->CP0_Status & (1 << CP0St_FR))
864 env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
865 else
866 env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
ths2052caa2007-06-01 13:18:19 +0000867 ptr += sizeof(target_ulong);
ths36d23952007-02-28 22:37:42 +0000868 }
869
ths7ac256b2007-10-25 21:30:37 +0000870 env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
ths2052caa2007-06-01 13:18:19 +0000871 ptr += sizeof(target_ulong);
ths8e33c082006-12-11 19:22:27 +0000872
ths7ac256b2007-10-25 21:30:37 +0000873 /* The remaining registers are assumed to be read-only. */
ths8e33c082006-12-11 19:22:27 +0000874
ths36d23952007-02-28 22:37:42 +0000875 /* set rounding mode */
876 RESTORE_ROUNDING_MODE;
ths8e33c082006-12-11 19:22:27 +0000877
878#ifndef CONFIG_SOFTFLOAT
ths36d23952007-02-28 22:37:42 +0000879 /* no floating point exception for native float */
880 SET_FP_ENABLE(env->fcr31, 0);
ths8e33c082006-12-11 19:22:27 +0000881#endif
ths36d23952007-02-28 22:37:42 +0000882 }
bellard6f970bd2005-12-05 19:55:19 +0000883}
bellardfdf9b3e2006-04-27 21:07:38 +0000884#elif defined (TARGET_SH4)
ths6ef99fc2007-05-13 16:36:24 +0000885
886/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
887
bellardfdf9b3e2006-04-27 21:07:38 +0000888static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
889{
890 uint32_t *ptr = (uint32_t *)mem_buf;
891 int i;
892
893#define SAVE(x) *ptr++=tswapl(x)
pbrook9c2a9ea2006-06-18 19:12:54 +0000894 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
895 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
896 } else {
897 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
898 }
899 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
bellardfdf9b3e2006-04-27 21:07:38 +0000900 SAVE (env->pc);
901 SAVE (env->pr);
902 SAVE (env->gbr);
903 SAVE (env->vbr);
904 SAVE (env->mach);
905 SAVE (env->macl);
906 SAVE (env->sr);
ths6ef99fc2007-05-13 16:36:24 +0000907 SAVE (env->fpul);
908 SAVE (env->fpscr);
909 for (i = 0; i < 16; i++)
910 SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
911 SAVE (env->ssr);
912 SAVE (env->spc);
913 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
914 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
bellardfdf9b3e2006-04-27 21:07:38 +0000915 return ((uint8_t *)ptr - mem_buf);
916}
917
918static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
919{
920 uint32_t *ptr = (uint32_t *)mem_buf;
921 int i;
922
923#define LOAD(x) (x)=*ptr++;
pbrook9c2a9ea2006-06-18 19:12:54 +0000924 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
925 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
926 } else {
927 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
928 }
929 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
bellardfdf9b3e2006-04-27 21:07:38 +0000930 LOAD (env->pc);
931 LOAD (env->pr);
932 LOAD (env->gbr);
933 LOAD (env->vbr);
934 LOAD (env->mach);
935 LOAD (env->macl);
936 LOAD (env->sr);
ths6ef99fc2007-05-13 16:36:24 +0000937 LOAD (env->fpul);
938 LOAD (env->fpscr);
939 for (i = 0; i < 16; i++)
940 LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
941 LOAD (env->ssr);
942 LOAD (env->spc);
943 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
944 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
bellardfdf9b3e2006-04-27 21:07:38 +0000945}
thsf1ccf902007-10-08 13:16:14 +0000946#elif defined (TARGET_CRIS)
947
948static int cris_save_32 (unsigned char *d, uint32_t value)
949{
950 *d++ = (value);
951 *d++ = (value >>= 8);
952 *d++ = (value >>= 8);
953 *d++ = (value >>= 8);
954 return 4;
955}
956static int cris_save_16 (unsigned char *d, uint32_t value)
957{
958 *d++ = (value);
959 *d++ = (value >>= 8);
960 return 2;
961}
962static int cris_save_8 (unsigned char *d, uint32_t value)
963{
964 *d++ = (value);
965 return 1;
966}
967
968/* FIXME: this will bug on archs not supporting unaligned word accesses. */
969static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
970{
971 uint8_t *ptr = mem_buf;
972 uint8_t srs;
973 int i;
974
975 for (i = 0; i < 16; i++)
976 ptr += cris_save_32 (ptr, env->regs[i]);
977
edgar_igl90046272008-02-28 08:28:32 +0000978 srs = env->pregs[PR_SRS];
thsf1ccf902007-10-08 13:16:14 +0000979
980 ptr += cris_save_8 (ptr, env->pregs[0]);
981 ptr += cris_save_8 (ptr, env->pregs[1]);
982 ptr += cris_save_32 (ptr, env->pregs[2]);
983 ptr += cris_save_8 (ptr, srs);
984 ptr += cris_save_16 (ptr, env->pregs[4]);
985
986 for (i = 5; i < 16; i++)
987 ptr += cris_save_32 (ptr, env->pregs[i]);
988
989 ptr += cris_save_32 (ptr, env->pc);
990
991 for (i = 0; i < 16; i++)
992 ptr += cris_save_32 (ptr, env->sregs[srs][i]);
993
994 return ((uint8_t *)ptr - mem_buf);
995}
996
997static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
998{
999 uint32_t *ptr = (uint32_t *)mem_buf;
1000 int i;
1001
1002#define LOAD(x) (x)=*ptr++;
1003 for (i = 0; i < 16; i++) LOAD(env->regs[i]);
1004 LOAD (env->pc);
1005}
bellard1fddef42005-04-17 19:16:13 +00001006#else
bellard6da41ea2004-01-04 15:48:38 +00001007static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
1008{
1009 return 0;
1010}
1011
1012static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
1013{
1014}
1015
1016#endif
bellardb4608c02003-06-27 17:34:32 +00001017
bellard1fddef42005-04-17 19:16:13 +00001018static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
bellardb4608c02003-06-27 17:34:32 +00001019{
bellardb4608c02003-06-27 17:34:32 +00001020 const char *p;
bellard858693c2004-03-31 18:52:07 +00001021 int ch, reg_size, type;
bellardb4608c02003-06-27 17:34:32 +00001022 char buf[4096];
thsf1ccf902007-10-08 13:16:14 +00001023 uint8_t mem_buf[4096];
bellardb4608c02003-06-27 17:34:32 +00001024 uint32_t *registers;
bellard9d9754a2006-06-25 15:32:37 +00001025 target_ulong addr, len;
ths3b46e622007-09-17 08:09:54 +00001026
bellard858693c2004-03-31 18:52:07 +00001027#ifdef DEBUG_GDB
1028 printf("command='%s'\n", line_buf);
bellard4c3a88a2003-07-26 12:06:08 +00001029#endif
bellard858693c2004-03-31 18:52:07 +00001030 p = line_buf;
1031 ch = *p++;
1032 switch(ch) {
1033 case '?':
bellard1fddef42005-04-17 19:16:13 +00001034 /* TODO: Make this return the correct value for user-mode. */
bellard858693c2004-03-31 18:52:07 +00001035 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
1036 put_packet(s, buf);
1037 break;
1038 case 'c':
1039 if (*p != '\0') {
bellard9d9754a2006-06-25 15:32:37 +00001040 addr = strtoull(p, (char **)&p, 16);
bellardc33a3462003-07-29 20:50:33 +00001041#if defined(TARGET_I386)
bellard858693c2004-03-31 18:52:07 +00001042 env->eip = addr;
bellard5be1a8e2004-01-04 23:51:58 +00001043#elif defined (TARGET_PPC)
bellard858693c2004-03-31 18:52:07 +00001044 env->nip = addr;
bellard8d5f07f2004-10-04 21:23:09 +00001045#elif defined (TARGET_SPARC)
1046 env->pc = addr;
1047 env->npc = addr + 4;
bellardb5ff1b32005-11-26 10:38:39 +00001048#elif defined (TARGET_ARM)
1049 env->regs[15] = addr;
bellardfdf9b3e2006-04-27 21:07:38 +00001050#elif defined (TARGET_SH4)
ths8fac5802007-07-12 10:05:07 +00001051 env->pc = addr;
1052#elif defined (TARGET_MIPS)
thsead93602007-09-06 00:18:15 +00001053 env->PC[env->current_tc] = addr;
thsf1ccf902007-10-08 13:16:14 +00001054#elif defined (TARGET_CRIS)
1055 env->pc = addr;
bellardc33a3462003-07-29 20:50:33 +00001056#endif
bellard858693c2004-03-31 18:52:07 +00001057 }
edgar_iglba70a622008-03-14 06:10:42 +00001058 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +00001059 return RS_IDLE;
bellard858693c2004-03-31 18:52:07 +00001060 case 's':
1061 if (*p != '\0') {
ths8fac5802007-07-12 10:05:07 +00001062 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001063#if defined(TARGET_I386)
1064 env->eip = addr;
1065#elif defined (TARGET_PPC)
1066 env->nip = addr;
bellard8d5f07f2004-10-04 21:23:09 +00001067#elif defined (TARGET_SPARC)
1068 env->pc = addr;
1069 env->npc = addr + 4;
bellardb5ff1b32005-11-26 10:38:39 +00001070#elif defined (TARGET_ARM)
1071 env->regs[15] = addr;
bellardfdf9b3e2006-04-27 21:07:38 +00001072#elif defined (TARGET_SH4)
ths8fac5802007-07-12 10:05:07 +00001073 env->pc = addr;
1074#elif defined (TARGET_MIPS)
thsead93602007-09-06 00:18:15 +00001075 env->PC[env->current_tc] = addr;
thsf1ccf902007-10-08 13:16:14 +00001076#elif defined (TARGET_CRIS)
1077 env->pc = addr;
bellard858693c2004-03-31 18:52:07 +00001078#endif
1079 }
edgar_igl60897d32008-05-09 08:25:14 +00001080 cpu_single_step(env, sstep_flags);
edgar_iglba70a622008-03-14 06:10:42 +00001081 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +00001082 return RS_IDLE;
pbrooka2d1eba2007-01-28 03:10:55 +00001083 case 'F':
1084 {
1085 target_ulong ret;
1086 target_ulong err;
1087
1088 ret = strtoull(p, (char **)&p, 16);
1089 if (*p == ',') {
1090 p++;
1091 err = strtoull(p, (char **)&p, 16);
1092 } else {
1093 err = 0;
1094 }
1095 if (*p == ',')
1096 p++;
1097 type = *p;
1098 if (gdb_current_syscall_cb)
1099 gdb_current_syscall_cb(s->env, ret, err);
1100 if (type == 'C') {
1101 put_packet(s, "T02");
1102 } else {
edgar_iglba70a622008-03-14 06:10:42 +00001103 gdb_continue(s);
pbrooka2d1eba2007-01-28 03:10:55 +00001104 }
1105 }
1106 break;
bellard858693c2004-03-31 18:52:07 +00001107 case 'g':
1108 reg_size = cpu_gdb_read_registers(env, mem_buf);
1109 memtohex(buf, mem_buf, reg_size);
1110 put_packet(s, buf);
1111 break;
1112 case 'G':
1113 registers = (void *)mem_buf;
1114 len = strlen(p) / 2;
1115 hextomem((uint8_t *)registers, p, len);
1116 cpu_gdb_write_registers(env, mem_buf, len);
1117 put_packet(s, "OK");
1118 break;
1119 case 'm':
bellard9d9754a2006-06-25 15:32:37 +00001120 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001121 if (*p == ',')
1122 p++;
bellard9d9754a2006-06-25 15:32:37 +00001123 len = strtoull(p, NULL, 16);
bellard6f970bd2005-12-05 19:55:19 +00001124 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
1125 put_packet (s, "E14");
1126 } else {
1127 memtohex(buf, mem_buf, len);
1128 put_packet(s, buf);
1129 }
bellard858693c2004-03-31 18:52:07 +00001130 break;
1131 case 'M':
bellard9d9754a2006-06-25 15:32:37 +00001132 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001133 if (*p == ',')
1134 p++;
bellard9d9754a2006-06-25 15:32:37 +00001135 len = strtoull(p, (char **)&p, 16);
bellardb328f872005-01-17 22:03:16 +00001136 if (*p == ':')
bellard858693c2004-03-31 18:52:07 +00001137 p++;
1138 hextomem(mem_buf, p, len);
1139 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
bellard905f20b2005-04-26 21:09:55 +00001140 put_packet(s, "E14");
bellard858693c2004-03-31 18:52:07 +00001141 else
1142 put_packet(s, "OK");
1143 break;
1144 case 'Z':
1145 type = strtoul(p, (char **)&p, 16);
1146 if (*p == ',')
1147 p++;
bellard9d9754a2006-06-25 15:32:37 +00001148 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001149 if (*p == ',')
1150 p++;
bellard9d9754a2006-06-25 15:32:37 +00001151 len = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001152 if (type == 0 || type == 1) {
1153 if (cpu_breakpoint_insert(env, addr) < 0)
bellard4c3a88a2003-07-26 12:06:08 +00001154 goto breakpoint_error;
bellard858693c2004-03-31 18:52:07 +00001155 put_packet(s, "OK");
pbrook6658ffb2007-03-16 23:58:11 +00001156#ifndef CONFIG_USER_ONLY
1157 } else if (type == 2) {
1158 if (cpu_watchpoint_insert(env, addr) < 0)
1159 goto breakpoint_error;
1160 put_packet(s, "OK");
1161#endif
bellard858693c2004-03-31 18:52:07 +00001162 } else {
1163 breakpoint_error:
bellard905f20b2005-04-26 21:09:55 +00001164 put_packet(s, "E22");
bellard858693c2004-03-31 18:52:07 +00001165 }
1166 break;
1167 case 'z':
1168 type = strtoul(p, (char **)&p, 16);
1169 if (*p == ',')
1170 p++;
bellard9d9754a2006-06-25 15:32:37 +00001171 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001172 if (*p == ',')
1173 p++;
bellard9d9754a2006-06-25 15:32:37 +00001174 len = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00001175 if (type == 0 || type == 1) {
1176 cpu_breakpoint_remove(env, addr);
1177 put_packet(s, "OK");
pbrook6658ffb2007-03-16 23:58:11 +00001178#ifndef CONFIG_USER_ONLY
1179 } else if (type == 2) {
1180 cpu_watchpoint_remove(env, addr);
1181 put_packet(s, "OK");
1182#endif
bellard858693c2004-03-31 18:52:07 +00001183 } else {
1184 goto breakpoint_error;
1185 }
1186 break;
pbrook978efd62006-06-17 18:30:42 +00001187 case 'q':
edgar_igl60897d32008-05-09 08:25:14 +00001188 case 'Q':
1189 /* parse any 'q' packets here */
1190 if (!strcmp(p,"qemu.sstepbits")) {
1191 /* Query Breakpoint bit definitions */
1192 sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1193 SSTEP_ENABLE,
1194 SSTEP_NOIRQ,
1195 SSTEP_NOTIMER);
1196 put_packet(s, buf);
1197 break;
1198 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1199 /* Display or change the sstep_flags */
1200 p += 10;
1201 if (*p != '=') {
1202 /* Display current setting */
1203 sprintf(buf,"0x%x", sstep_flags);
1204 put_packet(s, buf);
1205 break;
1206 }
1207 p++;
1208 type = strtoul(p, (char **)&p, 16);
1209 sstep_flags = type;
1210 put_packet(s, "OK");
1211 break;
1212 }
1213#ifdef CONFIG_LINUX_USER
1214 else if (strncmp(p, "Offsets", 7) == 0) {
pbrook978efd62006-06-17 18:30:42 +00001215 TaskState *ts = env->opaque;
1216
thsfe834d02007-06-03 17:08:32 +00001217 sprintf(buf,
pbrookcd041682007-11-11 14:52:02 +00001218 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1219 ";Bss=" TARGET_ABI_FMT_lx,
thsfe834d02007-06-03 17:08:32 +00001220 ts->info->code_offset,
1221 ts->info->data_offset,
1222 ts->info->data_offset);
pbrook978efd62006-06-17 18:30:42 +00001223 put_packet(s, buf);
1224 break;
1225 }
pbrook978efd62006-06-17 18:30:42 +00001226#endif
edgar_igl60897d32008-05-09 08:25:14 +00001227 /* Fall through. */
bellard858693c2004-03-31 18:52:07 +00001228 default:
bellard858693c2004-03-31 18:52:07 +00001229 /* put empty packet */
1230 buf[0] = '\0';
1231 put_packet(s, buf);
1232 break;
1233 }
1234 return RS_IDLE;
1235}
1236
bellard612458f2005-01-03 23:34:06 +00001237extern void tb_flush(CPUState *env);
1238
bellard1fddef42005-04-17 19:16:13 +00001239#ifndef CONFIG_USER_ONLY
bellard858693c2004-03-31 18:52:07 +00001240static void gdb_vm_stopped(void *opaque, int reason)
1241{
1242 GDBState *s = opaque;
1243 char buf[256];
1244 int ret;
1245
pbrooka2d1eba2007-01-28 03:10:55 +00001246 if (s->state == RS_SYSCALL)
1247 return;
1248
bellard858693c2004-03-31 18:52:07 +00001249 /* disable single step if it was enable */
bellard6a00d602005-11-21 23:25:50 +00001250 cpu_single_step(s->env, 0);
bellard858693c2004-03-31 18:52:07 +00001251
bellarde80cfcf2004-12-19 23:18:01 +00001252 if (reason == EXCP_DEBUG) {
pbrook6658ffb2007-03-16 23:58:11 +00001253 if (s->env->watchpoint_hit) {
pbrookaa6290b2007-04-14 22:35:50 +00001254 snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1255 SIGTRAP,
pbrook6658ffb2007-03-16 23:58:11 +00001256 s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1257 put_packet(s, buf);
1258 s->env->watchpoint_hit = 0;
1259 return;
1260 }
bellard6a00d602005-11-21 23:25:50 +00001261 tb_flush(s->env);
bellard858693c2004-03-31 18:52:07 +00001262 ret = SIGTRAP;
bellardbbeb7b52006-04-23 18:42:15 +00001263 } else if (reason == EXCP_INTERRUPT) {
1264 ret = SIGINT;
1265 } else {
bellard858693c2004-03-31 18:52:07 +00001266 ret = 0;
bellardbbeb7b52006-04-23 18:42:15 +00001267 }
bellard858693c2004-03-31 18:52:07 +00001268 snprintf(buf, sizeof(buf), "S%02x", ret);
1269 put_packet(s, buf);
1270}
bellard1fddef42005-04-17 19:16:13 +00001271#endif
bellard858693c2004-03-31 18:52:07 +00001272
pbrooka2d1eba2007-01-28 03:10:55 +00001273/* Send a gdb syscall request.
1274 This accepts limited printf-style format specifiers, specifically:
pbrooka87295e2007-05-26 15:09:38 +00001275 %x - target_ulong argument printed in hex.
1276 %lx - 64-bit argument printed in hex.
1277 %s - string pointer (target_ulong) and length (int) pair. */
pbrooka2d1eba2007-01-28 03:10:55 +00001278void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1279{
1280 va_list va;
1281 char buf[256];
1282 char *p;
1283 target_ulong addr;
pbrooka87295e2007-05-26 15:09:38 +00001284 uint64_t i64;
pbrooka2d1eba2007-01-28 03:10:55 +00001285 GDBState *s;
1286
1287 s = gdb_syscall_state;
1288 if (!s)
1289 return;
1290 gdb_current_syscall_cb = cb;
1291 s->state = RS_SYSCALL;
1292#ifndef CONFIG_USER_ONLY
1293 vm_stop(EXCP_DEBUG);
1294#endif
1295 s->state = RS_IDLE;
1296 va_start(va, fmt);
1297 p = buf;
1298 *(p++) = 'F';
1299 while (*fmt) {
1300 if (*fmt == '%') {
1301 fmt++;
1302 switch (*fmt++) {
1303 case 'x':
1304 addr = va_arg(va, target_ulong);
1305 p += sprintf(p, TARGET_FMT_lx, addr);
1306 break;
pbrooka87295e2007-05-26 15:09:38 +00001307 case 'l':
1308 if (*(fmt++) != 'x')
1309 goto bad_format;
1310 i64 = va_arg(va, uint64_t);
1311 p += sprintf(p, "%" PRIx64, i64);
1312 break;
pbrooka2d1eba2007-01-28 03:10:55 +00001313 case 's':
1314 addr = va_arg(va, target_ulong);
1315 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1316 break;
1317 default:
pbrooka87295e2007-05-26 15:09:38 +00001318 bad_format:
pbrooka2d1eba2007-01-28 03:10:55 +00001319 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1320 fmt - 1);
1321 break;
1322 }
1323 } else {
1324 *(p++) = *(fmt++);
1325 }
1326 }
pbrook8a93e022007-08-06 13:19:15 +00001327 *p = 0;
pbrooka2d1eba2007-01-28 03:10:55 +00001328 va_end(va);
1329 put_packet(s, buf);
1330#ifdef CONFIG_USER_ONLY
1331 gdb_handlesig(s->env, 0);
1332#else
1333 cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1334#endif
1335}
1336
bellard6a00d602005-11-21 23:25:50 +00001337static void gdb_read_byte(GDBState *s, int ch)
bellard858693c2004-03-31 18:52:07 +00001338{
bellard6a00d602005-11-21 23:25:50 +00001339 CPUState *env = s->env;
bellard858693c2004-03-31 18:52:07 +00001340 int i, csum;
ths60fe76f2007-12-16 03:02:09 +00001341 uint8_t reply;
bellard858693c2004-03-31 18:52:07 +00001342
bellard1fddef42005-04-17 19:16:13 +00001343#ifndef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +00001344 if (s->last_packet_len) {
1345 /* Waiting for a response to the last packet. If we see the start
1346 of a new command then abandon the previous response. */
1347 if (ch == '-') {
1348#ifdef DEBUG_GDB
1349 printf("Got NACK, retransmitting\n");
1350#endif
thsffe8ab82007-12-16 03:16:05 +00001351 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
pbrook4046d912007-01-28 01:53:16 +00001352 }
1353#ifdef DEBUG_GDB
1354 else if (ch == '+')
1355 printf("Got ACK\n");
1356 else
1357 printf("Got '%c' when expecting ACK/NACK\n", ch);
1358#endif
1359 if (ch == '+' || ch == '$')
1360 s->last_packet_len = 0;
1361 if (ch != '$')
1362 return;
1363 }
bellard858693c2004-03-31 18:52:07 +00001364 if (vm_running) {
1365 /* when the CPU is running, we cannot do anything except stop
1366 it when receiving a char */
1367 vm_stop(EXCP_INTERRUPT);
ths5fafdf22007-09-16 21:08:06 +00001368 } else
bellard1fddef42005-04-17 19:16:13 +00001369#endif
bellard41625032005-04-24 10:07:11 +00001370 {
bellard858693c2004-03-31 18:52:07 +00001371 switch(s->state) {
1372 case RS_IDLE:
1373 if (ch == '$') {
1374 s->line_buf_index = 0;
1375 s->state = RS_GETLINE;
bellard4c3a88a2003-07-26 12:06:08 +00001376 }
1377 break;
bellard858693c2004-03-31 18:52:07 +00001378 case RS_GETLINE:
1379 if (ch == '#') {
1380 s->state = RS_CHKSUM1;
1381 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1382 s->state = RS_IDLE;
1383 } else {
1384 s->line_buf[s->line_buf_index++] = ch;
1385 }
1386 break;
1387 case RS_CHKSUM1:
1388 s->line_buf[s->line_buf_index] = '\0';
1389 s->line_csum = fromhex(ch) << 4;
1390 s->state = RS_CHKSUM2;
1391 break;
1392 case RS_CHKSUM2:
1393 s->line_csum |= fromhex(ch);
1394 csum = 0;
1395 for(i = 0; i < s->line_buf_index; i++) {
1396 csum += s->line_buf[i];
1397 }
1398 if (s->line_csum != (csum & 0xff)) {
ths60fe76f2007-12-16 03:02:09 +00001399 reply = '-';
1400 put_buffer(s, &reply, 1);
bellard858693c2004-03-31 18:52:07 +00001401 s->state = RS_IDLE;
1402 } else {
ths60fe76f2007-12-16 03:02:09 +00001403 reply = '+';
1404 put_buffer(s, &reply, 1);
bellard1fddef42005-04-17 19:16:13 +00001405 s->state = gdb_handle_packet(s, env, s->line_buf);
bellard858693c2004-03-31 18:52:07 +00001406 }
bellardb4608c02003-06-27 17:34:32 +00001407 break;
pbrooka2d1eba2007-01-28 03:10:55 +00001408 default:
1409 abort();
bellardb4608c02003-06-27 17:34:32 +00001410 }
1411 }
bellard858693c2004-03-31 18:52:07 +00001412}
1413
bellard1fddef42005-04-17 19:16:13 +00001414#ifdef CONFIG_USER_ONLY
1415int
1416gdb_handlesig (CPUState *env, int sig)
1417{
1418 GDBState *s;
1419 char buf[256];
1420 int n;
1421
1422 if (gdbserver_fd < 0)
1423 return sig;
1424
1425 s = &gdbserver_state;
1426
1427 /* disable single step if it was enabled */
1428 cpu_single_step(env, 0);
1429 tb_flush(env);
1430
1431 if (sig != 0)
1432 {
1433 snprintf(buf, sizeof(buf), "S%02x", sig);
1434 put_packet(s, buf);
1435 }
1436
bellard1fddef42005-04-17 19:16:13 +00001437 sig = 0;
1438 s->state = RS_IDLE;
bellard41625032005-04-24 10:07:11 +00001439 s->running_state = 0;
1440 while (s->running_state == 0) {
bellard1fddef42005-04-17 19:16:13 +00001441 n = read (s->fd, buf, 256);
1442 if (n > 0)
1443 {
1444 int i;
1445
1446 for (i = 0; i < n; i++)
bellard6a00d602005-11-21 23:25:50 +00001447 gdb_read_byte (s, buf[i]);
bellard1fddef42005-04-17 19:16:13 +00001448 }
1449 else if (n == 0 || errno != EAGAIN)
1450 {
1451 /* XXX: Connection closed. Should probably wait for annother
1452 connection before continuing. */
1453 return sig;
1454 }
bellard41625032005-04-24 10:07:11 +00001455 }
bellard1fddef42005-04-17 19:16:13 +00001456 return sig;
1457}
bellarde9009672005-04-26 20:42:36 +00001458
1459/* Tell the remote gdb that the process has exited. */
1460void gdb_exit(CPUState *env, int code)
1461{
1462 GDBState *s;
1463 char buf[4];
1464
1465 if (gdbserver_fd < 0)
1466 return;
1467
1468 s = &gdbserver_state;
1469
1470 snprintf(buf, sizeof(buf), "W%02x", code);
1471 put_packet(s, buf);
1472}
1473
bellard1fddef42005-04-17 19:16:13 +00001474
bellard7c9d8e02005-11-15 22:16:05 +00001475static void gdb_accept(void *opaque)
bellard858693c2004-03-31 18:52:07 +00001476{
1477 GDBState *s;
1478 struct sockaddr_in sockaddr;
1479 socklen_t len;
1480 int val, fd;
1481
1482 for(;;) {
1483 len = sizeof(sockaddr);
1484 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1485 if (fd < 0 && errno != EINTR) {
1486 perror("accept");
1487 return;
1488 } else if (fd >= 0) {
1489 break;
1490 }
1491 }
1492
1493 /* set short latency */
1494 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00001495 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
ths3b46e622007-09-17 08:09:54 +00001496
bellard1fddef42005-04-17 19:16:13 +00001497 s = &gdbserver_state;
1498 memset (s, 0, sizeof (GDBState));
bellard6a00d602005-11-21 23:25:50 +00001499 s->env = first_cpu; /* XXX: allow to change CPU */
bellard858693c2004-03-31 18:52:07 +00001500 s->fd = fd;
1501
pbrooka2d1eba2007-01-28 03:10:55 +00001502 gdb_syscall_state = s;
1503
bellard858693c2004-03-31 18:52:07 +00001504 fcntl(fd, F_SETFL, O_NONBLOCK);
bellard858693c2004-03-31 18:52:07 +00001505}
1506
1507static int gdbserver_open(int port)
1508{
1509 struct sockaddr_in sockaddr;
1510 int fd, val, ret;
1511
1512 fd = socket(PF_INET, SOCK_STREAM, 0);
1513 if (fd < 0) {
1514 perror("socket");
1515 return -1;
1516 }
1517
1518 /* allow fast reuse */
1519 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00001520 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
bellard858693c2004-03-31 18:52:07 +00001521
1522 sockaddr.sin_family = AF_INET;
1523 sockaddr.sin_port = htons(port);
1524 sockaddr.sin_addr.s_addr = 0;
1525 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1526 if (ret < 0) {
1527 perror("bind");
1528 return -1;
1529 }
1530 ret = listen(fd, 0);
1531 if (ret < 0) {
1532 perror("listen");
1533 return -1;
1534 }
bellard858693c2004-03-31 18:52:07 +00001535 return fd;
1536}
1537
1538int gdbserver_start(int port)
1539{
1540 gdbserver_fd = gdbserver_open(port);
1541 if (gdbserver_fd < 0)
1542 return -1;
1543 /* accept connections */
bellard7c9d8e02005-11-15 22:16:05 +00001544 gdb_accept (NULL);
bellardb4608c02003-06-27 17:34:32 +00001545 return 0;
1546}
pbrook4046d912007-01-28 01:53:16 +00001547#else
thsaa1f17c2007-07-11 22:48:58 +00001548static int gdb_chr_can_receive(void *opaque)
pbrook4046d912007-01-28 01:53:16 +00001549{
1550 return 1;
1551}
1552
thsaa1f17c2007-07-11 22:48:58 +00001553static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
pbrook4046d912007-01-28 01:53:16 +00001554{
1555 GDBState *s = opaque;
1556 int i;
1557
1558 for (i = 0; i < size; i++) {
1559 gdb_read_byte(s, buf[i]);
1560 }
1561}
1562
1563static void gdb_chr_event(void *opaque, int event)
1564{
1565 switch (event) {
1566 case CHR_EVENT_RESET:
1567 vm_stop(EXCP_INTERRUPT);
pbrooka2d1eba2007-01-28 03:10:55 +00001568 gdb_syscall_state = opaque;
pbrook4046d912007-01-28 01:53:16 +00001569 break;
1570 default:
1571 break;
1572 }
1573}
1574
pbrookcfc34752007-02-22 01:48:01 +00001575int gdbserver_start(const char *port)
pbrook4046d912007-01-28 01:53:16 +00001576{
1577 GDBState *s;
pbrookcfc34752007-02-22 01:48:01 +00001578 char gdbstub_port_name[128];
1579 int port_num;
1580 char *p;
1581 CharDriverState *chr;
pbrook4046d912007-01-28 01:53:16 +00001582
pbrookcfc34752007-02-22 01:48:01 +00001583 if (!port || !*port)
1584 return -1;
1585
1586 port_num = strtol(port, &p, 10);
1587 if (*p == 0) {
1588 /* A numeric value is interpreted as a port number. */
1589 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1590 "tcp::%d,nowait,nodelay,server", port_num);
1591 port = gdbstub_port_name;
1592 }
1593
1594 chr = qemu_chr_open(port);
pbrook4046d912007-01-28 01:53:16 +00001595 if (!chr)
1596 return -1;
1597
1598 s = qemu_mallocz(sizeof(GDBState));
1599 if (!s) {
1600 return -1;
1601 }
1602 s->env = first_cpu; /* XXX: allow to change CPU */
1603 s->chr = chr;
thsaa1f17c2007-07-11 22:48:58 +00001604 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
pbrook4046d912007-01-28 01:53:16 +00001605 gdb_chr_event, s);
1606 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1607 return 0;
1608}
1609#endif