David Hendricks | d1c55d7 | 2010-08-24 15:14:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 21 | #include <stdlib.h> |
| 22 | #include <string.h> |
| 23 | |
| 24 | #include "flash.h" |
| 25 | #include "flashchips.h" |
| 26 | #include "chipdrivers.h" |
Louis Yung-Chieh Lo | 52aa930 | 2010-09-06 10:45:02 +0800 | [diff] [blame] | 27 | #include "spi.h" |
David Hendricks | 23cd778 | 2010-08-25 12:42:38 -0700 | [diff] [blame] | 28 | #include "writeprotect.h" |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 29 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 30 | /* |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 31 | * The following procedures rely on look-up tables to match the user-specified |
| 32 | * range with the chip's supported ranges. This turned out to be the most |
| 33 | * elegant approach since diferent flash chips use different levels of |
| 34 | * granularity and methods to determine protected ranges. In other words, |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 35 | * be stupid and simple since clever arithmetic will not work for many chips. |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 36 | */ |
| 37 | |
| 38 | struct wp_range { |
| 39 | unsigned int start; /* starting address */ |
| 40 | unsigned int len; /* len */ |
| 41 | }; |
| 42 | |
| 43 | enum bit_state { |
| 44 | OFF = 0, |
| 45 | ON = 1, |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 46 | X = -1 /* don't care. Must be bigger than max # of bp. */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 49 | /* |
| 50 | * Generic write-protection schema for 25-series SPI flash chips. This assumes |
| 51 | * there is a status register that contains one or more consecutive bits which |
| 52 | * determine which address range is protected. |
| 53 | */ |
| 54 | |
| 55 | struct status_register_layout { |
| 56 | int bp0_pos; /* position of BP0 */ |
| 57 | int bp_bits; /* number of block protect bits */ |
| 58 | int srp_pos; /* position of status register protect enable bit */ |
| 59 | }; |
| 60 | |
| 61 | struct generic_range { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 62 | struct generic_modifier_bits m; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 63 | unsigned int bp; /* block protect bitfield */ |
| 64 | struct wp_range range; |
| 65 | }; |
| 66 | |
| 67 | struct generic_wp { |
| 68 | struct status_register_layout sr1; /* status register 1 */ |
| 69 | struct generic_range *ranges; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * Some chips store modifier bits in one or more special control |
| 73 | * registers instead of the status register like many older SPI NOR |
| 74 | * flash chips did. get_modifier_bits() and set_modifier_bits() will do |
| 75 | * any chip-specific operations necessary to get/set these bit values. |
| 76 | */ |
| 77 | int (*get_modifier_bits)(const struct flashchip *flash, |
| 78 | struct generic_modifier_bits *m); |
| 79 | int (*set_modifier_bits)(const struct flashchip *flash, |
| 80 | struct generic_modifier_bits *m); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | /* |
| 84 | * The following ranges and functions are useful for representing Winbond- |
| 85 | * style writeprotect schema in which there are typically 5 bits of |
| 86 | * relevant information stored in status register 1: |
| 87 | * sec: This bit indicates the units (sectors vs. blocks) |
| 88 | * tb: The top-bottom bit indicates if the affected range is at the top of |
| 89 | * the flash memory's address space or at the bottom. |
| 90 | * bp[2:0]: The number of affected sectors/blocks. |
| 91 | */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 92 | struct w25q_range { |
| 93 | enum bit_state sec; /* if 1, bp[2:0] describe sectors */ |
| 94 | enum bit_state tb; /* top/bottom select */ |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 95 | int bp; /* block protect bitfield */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 96 | struct wp_range range; |
| 97 | }; |
| 98 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 99 | /* |
| 100 | * Mask to extract write-protect enable and range bits |
| 101 | * Status register 1: |
| 102 | * SRP0: bit 7 |
| 103 | * range(BP2-BP0): bit 4-2 |
| 104 | * Status register 2: |
| 105 | * SRP1: bit 1 |
| 106 | */ |
| 107 | #define MASK_WP_AREA (0x9C) |
| 108 | #define MASK_WP2_AREA (0x01) |
| 109 | |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 110 | struct w25q_range en25f40_ranges[] = { |
| 111 | { X, X, 0, {0, 0} }, /* none */ |
| 112 | { 0, 0, 0x1, {0x000000, 504 * 1024} }, |
| 113 | { 0, 0, 0x2, {0x000000, 496 * 1024} }, |
| 114 | { 0, 0, 0x3, {0x000000, 480 * 1024} }, |
| 115 | { 0, 0, 0x4, {0x000000, 448 * 1024} }, |
| 116 | { 0, 0, 0x5, {0x000000, 384 * 1024} }, |
| 117 | { 0, 0, 0x6, {0x000000, 256 * 1024} }, |
| 118 | { 0, 0, 0x7, {0x000000, 512 * 1024} }, |
| 119 | }; |
| 120 | |
David Hendricks | e185bf2 | 2011-05-24 15:34:18 -0700 | [diff] [blame] | 121 | struct w25q_range en25q40_ranges[] = { |
| 122 | { 0, 0, 0, {0, 0} }, /* none */ |
| 123 | { 0, 0, 0x1, {0x000000, 504 * 1024} }, |
| 124 | { 0, 0, 0x2, {0x000000, 496 * 1024} }, |
| 125 | { 0, 0, 0x3, {0x000000, 480 * 1024} }, |
| 126 | |
| 127 | { 0, 1, 0x0, {0x000000, 448 * 1024} }, |
| 128 | { 0, 1, 0x1, {0x000000, 384 * 1024} }, |
| 129 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 130 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 131 | }; |
| 132 | |
| 133 | struct w25q_range en25q80_ranges[] = { |
| 134 | { 0, 0, 0, {0, 0} }, /* none */ |
| 135 | { 0, 0, 0x1, {0x000000, 1016 * 1024} }, |
| 136 | { 0, 0, 0x2, {0x000000, 1008 * 1024} }, |
| 137 | { 0, 0, 0x3, {0x000000, 992 * 1024} }, |
| 138 | { 0, 0, 0x4, {0x000000, 960 * 1024} }, |
| 139 | { 0, 0, 0x5, {0x000000, 896 * 1024} }, |
| 140 | { 0, 0, 0x6, {0x000000, 768 * 1024} }, |
| 141 | { 0, 0, 0x7, {0x000000, 1024 * 1024} }, |
| 142 | }; |
| 143 | |
| 144 | struct w25q_range en25q32_ranges[] = { |
| 145 | { 0, 0, 0, {0, 0} }, /* none */ |
| 146 | { 0, 0, 0x1, {0x000000, 4032 * 1024} }, |
| 147 | { 0, 0, 0x2, {0x000000, 3968 * 1024} }, |
| 148 | { 0, 0, 0x3, {0x000000, 3840 * 1024} }, |
| 149 | { 0, 0, 0x4, {0x000000, 3584 * 1024} }, |
| 150 | { 0, 0, 0x5, {0x000000, 3072 * 1024} }, |
| 151 | { 0, 0, 0x6, {0x000000, 2048 * 1024} }, |
| 152 | { 0, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 153 | |
| 154 | { 0, 1, 0, {0, 0} }, /* none */ |
| 155 | { 0, 1, 0x1, {0x010000, 4032 * 1024} }, |
| 156 | { 0, 1, 0x2, {0x020000, 3968 * 1024} }, |
| 157 | { 0, 1, 0x3, {0x040000, 3840 * 1024} }, |
| 158 | { 0, 1, 0x4, {0x080000, 3584 * 1024} }, |
| 159 | { 0, 1, 0x5, {0x100000, 3072 * 1024} }, |
| 160 | { 0, 1, 0x6, {0x200000, 2048 * 1024} }, |
| 161 | { 0, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 162 | }; |
| 163 | |
| 164 | struct w25q_range en25q64_ranges[] = { |
| 165 | { 0, 0, 0, {0, 0} }, /* none */ |
| 166 | { 0, 0, 0x1, {0x000000, 8128 * 1024} }, |
| 167 | { 0, 0, 0x2, {0x000000, 8064 * 1024} }, |
| 168 | { 0, 0, 0x3, {0x000000, 7936 * 1024} }, |
| 169 | { 0, 0, 0x4, {0x000000, 7680 * 1024} }, |
| 170 | { 0, 0, 0x5, {0x000000, 7168 * 1024} }, |
| 171 | { 0, 0, 0x6, {0x000000, 6144 * 1024} }, |
| 172 | { 0, 0, 0x7, {0x000000, 8192 * 1024} }, |
| 173 | |
| 174 | { 0, 1, 0, {0, 0} }, /* none */ |
| 175 | { 0, 1, 0x1, {0x010000, 8128 * 1024} }, |
| 176 | { 0, 1, 0x2, {0x020000, 8064 * 1024} }, |
| 177 | { 0, 1, 0x3, {0x040000, 7936 * 1024} }, |
| 178 | { 0, 1, 0x4, {0x080000, 7680 * 1024} }, |
| 179 | { 0, 1, 0x5, {0x100000, 7168 * 1024} }, |
| 180 | { 0, 1, 0x6, {0x200000, 6144 * 1024} }, |
| 181 | { 0, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 182 | }; |
| 183 | |
| 184 | struct w25q_range en25q128_ranges[] = { |
| 185 | { 0, 0, 0, {0, 0} }, /* none */ |
| 186 | { 0, 0, 0x1, {0x000000, 16320 * 1024} }, |
| 187 | { 0, 0, 0x2, {0x000000, 16256 * 1024} }, |
| 188 | { 0, 0, 0x3, {0x000000, 16128 * 1024} }, |
| 189 | { 0, 0, 0x4, {0x000000, 15872 * 1024} }, |
| 190 | { 0, 0, 0x5, {0x000000, 15360 * 1024} }, |
| 191 | { 0, 0, 0x6, {0x000000, 14336 * 1024} }, |
| 192 | { 0, 0, 0x7, {0x000000, 16384 * 1024} }, |
| 193 | |
| 194 | { 0, 1, 0, {0, 0} }, /* none */ |
| 195 | { 0, 1, 0x1, {0x010000, 16320 * 1024} }, |
| 196 | { 0, 1, 0x2, {0x020000, 16256 * 1024} }, |
| 197 | { 0, 1, 0x3, {0x040000, 16128 * 1024} }, |
| 198 | { 0, 1, 0x4, {0x080000, 15872 * 1024} }, |
| 199 | { 0, 1, 0x5, {0x100000, 15360 * 1024} }, |
| 200 | { 0, 1, 0x6, {0x200000, 14336 * 1024} }, |
| 201 | { 0, 1, 0x7, {0x000000, 16384 * 1024} }, |
| 202 | }; |
| 203 | |
Marc Jones | b2f9002 | 2014-04-29 17:37:23 -0600 | [diff] [blame] | 204 | struct w25q_range en25s64_ranges[] = { |
| 205 | { 0, 0, 0, {0, 0} }, /* none */ |
| 206 | { 0, 0, 0x1, {0x000000, 8064 * 1024} }, |
| 207 | { 0, 0, 0x2, {0x000000, 7936 * 1024} }, |
| 208 | { 0, 0, 0x3, {0x000000, 7680 * 1024} }, |
| 209 | { 0, 0, 0x4, {0x000000, 7168 * 1024} }, |
| 210 | { 0, 0, 0x5, {0x000000, 6144 * 1024} }, |
| 211 | { 0, 0, 0x6, {0x000000, 4096 * 1024} }, |
| 212 | { 0, 0, 0x7, {0x000000, 8192 * 1024} }, |
| 213 | |
| 214 | { 0, 1, 0, {0, 0} }, /* none */ |
| 215 | { 0, 1, 0x1, {0x7e0000, 128 * 1024} }, |
| 216 | { 0, 1, 0x2, {0x7c0000, 256 * 1024} }, |
| 217 | { 0, 1, 0x3, {0x780000, 512 * 1024} }, |
| 218 | { 0, 1, 0x4, {0x700000, 1024 * 1024} }, |
| 219 | { 0, 1, 0x5, {0x600000, 2048 * 1024} }, |
| 220 | { 0, 1, 0x6, {0x400000, 4096 * 1024} }, |
| 221 | { 0, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 222 | }; |
| 223 | |
David Hendricks | f8f00c7 | 2011-02-01 12:39:46 -0800 | [diff] [blame] | 224 | /* mx25l1005 ranges also work for the mx25l1005c */ |
| 225 | static struct w25q_range mx25l1005_ranges[] = { |
| 226 | { X, X, 0, {0, 0} }, /* none */ |
| 227 | { X, X, 0x1, {0x010000, 64 * 1024} }, |
| 228 | { X, X, 0x2, {0x000000, 128 * 1024} }, |
| 229 | { X, X, 0x3, {0x000000, 128 * 1024} }, |
| 230 | }; |
| 231 | |
| 232 | static struct w25q_range mx25l2005_ranges[] = { |
| 233 | { X, X, 0, {0, 0} }, /* none */ |
| 234 | { X, X, 0x1, {0x030000, 64 * 1024} }, |
| 235 | { X, X, 0x2, {0x020000, 128 * 1024} }, |
| 236 | { X, X, 0x3, {0x000000, 256 * 1024} }, |
| 237 | }; |
| 238 | |
| 239 | static struct w25q_range mx25l4005_ranges[] = { |
| 240 | { X, X, 0, {0, 0} }, /* none */ |
| 241 | { X, X, 0x1, {0x070000, 64 * 1 * 1024} }, /* block 7 */ |
| 242 | { X, X, 0x2, {0x060000, 64 * 2 * 1024} }, /* blocks 6-7 */ |
| 243 | { X, X, 0x3, {0x040000, 64 * 4 * 1024} }, /* blocks 4-7 */ |
| 244 | { X, X, 0x4, {0x000000, 512 * 1024} }, |
| 245 | { X, X, 0x5, {0x000000, 512 * 1024} }, |
| 246 | { X, X, 0x6, {0x000000, 512 * 1024} }, |
| 247 | { X, X, 0x7, {0x000000, 512 * 1024} }, |
| 248 | }; |
| 249 | |
| 250 | static struct w25q_range mx25l8005_ranges[] = { |
| 251 | { X, X, 0, {0, 0} }, /* none */ |
| 252 | { X, X, 0x1, {0x0f0000, 64 * 1 * 1024} }, /* block 15 */ |
| 253 | { X, X, 0x2, {0x0e0000, 64 * 2 * 1024} }, /* blocks 14-15 */ |
| 254 | { X, X, 0x3, {0x0c0000, 64 * 4 * 1024} }, /* blocks 12-15 */ |
| 255 | { X, X, 0x4, {0x080000, 64 * 8 * 1024} }, /* blocks 8-15 */ |
| 256 | { X, X, 0x5, {0x000000, 1024 * 1024} }, |
| 257 | { X, X, 0x6, {0x000000, 1024 * 1024} }, |
| 258 | { X, X, 0x7, {0x000000, 1024 * 1024} }, |
| 259 | }; |
| 260 | |
| 261 | #if 0 |
| 262 | /* FIXME: mx25l1605 has the same IDs as the mx25l1605d */ |
| 263 | static struct w25q_range mx25l1605_ranges[] = { |
| 264 | { X, X, 0, {0, 0} }, /* none */ |
| 265 | { X, X, 0x1, {0x1f0000, 64 * 1024} }, /* block 31 */ |
| 266 | { X, X, 0x2, {0x1e0000, 128 * 1024} }, /* blocks 30-31 */ |
| 267 | { X, X, 0x3, {0x1c0000, 256 * 1024} }, /* blocks 28-31 */ |
| 268 | { X, X, 0x4, {0x180000, 512 * 1024} }, /* blocks 24-31 */ |
| 269 | { X, X, 0x4, {0x100000, 1024 * 1024} }, /* blocks 16-31 */ |
| 270 | { X, X, 0x6, {0x000000, 2048 * 1024} }, |
| 271 | { X, X, 0x7, {0x000000, 2048 * 1024} }, |
| 272 | }; |
| 273 | #endif |
| 274 | |
| 275 | #if 0 |
| 276 | /* FIXME: mx25l6405 has the same IDs as the mx25l6405d */ |
| 277 | static struct w25q_range mx25l6405_ranges[] = { |
| 278 | { X, 0, 0, {0, 0} }, /* none */ |
| 279 | { X, 0, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */ |
| 280 | { X, 0, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 281 | { X, 0, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
| 282 | { X, 0, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 283 | { X, 0, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 284 | { X, 0, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 285 | { X, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 286 | |
| 287 | { X, 1, 0x0, {0x000000, 8192 * 1024} }, |
| 288 | { X, 1, 0x1, {0x000000, 8192 * 1024} }, |
| 289 | { X, 1, 0x2, {0x000000, 8192 * 1024} }, |
| 290 | { X, 1, 0x3, {0x000000, 8192 * 1024} }, |
| 291 | { X, 1, 0x4, {0x000000, 8192 * 1024} }, |
| 292 | { X, 1, 0x5, {0x000000, 8192 * 1024} }, |
| 293 | { X, 1, 0x6, {0x000000, 8192 * 1024} }, |
| 294 | { X, 1, 0x7, {0x000000, 8192 * 1024} }, |
| 295 | }; |
| 296 | #endif |
| 297 | |
| 298 | static struct w25q_range mx25l1605d_ranges[] = { |
| 299 | { X, 0, 0, {0, 0} }, /* none */ |
| 300 | { X, 0, 0x1, {0x1f0000, 64 * 1 * 1024} }, /* block 31 */ |
| 301 | { X, 0, 0x2, {0x1e0000, 64 * 2 * 1024} }, /* blocks 30-31 */ |
| 302 | { X, 0, 0x3, {0x1c0000, 64 * 4 * 1024} }, /* blocks 28-31 */ |
| 303 | { X, 0, 0x4, {0x180000, 64 * 8 * 1024} }, /* blocks 24-31 */ |
| 304 | { X, 0, 0x5, {0x100000, 64 * 16 * 1024} }, /* blocks 16-31 */ |
| 305 | { X, 0, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 306 | { X, 0, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 307 | |
| 308 | { X, 1, 0x0, {0x000000, 2048 * 1024} }, |
| 309 | { X, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 310 | { X, 1, 0x2, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */ |
| 311 | { X, 1, 0x3, {0x000000, 64 * 24 * 1024} }, /* blocks 0-23 */ |
| 312 | { X, 1, 0x4, {0x000000, 64 * 28 * 1024} }, /* blocks 0-27 */ |
| 313 | { X, 1, 0x5, {0x000000, 64 * 30 * 1024} }, /* blocks 0-29 */ |
| 314 | { X, 1, 0x6, {0x000000, 64 * 31 * 1024} }, /* blocks 0-30 */ |
| 315 | { X, 1, 0x7, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 316 | }; |
| 317 | |
| 318 | /* FIXME: Is there an mx25l3205 (without a trailing letter)? */ |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 319 | static struct w25q_range mx25l3205d_ranges[] = { |
| 320 | { X, 0, 0, {0, 0} }, /* none */ |
| 321 | { X, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 322 | { X, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 323 | { X, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 324 | { X, 0, 0x4, {0x380000, 512 * 1024} }, |
| 325 | { X, 0, 0x5, {0x300000, 1024 * 1024} }, |
| 326 | { X, 0, 0x6, {0x200000, 2048 * 1024} }, |
| 327 | { X, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 328 | |
| 329 | { X, 1, 0x0, {0x000000, 4096 * 1024} }, |
| 330 | { X, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 331 | { X, 1, 0x2, {0x000000, 3072 * 1024} }, |
| 332 | { X, 1, 0x3, {0x000000, 3584 * 1024} }, |
| 333 | { X, 1, 0x4, {0x000000, 3840 * 1024} }, |
| 334 | { X, 1, 0x5, {0x000000, 3968 * 1024} }, |
| 335 | { X, 1, 0x6, {0x000000, 4032 * 1024} }, |
| 336 | { X, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 337 | }; |
| 338 | |
Vincent Palatin | 87e092a | 2013-02-28 15:46:14 -0800 | [diff] [blame] | 339 | static struct w25q_range mx25u3235e_ranges[] = { |
| 340 | { X, 0, 0, {0, 0} }, /* none */ |
| 341 | { 0, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 342 | { 0, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 343 | { 0, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 344 | { 0, 0, 0x4, {0x380000, 512 * 1024} }, |
| 345 | { 0, 0, 0x5, {0x300000, 1024 * 1024} }, |
| 346 | { 0, 0, 0x6, {0x200000, 2048 * 1024} }, |
| 347 | { 0, 0, 0x7, {0x000000, 4096 * 1024} }, |
| 348 | |
| 349 | { 0, 1, 0x0, {0x000000, 4096 * 1024} }, |
| 350 | { 0, 1, 0x1, {0x000000, 2048 * 1024} }, |
| 351 | { 0, 1, 0x2, {0x000000, 3072 * 1024} }, |
| 352 | { 0, 1, 0x3, {0x000000, 3584 * 1024} }, |
| 353 | { 0, 1, 0x4, {0x000000, 3840 * 1024} }, |
| 354 | { 0, 1, 0x5, {0x000000, 3968 * 1024} }, |
| 355 | { 0, 1, 0x6, {0x000000, 4032 * 1024} }, |
| 356 | { 0, 1, 0x7, {0x000000, 4096 * 1024} }, |
| 357 | }; |
| 358 | |
Jongpil | 66a9649 | 2014-08-14 17:59:06 +0900 | [diff] [blame] | 359 | static struct w25q_range mx25u6435e_ranges[] = { |
| 360 | { X, 0, 0, {0, 0} }, /* none */ |
| 361 | { 0, 0, 0x1, {0x7f0000, 1 * 64 * 1024} }, /* block 127 */ |
| 362 | { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 363 | { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 364 | { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 365 | { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 366 | { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 367 | { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 368 | |
| 369 | { 0, 1, 0x0, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 370 | { 0, 1, 0x1, {0x000000, 96 * 64 * 1024} }, /* blocks 0-95 */ |
| 371 | { 0, 1, 0x2, {0x000000, 112 * 64 * 1024} }, /* blocks 0-111 */ |
| 372 | { 0, 1, 0x3, {0x000000, 120 * 64 * 1024} }, /* blocks 0-119 */ |
| 373 | { 0, 1, 0x4, {0x000000, 124 * 64 * 1024} }, /* blocks 0-123 */ |
| 374 | { 0, 1, 0x5, {0x000000, 126 * 64 * 1024} }, /* blocks 0-125 */ |
| 375 | { 0, 1, 0x6, {0x000000, 127 * 64 * 1024} }, /* blocks 0-126 */ |
| 376 | { 0, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* blocks 0-127 */ |
| 377 | }; |
| 378 | |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 379 | static struct w25q_range n25q064_ranges[] = { |
| 380 | { X, 0, 0, {0, 0} }, /* none */ |
| 381 | |
| 382 | { 0, 0, 0x1, {0x7f0000, 64 * 1024} }, /* block 127 */ |
| 383 | { 0, 0, 0x2, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 384 | { 0, 0, 0x3, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 385 | { 0, 0, 0x4, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 386 | { 0, 0, 0x5, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 387 | { 0, 0, 0x6, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 388 | { 0, 0, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 389 | |
| 390 | { 1, 0, 0x1, {0x000000, 64 * 1024} }, /* block 0 */ |
| 391 | { 1, 0, 0x2, {0x000000, 2 * 64 * 1024} }, /* blocks 0-1 */ |
| 392 | { 1, 0, 0x3, {0x000000, 4 * 64 * 1024} }, /* blocks 0-3 */ |
| 393 | { 1, 0, 0x4, {0x000000, 8 * 64 * 1024} }, /* blocks 0-7 */ |
| 394 | { 1, 0, 0x5, {0x000000, 16 * 64 * 1024} }, /* blocks 0-15 */ |
| 395 | { 1, 0, 0x6, {0x000000, 32 * 64 * 1024} }, /* blocks 0-31 */ |
| 396 | { 1, 0, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 397 | |
| 398 | { X, 1, 0x0, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 399 | { X, 1, 0x1, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 400 | { X, 1, 0x2, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 401 | { X, 1, 0x3, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 402 | { X, 1, 0x4, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 403 | { X, 1, 0x5, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 404 | { X, 1, 0x6, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 405 | { X, 1, 0x7, {0x000000, 128 * 64 * 1024} }, /* all */ |
| 406 | }; |
| 407 | |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 408 | static struct w25q_range w25q16_ranges[] = { |
| 409 | { X, X, 0, {0, 0} }, /* none */ |
| 410 | { 0, 0, 0x1, {0x1f0000, 64 * 1024} }, |
| 411 | { 0, 0, 0x2, {0x1e0000, 128 * 1024} }, |
| 412 | { 0, 0, 0x3, {0x1c0000, 256 * 1024} }, |
| 413 | { 0, 0, 0x4, {0x180000, 512 * 1024} }, |
| 414 | { 0, 0, 0x5, {0x100000, 1024 * 1024} }, |
| 415 | |
| 416 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 417 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 418 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 419 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 420 | { 0, 1, 0x5, {0x000000, 1024 * 1024} }, |
| 421 | { X, X, 0x6, {0x000000, 2048 * 1024} }, |
| 422 | { X, X, 0x7, {0x000000, 2048 * 1024} }, |
| 423 | |
| 424 | { 1, 0, 0x1, {0x1ff000, 4 * 1024} }, |
| 425 | { 1, 0, 0x2, {0x1fe000, 8 * 1024} }, |
| 426 | { 1, 0, 0x3, {0x1fc000, 16 * 1024} }, |
| 427 | { 1, 0, 0x4, {0x1f8000, 32 * 1024} }, |
| 428 | { 1, 0, 0x5, {0x1f8000, 32 * 1024} }, |
| 429 | |
| 430 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 431 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 432 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 433 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 434 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 435 | }; |
| 436 | |
| 437 | static struct w25q_range w25q32_ranges[] = { |
| 438 | { X, X, 0, {0, 0} }, /* none */ |
| 439 | { 0, 0, 0x1, {0x3f0000, 64 * 1024} }, |
| 440 | { 0, 0, 0x2, {0x3e0000, 128 * 1024} }, |
| 441 | { 0, 0, 0x3, {0x3c0000, 256 * 1024} }, |
| 442 | { 0, 0, 0x4, {0x380000, 512 * 1024} }, |
| 443 | { 0, 0, 0x5, {0x300000, 1024 * 1024} }, |
David Hendricks | 05653ff | 2010-06-15 16:05:12 -0700 | [diff] [blame] | 444 | { 0, 0, 0x6, {0x200000, 2048 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 445 | |
| 446 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 447 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 448 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 449 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 450 | { 0, 1, 0x5, {0x000000, 1024 * 1024} }, |
| 451 | { 0, 1, 0x6, {0x000000, 2048 * 1024} }, |
| 452 | { X, X, 0x7, {0x000000, 4096 * 1024} }, |
| 453 | |
| 454 | { 1, 0, 0x1, {0x3ff000, 4 * 1024} }, |
| 455 | { 1, 0, 0x2, {0x3fe000, 8 * 1024} }, |
| 456 | { 1, 0, 0x3, {0x3fc000, 16 * 1024} }, |
| 457 | { 1, 0, 0x4, {0x3f8000, 32 * 1024} }, |
| 458 | { 1, 0, 0x5, {0x3f8000, 32 * 1024} }, |
| 459 | |
| 460 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 461 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 462 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 463 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 464 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 465 | }; |
| 466 | |
| 467 | static struct w25q_range w25q80_ranges[] = { |
| 468 | { X, X, 0, {0, 0} }, /* none */ |
| 469 | { 0, 0, 0x1, {0x0f0000, 64 * 1024} }, |
| 470 | { 0, 0, 0x2, {0x0e0000, 128 * 1024} }, |
| 471 | { 0, 0, 0x3, {0x0c0000, 256 * 1024} }, |
| 472 | { 0, 0, 0x4, {0x080000, 512 * 1024} }, |
| 473 | |
| 474 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 475 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 476 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 477 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
David Hendricks | 05653ff | 2010-06-15 16:05:12 -0700 | [diff] [blame] | 478 | { X, X, 0x6, {0x000000, 1024 * 1024} }, |
| 479 | { X, X, 0x7, {0x000000, 1024 * 1024} }, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 480 | |
| 481 | { 1, 0, 0x1, {0x1ff000, 4 * 1024} }, |
| 482 | { 1, 0, 0x2, {0x1fe000, 8 * 1024} }, |
| 483 | { 1, 0, 0x3, {0x1fc000, 16 * 1024} }, |
| 484 | { 1, 0, 0x4, {0x1f8000, 32 * 1024} }, |
| 485 | { 1, 0, 0x5, {0x1f8000, 32 * 1024} }, |
| 486 | |
| 487 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 488 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 489 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 490 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 491 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 492 | }; |
| 493 | |
David Hendricks | 2c4a76c | 2010-06-28 14:00:43 -0700 | [diff] [blame] | 494 | static struct w25q_range w25q64_ranges[] = { |
| 495 | { X, X, 0, {0, 0} }, /* none */ |
| 496 | |
| 497 | { 0, 0, 0x1, {0x7e0000, 128 * 1024} }, |
| 498 | { 0, 0, 0x2, {0x7c0000, 256 * 1024} }, |
| 499 | { 0, 0, 0x3, {0x780000, 512 * 1024} }, |
| 500 | { 0, 0, 0x4, {0x700000, 1024 * 1024} }, |
| 501 | { 0, 0, 0x5, {0x600000, 2048 * 1024} }, |
| 502 | { 0, 0, 0x6, {0x400000, 4096 * 1024} }, |
| 503 | |
| 504 | { 0, 1, 0x1, {0x000000, 128 * 1024} }, |
| 505 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 506 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 507 | { 0, 1, 0x4, {0x000000, 1024 * 1024} }, |
| 508 | { 0, 1, 0x5, {0x000000, 2048 * 1024} }, |
| 509 | { 0, 1, 0x6, {0x000000, 4096 * 1024} }, |
| 510 | { X, X, 0x7, {0x000000, 8192 * 1024} }, |
| 511 | |
| 512 | { 1, 0, 0x1, {0x7ff000, 4 * 1024} }, |
| 513 | { 1, 0, 0x2, {0x7fe000, 8 * 1024} }, |
| 514 | { 1, 0, 0x3, {0x7fc000, 16 * 1024} }, |
| 515 | { 1, 0, 0x4, {0x7f8000, 32 * 1024} }, |
| 516 | { 1, 0, 0x5, {0x7f8000, 32 * 1024} }, |
| 517 | |
| 518 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 519 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 520 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 521 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 522 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 523 | }; |
| 524 | |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 525 | struct w25q_range w25x10_ranges[] = { |
| 526 | { X, X, 0, {0, 0} }, /* none */ |
| 527 | { 0, 0, 0x1, {0x010000, 64 * 1024} }, |
| 528 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 529 | { X, X, 0x2, {0x000000, 128 * 1024} }, |
| 530 | { X, X, 0x3, {0x000000, 128 * 1024} }, |
| 531 | }; |
| 532 | |
| 533 | struct w25q_range w25x20_ranges[] = { |
| 534 | { X, X, 0, {0, 0} }, /* none */ |
| 535 | { 0, 0, 0x1, {0x030000, 64 * 1024} }, |
| 536 | { 0, 0, 0x2, {0x020000, 128 * 1024} }, |
| 537 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 538 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 539 | { 0, X, 0x3, {0x000000, 256 * 1024} }, |
| 540 | }; |
| 541 | |
David Hendricks | 470ca95 | 2010-08-13 14:01:53 -0700 | [diff] [blame] | 542 | struct w25q_range w25x40_ranges[] = { |
| 543 | { X, X, 0, {0, 0} }, /* none */ |
| 544 | { 0, 0, 0x1, {0x070000, 64 * 1024} }, |
| 545 | { 0, 0, 0x2, {0x060000, 128 * 1024} }, |
| 546 | { 0, 0, 0x3, {0x040000, 256 * 1024} }, |
| 547 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 548 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 549 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 550 | { 0, X, 0x4, {0x000000, 512 * 1024} }, |
| 551 | }; |
| 552 | |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 553 | struct w25q_range w25x80_ranges[] = { |
| 554 | { X, X, 0, {0, 0} }, /* none */ |
| 555 | { 0, 0, 0x1, {0x0F0000, 64 * 1024} }, |
| 556 | { 0, 0, 0x2, {0x0E0000, 128 * 1024} }, |
| 557 | { 0, 0, 0x3, {0x0C0000, 256 * 1024} }, |
| 558 | { 0, 0, 0x4, {0x080000, 512 * 1024} }, |
| 559 | { 0, 1, 0x1, {0x000000, 64 * 1024} }, |
| 560 | { 0, 1, 0x2, {0x000000, 128 * 1024} }, |
| 561 | { 0, 1, 0x3, {0x000000, 256 * 1024} }, |
| 562 | { 0, 1, 0x4, {0x000000, 512 * 1024} }, |
| 563 | { 0, X, 0x5, {0x000000, 1024 * 1024} }, |
| 564 | { 0, X, 0x6, {0x000000, 1024 * 1024} }, |
| 565 | { 0, X, 0x7, {0x000000, 1024 * 1024} }, |
| 566 | }; |
| 567 | |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 568 | static struct w25q_range gd25q64_ranges[] = { |
| 569 | { X, X, 0, {0, 0} }, /* none */ |
| 570 | { 0, 0, 0x1, {0x7e0000, 128 * 1024} }, |
| 571 | { 0, 0, 0x2, {0x7c0000, 256 * 1024} }, |
| 572 | { 0, 0, 0x3, {0x780000, 512 * 1024} }, |
| 573 | { 0, 0, 0x4, {0x700000, 1024 * 1024} }, |
| 574 | { 0, 0, 0x5, {0x600000, 2048 * 1024} }, |
| 575 | { 0, 0, 0x6, {0x400000, 4096 * 1024} }, |
| 576 | |
| 577 | { 0, 1, 0x1, {0x000000, 128 * 1024} }, |
| 578 | { 0, 1, 0x2, {0x000000, 256 * 1024} }, |
| 579 | { 0, 1, 0x3, {0x000000, 512 * 1024} }, |
| 580 | { 0, 1, 0x4, {0x000000, 1024 * 1024} }, |
| 581 | { 0, 1, 0x5, {0x000000, 2048 * 1024} }, |
| 582 | { 0, 1, 0x6, {0x000000, 4096 * 1024} }, |
| 583 | { X, X, 0x7, {0x000000, 8192 * 1024} }, |
| 584 | |
| 585 | { 1, 0, 0x1, {0x7ff000, 4 * 1024} }, |
| 586 | { 1, 0, 0x2, {0x7fe000, 8 * 1024} }, |
| 587 | { 1, 0, 0x3, {0x7fc000, 16 * 1024} }, |
| 588 | { 1, 0, 0x4, {0x7f8000, 32 * 1024} }, |
| 589 | { 1, 0, 0x5, {0x7f8000, 32 * 1024} }, |
| 590 | { 1, 0, 0x6, {0x7f8000, 32 * 1024} }, |
| 591 | |
| 592 | { 1, 1, 0x1, {0x000000, 4 * 1024} }, |
| 593 | { 1, 1, 0x2, {0x000000, 8 * 1024} }, |
| 594 | { 1, 1, 0x3, {0x000000, 16 * 1024} }, |
| 595 | { 1, 1, 0x4, {0x000000, 32 * 1024} }, |
| 596 | { 1, 1, 0x5, {0x000000, 32 * 1024} }, |
| 597 | { 1, 1, 0x6, {0x000000, 32 * 1024} }, |
| 598 | }; |
| 599 | |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 600 | static struct w25q_range a25l040_ranges[] = { |
| 601 | { X, X, 0x0, {0, 0} }, /* none */ |
| 602 | { X, X, 0x1, {0x70000, 64 * 1024} }, |
| 603 | { X, X, 0x2, {0x60000, 128 * 1024} }, |
| 604 | { X, X, 0x3, {0x40000, 256 * 1024} }, |
| 605 | { X, X, 0x4, {0x00000, 512 * 1024} }, |
| 606 | { X, X, 0x5, {0x00000, 512 * 1024} }, |
| 607 | { X, X, 0x6, {0x00000, 512 * 1024} }, |
| 608 | { X, X, 0x7, {0x00000, 512 * 1024} }, |
| 609 | }; |
| 610 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 611 | /* Given a flash chip, this function returns its range table. */ |
| 612 | static int w25_range_table(const struct flashchip *flash, |
| 613 | struct w25q_range **w25q_ranges, |
| 614 | int *num_entries) |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 615 | { |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 616 | *w25q_ranges = 0; |
| 617 | *num_entries = 0; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 618 | |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 619 | switch (flash->manufacture_id) { |
| 620 | case WINBOND_NEX_ID: |
| 621 | switch(flash->model_id) { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 622 | case WINBOND_NEX_W25X10: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 623 | *w25q_ranges = w25x10_ranges; |
| 624 | *num_entries = ARRAY_SIZE(w25x10_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 625 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 626 | case WINBOND_NEX_W25X20: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 627 | *w25q_ranges = w25x20_ranges; |
| 628 | *num_entries = ARRAY_SIZE(w25x20_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 629 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 630 | case WINBOND_NEX_W25X40: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 631 | *w25q_ranges = w25x40_ranges; |
| 632 | *num_entries = ARRAY_SIZE(w25x40_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 633 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 634 | case WINBOND_NEX_W25X80: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 635 | *w25q_ranges = w25x80_ranges; |
| 636 | *num_entries = ARRAY_SIZE(w25x80_ranges); |
Louis Yung-Chieh Lo | 232951f | 2010-09-16 11:30:00 +0800 | [diff] [blame] | 637 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 638 | case WINBOND_NEX_W25Q80: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 639 | *w25q_ranges = w25q80_ranges; |
| 640 | *num_entries = ARRAY_SIZE(w25q80_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 641 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 642 | case WINBOND_NEX_W25Q16: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 643 | *w25q_ranges = w25q16_ranges; |
| 644 | *num_entries = ARRAY_SIZE(w25q16_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 645 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 646 | case WINBOND_NEX_W25Q32: |
Louis Yung-Chieh Lo | 469707f | 2012-05-18 16:38:37 +0800 | [diff] [blame] | 647 | case WINBOND_NEX_W25Q32DW: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 648 | *w25q_ranges = w25q32_ranges; |
| 649 | *num_entries = ARRAY_SIZE(w25q32_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 650 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 651 | case WINBOND_NEX_W25Q64: |
AdamTsai | 141a262 | 2013-12-31 14:07:15 +0800 | [diff] [blame] | 652 | case WINBOND_NEX_W25Q64DW: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 653 | *w25q_ranges = w25q64_ranges; |
| 654 | *num_entries = ARRAY_SIZE(w25q64_ranges); |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 655 | break; |
| 656 | default: |
| 657 | msg_cerr("%s() %d: WINBOND flash chip mismatch (0x%04x)" |
| 658 | ", aborting\n", __func__, __LINE__, |
| 659 | flash->model_id); |
| 660 | return -1; |
| 661 | } |
David Hendricks | 2c4a76c | 2010-06-28 14:00:43 -0700 | [diff] [blame] | 662 | break; |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 663 | case EON_ID_NOPREFIX: |
| 664 | switch (flash->model_id) { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 665 | case EON_EN25F40: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 666 | *w25q_ranges = en25f40_ranges; |
| 667 | *num_entries = ARRAY_SIZE(en25f40_ranges); |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 668 | break; |
David Hendricks | e185bf2 | 2011-05-24 15:34:18 -0700 | [diff] [blame] | 669 | case EON_EN25Q40: |
| 670 | *w25q_ranges = en25q40_ranges; |
| 671 | *num_entries = ARRAY_SIZE(en25q40_ranges); |
| 672 | break; |
| 673 | case EON_EN25Q80: |
| 674 | *w25q_ranges = en25q80_ranges; |
| 675 | *num_entries = ARRAY_SIZE(en25q80_ranges); |
| 676 | break; |
| 677 | case EON_EN25Q32: |
| 678 | *w25q_ranges = en25q32_ranges; |
| 679 | *num_entries = ARRAY_SIZE(en25q32_ranges); |
| 680 | break; |
| 681 | case EON_EN25Q64: |
| 682 | *w25q_ranges = en25q64_ranges; |
| 683 | *num_entries = ARRAY_SIZE(en25q64_ranges); |
| 684 | break; |
| 685 | case EON_EN25Q128: |
| 686 | *w25q_ranges = en25q128_ranges; |
| 687 | *num_entries = ARRAY_SIZE(en25q128_ranges); |
| 688 | break; |
Marc Jones | b2f9002 | 2014-04-29 17:37:23 -0600 | [diff] [blame] | 689 | case EON_EN25S64: |
| 690 | *w25q_ranges = en25s64_ranges; |
| 691 | *num_entries = ARRAY_SIZE(en25s64_ranges); |
| 692 | break; |
David Hendricks | 57566ed | 2010-08-16 18:24:45 -0700 | [diff] [blame] | 693 | default: |
| 694 | msg_cerr("%s():%d: EON flash chip mismatch (0x%04x)" |
| 695 | ", aborting\n", __func__, __LINE__, |
| 696 | flash->model_id); |
| 697 | return -1; |
| 698 | } |
| 699 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 700 | case MACRONIX_ID: |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 701 | switch (flash->model_id) { |
David Hendricks | f8f00c7 | 2011-02-01 12:39:46 -0800 | [diff] [blame] | 702 | case MACRONIX_MX25L1005: |
| 703 | *w25q_ranges = mx25l1005_ranges; |
| 704 | *num_entries = ARRAY_SIZE(mx25l1005_ranges); |
| 705 | break; |
| 706 | case MACRONIX_MX25L2005: |
| 707 | *w25q_ranges = mx25l2005_ranges; |
| 708 | *num_entries = ARRAY_SIZE(mx25l2005_ranges); |
| 709 | break; |
| 710 | case MACRONIX_MX25L4005: |
| 711 | *w25q_ranges = mx25l4005_ranges; |
| 712 | *num_entries = ARRAY_SIZE(mx25l4005_ranges); |
| 713 | break; |
| 714 | case MACRONIX_MX25L8005: |
| 715 | *w25q_ranges = mx25l8005_ranges; |
| 716 | *num_entries = ARRAY_SIZE(mx25l8005_ranges); |
| 717 | break; |
| 718 | case MACRONIX_MX25L1605: |
| 719 | /* FIXME: MX25L1605 and MX25L1605D have different write |
| 720 | * protection capabilities, but share IDs */ |
| 721 | *w25q_ranges = mx25l1605d_ranges; |
| 722 | *num_entries = ARRAY_SIZE(mx25l1605d_ranges); |
| 723 | break; |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 724 | case MACRONIX_MX25L3205: |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 725 | *w25q_ranges = mx25l3205d_ranges; |
| 726 | *num_entries = ARRAY_SIZE(mx25l3205d_ranges); |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 727 | break; |
Vincent Palatin | 87e092a | 2013-02-28 15:46:14 -0800 | [diff] [blame] | 728 | case MACRONIX_MX25U3235E: |
| 729 | *w25q_ranges = mx25u3235e_ranges; |
| 730 | *num_entries = ARRAY_SIZE(mx25u3235e_ranges); |
| 731 | break; |
Jongpil | 66a9649 | 2014-08-14 17:59:06 +0900 | [diff] [blame] | 732 | case MACRONIX_MX25U6435E: |
| 733 | *w25q_ranges = mx25u6435e_ranges; |
| 734 | *num_entries = ARRAY_SIZE(mx25u6435e_ranges); |
| 735 | break; |
David Hendricks | ac72e36 | 2010-08-16 18:20:03 -0700 | [diff] [blame] | 736 | default: |
| 737 | msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)" |
| 738 | ", aborting\n", __func__, __LINE__, |
| 739 | flash->model_id); |
| 740 | return -1; |
| 741 | } |
| 742 | break; |
David Hendricks | bfa624b | 2012-07-24 12:47:59 -0700 | [diff] [blame] | 743 | case ST_ID: |
| 744 | switch(flash->model_id) { |
| 745 | case ST_N25Q064__1E: |
| 746 | case ST_N25Q064__3E: |
| 747 | *w25q_ranges = n25q064_ranges; |
| 748 | *num_entries = ARRAY_SIZE(n25q064_ranges); |
| 749 | break; |
| 750 | default: |
| 751 | msg_cerr("%s() %d: Micron flash chip mismatch" |
| 752 | " (0x%04x), aborting\n", __func__, __LINE__, |
| 753 | flash->model_id); |
| 754 | return -1; |
| 755 | } |
| 756 | break; |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 757 | case GIGADEVICE_ID: |
| 758 | switch(flash->model_id) { |
| 759 | case GIGADEVICE_GD25LQ32: |
| 760 | *w25q_ranges = w25q32_ranges; |
| 761 | *num_entries = ARRAY_SIZE(w25q32_ranges); |
| 762 | break; |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 763 | case GIGADEVICE_GD25Q64: |
Marc Jones | b18734f | 2014-04-03 16:19:47 -0600 | [diff] [blame] | 764 | case GIGADEVICE_GD25LQ64: |
Shawn Nematbakhsh | 9e8ef49 | 2012-09-01 21:58:03 -0700 | [diff] [blame] | 765 | *w25q_ranges = gd25q64_ranges; |
| 766 | *num_entries = ARRAY_SIZE(gd25q64_ranges); |
| 767 | break; |
| 768 | /* TODO(shawnn): add support for other GD parts */ |
Bryan Freed | 9a0051f | 2012-05-22 16:06:09 -0700 | [diff] [blame] | 769 | default: |
| 770 | msg_cerr("%s() %d: GigaDevice flash chip mismatch" |
| 771 | " (0x%04x), aborting\n", __func__, __LINE__, |
| 772 | flash->model_id); |
| 773 | return -1; |
| 774 | } |
| 775 | break; |
Louis Yung-Chieh Lo | c8ec715 | 2012-09-17 17:38:35 +0800 | [diff] [blame] | 776 | case AMIC_ID_NOPREFIX: |
| 777 | switch(flash->model_id) { |
| 778 | case AMIC_A25L040: |
| 779 | *w25q_ranges = a25l040_ranges; |
| 780 | *num_entries = ARRAY_SIZE(a25l040_ranges); |
| 781 | break; |
| 782 | default: |
| 783 | msg_cerr("%s() %d: AMIC flash chip mismatch" |
| 784 | " (0x%04x), aborting\n", __func__, __LINE__, |
| 785 | flash->model_id); |
| 786 | return -1; |
| 787 | } |
| 788 | break; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 789 | default: |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 790 | msg_cerr("%s: flash vendor (0x%x) not found, aborting\n", |
| 791 | __func__, flash->manufacture_id); |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 792 | return -1; |
| 793 | } |
| 794 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 795 | return 0; |
| 796 | } |
| 797 | |
| 798 | int w25_range_to_status(const struct flashchip *flash, |
| 799 | unsigned int start, unsigned int len, |
| 800 | struct w25q_status *status) |
| 801 | { |
| 802 | struct w25q_range *w25q_ranges; |
| 803 | int i, range_found = 0; |
| 804 | int num_entries; |
| 805 | |
| 806 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 807 | for (i = 0; i < num_entries; i++) { |
| 808 | struct wp_range *r = &w25q_ranges[i].range; |
| 809 | |
| 810 | msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n", |
| 811 | start, len, r->start, r->len); |
| 812 | if ((start == r->start) && (len == r->len)) { |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 813 | status->bp0 = w25q_ranges[i].bp & 1; |
| 814 | status->bp1 = w25q_ranges[i].bp >> 1; |
| 815 | status->bp2 = w25q_ranges[i].bp >> 2; |
| 816 | status->tb = w25q_ranges[i].tb; |
| 817 | status->sec = w25q_ranges[i].sec; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 818 | |
| 819 | range_found = 1; |
| 820 | break; |
| 821 | } |
| 822 | } |
| 823 | |
| 824 | if (!range_found) { |
| 825 | msg_cerr("matching range not found\n"); |
| 826 | return -1; |
| 827 | } |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 828 | return 0; |
| 829 | } |
| 830 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 831 | int w25_status_to_range(const struct flashchip *flash, |
| 832 | const struct w25q_status *status, |
| 833 | unsigned int *start, unsigned int *len) |
| 834 | { |
| 835 | struct w25q_range *w25q_ranges; |
| 836 | int i, status_found = 0; |
| 837 | int num_entries; |
| 838 | |
| 839 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
| 840 | for (i = 0; i < num_entries; i++) { |
| 841 | int bp; |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 842 | int table_bp, table_tb, table_sec; |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 843 | |
| 844 | bp = status->bp0 | (status->bp1 << 1) | (status->bp2 << 2); |
| 845 | msg_cspew("comparing 0x%x 0x%x / 0x%x 0x%x / 0x%x 0x%x\n", |
| 846 | bp, w25q_ranges[i].bp, |
| 847 | status->tb, w25q_ranges[i].tb, |
| 848 | status->sec, w25q_ranges[i].sec); |
Louis Yung-Chieh Lo | edd3930 | 2011-11-10 15:43:06 +0800 | [diff] [blame] | 849 | table_bp = w25q_ranges[i].bp; |
| 850 | table_tb = w25q_ranges[i].tb; |
| 851 | table_sec = w25q_ranges[i].sec; |
| 852 | if ((bp == table_bp || table_bp == X) && |
| 853 | (status->tb == table_tb || table_tb == X) && |
| 854 | (status->sec == table_sec || table_sec == X)) { |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 855 | *start = w25q_ranges[i].range.start; |
| 856 | *len = w25q_ranges[i].range.len; |
| 857 | |
| 858 | status_found = 1; |
| 859 | break; |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | if (!status_found) { |
| 864 | msg_cerr("matching status not found\n"); |
| 865 | return -1; |
| 866 | } |
| 867 | return 0; |
| 868 | } |
| 869 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 870 | /* Given a [start, len], this function calls w25_range_to_status() to convert |
| 871 | * it to flash-chip-specific range bits, then sets into status register. |
| 872 | */ |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 873 | static int w25_set_range(const struct flashchip *flash, |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 874 | unsigned int start, unsigned int len) |
| 875 | { |
| 876 | struct w25q_status status; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 877 | int tmp = 0; |
| 878 | int expected = 0; |
David Hendricks | d494b0a | 2010-08-16 16:28:50 -0700 | [diff] [blame] | 879 | |
| 880 | memset(&status, 0, sizeof(status)); |
| 881 | tmp = spi_read_status_register(); |
| 882 | memcpy(&status, &tmp, 1); |
| 883 | msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp); |
| 884 | |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 885 | if (w25_range_to_status(flash, start, len, &status)) return -1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 886 | |
| 887 | msg_cdbg("status.busy: %x\n", status.busy); |
| 888 | msg_cdbg("status.wel: %x\n", status.wel); |
| 889 | msg_cdbg("status.bp0: %x\n", status.bp0); |
| 890 | msg_cdbg("status.bp1: %x\n", status.bp1); |
| 891 | msg_cdbg("status.bp2: %x\n", status.bp2); |
| 892 | msg_cdbg("status.tb: %x\n", status.tb); |
| 893 | msg_cdbg("status.sec: %x\n", status.sec); |
| 894 | msg_cdbg("status.srp0: %x\n", status.srp0); |
| 895 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 896 | memcpy(&expected, &status, sizeof(status)); |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 897 | spi_write_status_register(flash, expected); |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 898 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 899 | tmp = spi_read_status_register(); |
| 900 | msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp); |
| 901 | if ((tmp & MASK_WP_AREA) == (expected & MASK_WP_AREA)) { |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 902 | return 0; |
| 903 | } else { |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 904 | msg_cerr("expected=0x%02x, but actual=0x%02x.\n", |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 905 | expected, tmp); |
| 906 | return 1; |
| 907 | } |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 908 | } |
| 909 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 910 | /* Print out the current status register value with human-readable text. */ |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 911 | static int w25_wp_status(const struct flashchip *flash) |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 912 | { |
| 913 | struct w25q_status status; |
| 914 | int tmp; |
David Hendricks | ce8ded3 | 2010-10-08 11:23:38 -0700 | [diff] [blame] | 915 | unsigned int start, len; |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 916 | int ret = 0; |
| 917 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 918 | memset(&status, 0, sizeof(status)); |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 919 | tmp = spi_read_status_register(); |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 920 | memcpy(&status, &tmp, 1); |
| 921 | msg_cinfo("WP: status: 0x%02x\n", tmp); |
| 922 | msg_cinfo("WP: status.srp0: %x\n", status.srp0); |
| 923 | msg_cinfo("WP: write protect is %s.\n", |
| 924 | status.srp0 ? "enabled" : "disabled"); |
| 925 | |
| 926 | msg_cinfo("WP: write protect range: "); |
| 927 | if (w25_status_to_range(flash, &status, &start, &len)) { |
| 928 | msg_cinfo("(cannot resolve the range)\n"); |
| 929 | ret = -1; |
| 930 | } else { |
| 931 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 932 | } |
| 933 | |
| 934 | return ret; |
| 935 | } |
| 936 | |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 937 | /* Set/clear the SRP0 bit in the status register. */ |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 938 | static int w25_set_srp0(const struct flashchip *flash, int enable) |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 939 | { |
| 940 | struct w25q_status status; |
| 941 | int tmp = 0; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 942 | int expected = 0; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 943 | |
| 944 | memset(&status, 0, sizeof(status)); |
| 945 | tmp = spi_read_status_register(); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 946 | /* FIXME: this is NOT endian-free copy. */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 947 | memcpy(&status, &tmp, 1); |
| 948 | msg_cdbg("%s: old status: 0x%02x\n", __func__, tmp); |
| 949 | |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 950 | status.srp0 = enable ? 1 : 0; |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 951 | memcpy(&expected, &status, sizeof(status)); |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 952 | spi_write_status_register(flash, expected); |
Louis Yung-Chieh Lo | 165b464 | 2010-11-26 16:35:26 +0800 | [diff] [blame] | 953 | |
| 954 | tmp = spi_read_status_register(); |
| 955 | msg_cdbg("%s: new status: 0x%02x\n", __func__, tmp); |
| 956 | if ((tmp & MASK_WP_AREA) != (expected & MASK_WP_AREA)) |
| 957 | return 1; |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 958 | |
| 959 | return 0; |
| 960 | } |
| 961 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 962 | static int w25_enable_writeprotect(const struct flashchip *flash, |
| 963 | enum wp_mode wp_mode) |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 964 | { |
| 965 | int ret; |
| 966 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 967 | switch (wp_mode) { |
| 968 | case WP_MODE_HARDWARE: |
| 969 | ret = w25_set_srp0(flash, 1); |
| 970 | break; |
| 971 | default: |
| 972 | msg_cerr("%s(): unsupported write-protect mode\n", __func__); |
| 973 | return 1; |
| 974 | } |
| 975 | |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 976 | if (ret) |
| 977 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 978 | return ret; |
| 979 | } |
| 980 | |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 981 | static int w25_disable_writeprotect(const struct flashchip *flash) |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 982 | { |
| 983 | int ret; |
| 984 | |
| 985 | ret = w25_set_srp0(flash, 0); |
David Hendricks | c801adb | 2010-12-09 16:58:56 -0800 | [diff] [blame] | 986 | if (ret) |
| 987 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 988 | return ret; |
| 989 | } |
| 990 | |
David Hendricks | 9104083 | 2011-07-08 20:01:09 -0700 | [diff] [blame] | 991 | static int w25_list_ranges(const struct flashchip *flash) |
David Hendricks | 0f7f538 | 2011-02-11 18:12:31 -0800 | [diff] [blame] | 992 | { |
| 993 | struct w25q_range *w25q_ranges; |
| 994 | int i, num_entries; |
| 995 | |
| 996 | if (w25_range_table(flash, &w25q_ranges, &num_entries)) return -1; |
| 997 | for (i = 0; i < num_entries; i++) { |
| 998 | msg_cinfo("start: 0x%06x, length: 0x%06x\n", |
| 999 | w25q_ranges[i].range.start, |
| 1000 | w25q_ranges[i].range.len); |
| 1001 | } |
| 1002 | |
| 1003 | return 0; |
| 1004 | } |
| 1005 | |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1006 | /* FIXME: Move to spi25.c if it's a JEDEC standard opcode */ |
| 1007 | uint8_t w25q_read_status_register_2(void) |
| 1008 | { |
| 1009 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x35 }; |
| 1010 | unsigned char readarr[2]; |
| 1011 | int ret; |
| 1012 | |
| 1013 | /* Read Status Register */ |
| 1014 | ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
| 1015 | if (ret) { |
| 1016 | /* |
| 1017 | * FIXME: make this a benign failure for now in case we are |
| 1018 | * unable to execute the opcode |
| 1019 | */ |
| 1020 | msg_cdbg("RDSR2 failed!\n"); |
| 1021 | readarr[0] = 0x00; |
| 1022 | } |
| 1023 | |
| 1024 | return readarr[0]; |
| 1025 | } |
| 1026 | |
| 1027 | static int w25q_wp_status(const struct flashchip *flash) |
| 1028 | { |
| 1029 | struct w25q_status sr1; |
| 1030 | struct w25q_status_2 sr2; |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1031 | uint8_t tmp[2]; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1032 | unsigned int start, len; |
| 1033 | int ret = 0; |
| 1034 | |
| 1035 | memset(&sr1, 0, sizeof(sr1)); |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1036 | tmp[0] = spi_read_status_register(); |
| 1037 | memcpy(&sr1, &tmp[0], 1); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1038 | |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1039 | memset(&sr2, 0, sizeof(sr2)); |
| 1040 | tmp[1] = w25q_read_status_register_2(); |
| 1041 | memcpy(&sr2, &tmp[1], 1); |
| 1042 | |
| 1043 | msg_cinfo("WP: status: 0x%02x%02x\n", tmp[1], tmp[0]); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1044 | msg_cinfo("WP: status.srp0: %x\n", sr1.srp0); |
| 1045 | msg_cinfo("WP: status.srp1: %x\n", sr2.srp1); |
| 1046 | msg_cinfo("WP: write protect is %s.\n", |
| 1047 | (sr1.srp0 || sr2.srp1) ? "enabled" : "disabled"); |
| 1048 | |
| 1049 | msg_cinfo("WP: write protect range: "); |
| 1050 | if (w25_status_to_range(flash, &sr1, &start, &len)) { |
| 1051 | msg_cinfo("(cannot resolve the range)\n"); |
| 1052 | ret = -1; |
| 1053 | } else { |
| 1054 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 1055 | } |
| 1056 | |
| 1057 | return ret; |
| 1058 | } |
| 1059 | |
| 1060 | /* |
| 1061 | * W25Q adds an optional byte to the standard WRSR opcode. If /CS is |
| 1062 | * de-asserted after the first byte, then it acts like a JEDEC-standard |
| 1063 | * WRSR command. if /CS is asserted, then the next data byte is written |
| 1064 | * into status register 2. |
| 1065 | */ |
| 1066 | #define W25Q_WRSR_OUTSIZE 0x03 |
| 1067 | static int w25q_write_status_register_WREN(uint8_t s1, uint8_t s2) |
| 1068 | { |
| 1069 | int result; |
| 1070 | struct spi_command cmds[] = { |
| 1071 | { |
| 1072 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
| 1073 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 1074 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 1075 | .readcnt = 0, |
| 1076 | .readarr = NULL, |
| 1077 | }, { |
| 1078 | .writecnt = W25Q_WRSR_OUTSIZE, |
| 1079 | .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 }, |
| 1080 | .readcnt = 0, |
| 1081 | .readarr = NULL, |
| 1082 | }, { |
| 1083 | .writecnt = 0, |
| 1084 | .writearr = NULL, |
| 1085 | .readcnt = 0, |
| 1086 | .readarr = NULL, |
| 1087 | }}; |
| 1088 | |
| 1089 | result = spi_send_multicommand(cmds); |
| 1090 | if (result) { |
| 1091 | msg_cerr("%s failed during command execution\n", |
| 1092 | __func__); |
| 1093 | } |
| 1094 | |
| 1095 | /* WRSR performs a self-timed erase before the changes take effect. */ |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 1096 | programmer_delay(100 * 1000); |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1097 | |
| 1098 | return result; |
| 1099 | } |
| 1100 | |
| 1101 | /* |
| 1102 | * Set/clear the SRP1 bit in status register 2. |
| 1103 | * FIXME: make this more generic if other chips use the same SR2 layout |
| 1104 | */ |
| 1105 | static int w25q_set_srp1(const struct flashchip *flash, int enable) |
| 1106 | { |
| 1107 | struct w25q_status sr1; |
| 1108 | struct w25q_status_2 sr2; |
| 1109 | uint8_t tmp, expected; |
| 1110 | |
| 1111 | tmp = spi_read_status_register(); |
| 1112 | memcpy(&sr1, &tmp, 1); |
| 1113 | tmp = w25q_read_status_register_2(); |
| 1114 | memcpy(&sr2, &tmp, 1); |
| 1115 | |
| 1116 | msg_cdbg("%s: old status 2: 0x%02x\n", __func__, tmp); |
| 1117 | |
| 1118 | sr2.srp1 = enable ? 1 : 0; |
| 1119 | |
| 1120 | memcpy(&expected, &sr2, 1); |
| 1121 | w25q_write_status_register_WREN(*((uint8_t *)&sr1), *((uint8_t *)&sr2)); |
| 1122 | |
| 1123 | tmp = w25q_read_status_register_2(); |
| 1124 | msg_cdbg("%s: new status 2: 0x%02x\n", __func__, tmp); |
| 1125 | if ((tmp & MASK_WP2_AREA) != (expected & MASK_WP2_AREA)) |
| 1126 | return 1; |
| 1127 | |
| 1128 | return 0; |
| 1129 | } |
| 1130 | |
| 1131 | enum wp_mode get_wp_mode(const char *mode_str) |
| 1132 | { |
| 1133 | enum wp_mode wp_mode = WP_MODE_UNKNOWN; |
| 1134 | |
| 1135 | if (!strcasecmp(mode_str, "hardware")) |
| 1136 | wp_mode = WP_MODE_HARDWARE; |
| 1137 | else if (!strcasecmp(mode_str, "power_cycle")) |
| 1138 | wp_mode = WP_MODE_POWER_CYCLE; |
| 1139 | else if (!strcasecmp(mode_str, "permanent")) |
| 1140 | wp_mode = WP_MODE_PERMANENT; |
| 1141 | |
| 1142 | return wp_mode; |
| 1143 | } |
| 1144 | |
| 1145 | static int w25q_disable_writeprotect(const struct flashchip *flash, |
| 1146 | enum wp_mode wp_mode) |
| 1147 | { |
| 1148 | int ret = 1; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1149 | struct w25q_status_2 sr2; |
| 1150 | uint8_t tmp; |
| 1151 | |
| 1152 | switch (wp_mode) { |
| 1153 | case WP_MODE_HARDWARE: |
| 1154 | ret = w25_set_srp0(flash, 0); |
| 1155 | break; |
| 1156 | case WP_MODE_POWER_CYCLE: |
| 1157 | tmp = w25q_read_status_register_2(); |
| 1158 | memcpy(&sr2, &tmp, 1); |
| 1159 | if (sr2.srp1) { |
| 1160 | msg_cerr("%s(): must disconnect power to disable " |
| 1161 | "write-protection\n", __func__); |
| 1162 | } else { |
| 1163 | ret = 0; |
| 1164 | } |
| 1165 | break; |
| 1166 | case WP_MODE_PERMANENT: |
| 1167 | msg_cerr("%s(): cannot disable permanent write-protection\n", |
| 1168 | __func__); |
| 1169 | break; |
| 1170 | default: |
| 1171 | msg_cerr("%s(): invalid mode specified\n", __func__); |
| 1172 | break; |
| 1173 | } |
| 1174 | |
| 1175 | if (ret) |
| 1176 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1177 | return ret; |
| 1178 | } |
| 1179 | |
| 1180 | static int w25q_disable_writeprotect_default(const struct flashchip *flash) |
| 1181 | { |
| 1182 | return w25q_disable_writeprotect(flash, WP_MODE_HARDWARE); |
| 1183 | } |
| 1184 | |
| 1185 | static int w25q_enable_writeprotect(const struct flashchip *flash, |
| 1186 | enum wp_mode wp_mode) |
| 1187 | { |
| 1188 | int ret = 1; |
| 1189 | struct w25q_status sr1; |
| 1190 | struct w25q_status_2 sr2; |
| 1191 | uint8_t tmp; |
| 1192 | |
| 1193 | switch (wp_mode) { |
| 1194 | case WP_MODE_HARDWARE: |
| 1195 | if (w25q_disable_writeprotect(flash, WP_MODE_POWER_CYCLE)) { |
| 1196 | msg_cerr("%s(): cannot disable power cycle WP mode\n", |
| 1197 | __func__); |
| 1198 | break; |
| 1199 | } |
| 1200 | |
| 1201 | tmp = spi_read_status_register(); |
| 1202 | memcpy(&sr1, &tmp, 1); |
| 1203 | if (sr1.srp0) |
| 1204 | ret = 0; |
| 1205 | else |
| 1206 | ret = w25_set_srp0(flash, 1); |
| 1207 | |
| 1208 | break; |
| 1209 | case WP_MODE_POWER_CYCLE: |
| 1210 | if (w25q_disable_writeprotect(flash, WP_MODE_HARDWARE)) { |
| 1211 | msg_cerr("%s(): cannot disable hardware WP mode\n", |
| 1212 | __func__); |
| 1213 | break; |
| 1214 | } |
| 1215 | |
| 1216 | tmp = w25q_read_status_register_2(); |
| 1217 | memcpy(&sr2, &tmp, 1); |
| 1218 | if (sr2.srp1) |
| 1219 | ret = 0; |
| 1220 | else |
| 1221 | ret = w25q_set_srp1(flash, 1); |
| 1222 | |
| 1223 | break; |
| 1224 | case WP_MODE_PERMANENT: |
| 1225 | tmp = spi_read_status_register(); |
| 1226 | memcpy(&sr1, &tmp, 1); |
| 1227 | if (sr1.srp0 == 0) { |
| 1228 | ret = w25_set_srp0(flash, 1); |
| 1229 | if (ret) { |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1230 | msg_perr("%s(): cannot enable SRP0 for " |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1231 | "permanent WP\n", __func__); |
| 1232 | break; |
| 1233 | } |
| 1234 | } |
| 1235 | |
| 1236 | tmp = w25q_read_status_register_2(); |
| 1237 | memcpy(&sr2, &tmp, 1); |
| 1238 | if (sr2.srp1 == 0) { |
| 1239 | ret = w25q_set_srp1(flash, 1); |
| 1240 | if (ret) { |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1241 | msg_perr("%s(): cannot enable SRP1 for " |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1242 | "permanent WP\n", __func__); |
| 1243 | break; |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | break; |
David Hendricks | f1bd880 | 2012-10-30 11:37:57 -0700 | [diff] [blame] | 1248 | default: |
| 1249 | msg_perr("%s(): invalid mode %d\n", __func__, wp_mode); |
| 1250 | break; |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1251 | } |
| 1252 | |
| 1253 | if (ret) |
| 1254 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1255 | return ret; |
| 1256 | } |
| 1257 | |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1258 | /* FIXME: Move to spi25.c if it's a JEDEC standard opcode */ |
| 1259 | uint8_t mx25l_read_config_register(void) |
| 1260 | { |
| 1261 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { 0x15 }; |
| 1262 | unsigned char readarr[2]; /* leave room for dummy byte */ |
| 1263 | int ret; |
| 1264 | |
| 1265 | ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
| 1266 | if (ret) { |
| 1267 | msg_cerr("RDCR failed!\n"); |
| 1268 | readarr[0] = 0x00; |
| 1269 | } |
| 1270 | |
| 1271 | return readarr[0]; |
| 1272 | } |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1273 | /* W25P, W25X, and many flash chips from various vendors */ |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1274 | struct wp wp_w25 = { |
David Hendricks | 0f7f538 | 2011-02-11 18:12:31 -0800 | [diff] [blame] | 1275 | .list_ranges = w25_list_ranges, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1276 | .set_range = w25_set_range, |
| 1277 | .enable = w25_enable_writeprotect, |
Louis Yung-Chieh Lo | c19d3c5 | 2010-10-08 11:59:16 +0800 | [diff] [blame] | 1278 | .disable = w25_disable_writeprotect, |
Louis Yung-Chieh Lo | a92e8b2 | 2010-10-08 13:31:27 +0800 | [diff] [blame] | 1279 | .wp_status = w25_wp_status, |
David Hendricks | 1c09f80 | 2012-10-03 11:03:48 -0700 | [diff] [blame] | 1280 | |
| 1281 | }; |
| 1282 | |
| 1283 | /* W25Q series has features such as a second status register and SFDP */ |
| 1284 | struct wp wp_w25q = { |
| 1285 | .list_ranges = w25_list_ranges, |
| 1286 | .set_range = w25_set_range, |
| 1287 | .enable = w25q_enable_writeprotect, |
| 1288 | /* |
| 1289 | * By default, disable hardware write-protection. We may change |
| 1290 | * this later if we want to add fine-grained write-protect disable |
| 1291 | * as a command-line option. |
| 1292 | */ |
| 1293 | .disable = w25q_disable_writeprotect_default, |
| 1294 | .wp_status = w25q_wp_status, |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 1295 | }; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1296 | |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1297 | struct generic_range gd25q32_cmp0_ranges[] = { |
| 1298 | /* none, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1299 | { { }, 0x00, {0, 0} }, |
| 1300 | { { }, 0x08, {0, 0} }, |
| 1301 | { { }, 0x10, {0, 0} }, |
| 1302 | { { }, 0x18, {0, 0} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1303 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1304 | { { }, 0x01, {0x3f0000, 64 * 1024} }, |
| 1305 | { { }, 0x02, {0x3e0000, 128 * 1024} }, |
| 1306 | { { }, 0x03, {0x3c0000, 256 * 1024} }, |
| 1307 | { { }, 0x04, {0x380000, 512 * 1024} }, |
| 1308 | { { }, 0x05, {0x300000, 1024 * 1024} }, |
| 1309 | { { }, 0x06, {0x200000, 2048 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1310 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1311 | { { }, 0x09, {0x000000, 64 * 1024} }, |
| 1312 | { { }, 0x0a, {0x000000, 128 * 1024} }, |
| 1313 | { { }, 0x0b, {0x000000, 256 * 1024} }, |
| 1314 | { { }, 0x0c, {0x000000, 512 * 1024} }, |
| 1315 | { { }, 0x0d, {0x000000, 1024 * 1024} }, |
| 1316 | { { }, 0x0e, {0x000000, 2048 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1317 | |
| 1318 | /* all, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1319 | { { }, 0x07, {0x000000, 4096 * 1024} }, |
| 1320 | { { }, 0x0f, {0x000000, 4096 * 1024} }, |
| 1321 | { { }, 0x17, {0x000000, 4096 * 1024} }, |
| 1322 | { { }, 0x1f, {0x000000, 4096 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1323 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1324 | { { }, 0x11, {0x3ff000, 4 * 1024} }, |
| 1325 | { { }, 0x12, {0x3fe000, 8 * 1024} }, |
| 1326 | { { }, 0x13, {0x3fc000, 16 * 1024} }, |
| 1327 | { { }, 0x14, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1328 | { { }, 0x15, {0x3f8000, 32 * 1024} }, /* bp0 => don't care */ |
| 1329 | { { }, 0x16, {0x3f8000, 32 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1330 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1331 | { { }, 0x19, {0x000000, 4 * 1024} }, |
| 1332 | { { }, 0x1a, {0x000000, 8 * 1024} }, |
| 1333 | { { }, 0x1b, {0x000000, 16 * 1024} }, |
| 1334 | { { }, 0x1c, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1335 | { { }, 0x1d, {0x000000, 32 * 1024} }, /* bp0 => don't care */ |
| 1336 | { { }, 0x1e, {0x000000, 32 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1337 | }; |
| 1338 | |
| 1339 | struct generic_range gd25q32_cmp1_ranges[] = { |
| 1340 | /* none, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1341 | { { }, 0x00, {0, 0} }, |
| 1342 | { { }, 0x08, {0, 0} }, |
| 1343 | { { }, 0x10, {0, 0} }, |
| 1344 | { { }, 0x18, {0, 0} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1345 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1346 | { { }, 0x01, {0x000000, 4032 * 1024} }, |
| 1347 | { { }, 0x02, {0x000000, 3968 * 1024} }, |
| 1348 | { { }, 0x03, {0x000000, 3840 * 1024} }, |
| 1349 | { { }, 0x04, {0x000000, 3584 * 1024} }, |
| 1350 | { { }, 0x05, {0x000000, 3 * 1024 * 1024} }, |
| 1351 | { { }, 0x06, {0x000000, 2 * 1024 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1352 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1353 | { { }, 0x09, {0x010000, 4032 * 1024} }, |
| 1354 | { { }, 0x0a, {0x020000, 3968 * 1024} }, |
| 1355 | { { }, 0x0b, {0x040000, 3840 * 1024} }, |
| 1356 | { { }, 0x0c, {0x080000, 3584 * 1024} }, |
| 1357 | { { }, 0x0d, {0x100000, 3 * 1024 * 1024} }, |
| 1358 | { { }, 0x0e, {0x200000, 2 * 1024 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1359 | |
| 1360 | /* all, bp4 and bp3 => don't care */ |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1361 | { { }, 0x07, {0x000000, 4096 * 1024} }, |
| 1362 | { { }, 0x0f, {0x000000, 4096 * 1024} }, |
| 1363 | { { }, 0x17, {0x000000, 4096 * 1024} }, |
| 1364 | { { }, 0x1f, {0x000000, 4096 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1365 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1366 | { { }, 0x11, {0x000000, 4092 * 1024} }, |
| 1367 | { { }, 0x12, {0x000000, 4088 * 1024} }, |
| 1368 | { { }, 0x13, {0x000000, 4080 * 1024} }, |
| 1369 | { { }, 0x14, {0x000000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1370 | { { }, 0x15, {0x000000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1371 | { { }, 0x16, {0x000000, 4064 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1372 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1373 | { { }, 0x19, {0x001000, 4092 * 1024} }, |
| 1374 | { { }, 0x1a, {0x002000, 4088 * 1024} }, |
| 1375 | { { }, 0x1b, {0x040000, 4080 * 1024} }, |
| 1376 | { { }, 0x1c, {0x080000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1377 | { { }, 0x1d, {0x080000, 4064 * 1024} }, /* bp0 => don't care */ |
| 1378 | { { }, 0x1e, {0x080000, 4064 * 1024} }, |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1379 | }; |
| 1380 | |
| 1381 | static struct generic_wp gd25q32_wp = { |
| 1382 | /* TODO: map second status register */ |
| 1383 | .sr1 = { .bp0_pos = 2, .bp_bits = 5, .srp_pos = 7 }, |
| 1384 | }; |
| 1385 | |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1386 | #if 0 |
| 1387 | /* FIXME: MX25L6405D has same ID as MX25L6406 */ |
| 1388 | static struct w25q_range mx25l6405d_ranges[] = { |
| 1389 | { X, 0, 0, {0, 0} }, /* none */ |
| 1390 | { X, 0, 0x1, {0x7e0000, 2 * 64 * 1024} }, /* blocks 126-127 */ |
| 1391 | { X, 0, 0x2, {0x7c0000, 4 * 64 * 1024} }, /* blocks 124-127 */ |
| 1392 | { X, 0, 0x3, {0x780000, 8 * 64 * 1024} }, /* blocks 120-127 */ |
| 1393 | { X, 0, 0x4, {0x700000, 16 * 64 * 1024} }, /* blocks 112-127 */ |
| 1394 | { X, 0, 0x5, {0x600000, 32 * 64 * 1024} }, /* blocks 96-127 */ |
| 1395 | { X, 0, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 1396 | { X, 0, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */ |
| 1397 | |
| 1398 | { X, 1, 0x0, {0x000000, 8192 * 1024} }, |
| 1399 | { X, 1, 0x1, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 1400 | { X, 1, 0x2, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */ |
| 1401 | { X, 1, 0x3, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */ |
| 1402 | { X, 1, 0x4, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */ |
| 1403 | { X, 1, 0x5, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */ |
| 1404 | { X, 1, 0x6, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */ |
| 1405 | { X, 1, 0x7, {0x000000, 64 * 128 * 1024} }, /* blocks 0-127 */ |
| 1406 | }; |
| 1407 | #endif |
| 1408 | |
| 1409 | /* FIXME: MX25L6406 has same ID as MX25L6405D */ |
| 1410 | struct generic_range mx25l6406e_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1411 | { { }, 0, {0, 0} }, /* none */ |
| 1412 | { { }, 0x1, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 1413 | { { }, 0x2, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
| 1414 | { { }, 0x3, {0x7a0000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 1415 | { { }, 0x4, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 1416 | { { }, 0x5, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 1417 | { { }, 0x6, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1418 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1419 | { { }, 0x7, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1420 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1421 | { { }, 0x9, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 1422 | { { }, 0xa, {0x000000, 64 * 96 * 1024} }, /* blocks 0-95 */ |
| 1423 | { { }, 0xb, {0x000000, 64 * 112 * 1024} }, /* blocks 0-111 */ |
| 1424 | { { }, 0xc, {0x000000, 64 * 120 * 1024} }, /* blocks 0-119 */ |
| 1425 | { { }, 0xd, {0x000000, 64 * 124 * 1024} }, /* blocks 0-123 */ |
| 1426 | { { }, 0xe, {0x000000, 64 * 126 * 1024} }, /* blocks 0-125 */ |
| 1427 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1428 | }; |
| 1429 | |
| 1430 | static struct generic_wp mx25l6406e_wp = { |
| 1431 | .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 }, |
| 1432 | .ranges = &mx25l6406e_ranges[0], |
| 1433 | }; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1434 | |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1435 | struct generic_range mx25l6495f_tb0_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1436 | { { }, 0, {0, 0} }, /* none */ |
| 1437 | { { }, 0x1, {0x7f0000, 64 * 1 * 1024} }, /* block 127 */ |
| 1438 | { { }, 0x2, {0x7e0000, 64 * 2 * 1024} }, /* blocks 126-127 */ |
| 1439 | { { }, 0x3, {0x7c0000, 64 * 4 * 1024} }, /* blocks 124-127 */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1440 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1441 | { { }, 0x4, {0x780000, 64 * 8 * 1024} }, /* blocks 120-127 */ |
| 1442 | { { }, 0x5, {0x700000, 64 * 16 * 1024} }, /* blocks 112-127 */ |
| 1443 | { { }, 0x6, {0x600000, 64 * 32 * 1024} }, /* blocks 96-127 */ |
| 1444 | { { }, 0x7, {0x400000, 64 * 64 * 1024} }, /* blocks 64-127 */ |
| 1445 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1446 | { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1447 | { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1448 | { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1449 | { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1450 | { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1451 | { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1452 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1453 | }; |
| 1454 | |
| 1455 | struct generic_range mx25l6495f_tb1_ranges[] = { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1456 | { { }, 0, {0, 0} }, /* none */ |
| 1457 | { { }, 0x1, {0x000000, 64 * 1 * 1024} }, /* block 0 */ |
| 1458 | { { }, 0x2, {0x000000, 64 * 2 * 1024} }, /* blocks 0-1 */ |
| 1459 | { { }, 0x3, {0x000000, 64 * 4 * 1024} }, /* blocks 0-3 */ |
| 1460 | { { }, 0x4, {0x000000, 64 * 8 * 1024} }, /* blocks 0-7 */ |
| 1461 | { { }, 0x5, {0x000000, 64 * 16 * 1024} }, /* blocks 0-15 */ |
| 1462 | { { }, 0x6, {0x000000, 64 * 32 * 1024} }, /* blocks 0-31 */ |
| 1463 | { { }, 0x7, {0x000000, 64 * 64 * 1024} }, /* blocks 0-63 */ |
| 1464 | { { }, 0x8, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1465 | { { }, 0x9, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1466 | { { }, 0xa, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1467 | { { }, 0xb, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1468 | { { }, 0xc, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1469 | { { }, 0xd, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1470 | { { }, 0xe, {0x000000, 64 * 128 * 1024} }, /* all */ |
| 1471 | { { }, 0xf, {0x000000, 64 * 128 * 1024} }, /* all */ |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1472 | }; |
| 1473 | |
| 1474 | static struct generic_wp mx25l6495f_wp = { |
| 1475 | .sr1 = { .bp0_pos = 2, .bp_bits = 4, .srp_pos = 7 }, |
| 1476 | }; |
| 1477 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1478 | struct generic_range s25fs128s_ranges[] = { |
| 1479 | { { .tb = 1 }, 0, {0, 0} }, /* none */ |
| 1480 | { { .tb = 1 }, 0x1, {0x000000, 256 * 1024} }, /* lower 64th */ |
| 1481 | { { .tb = 1 }, 0x2, {0x000000, 512 * 1024} }, /* lower 32nd */ |
| 1482 | { { .tb = 1 }, 0x3, {0x000000, 1024 * 1024} }, /* lower 16th */ |
| 1483 | { { .tb = 1 }, 0x4, {0x000000, 2048 * 1024} }, /* lower 8th */ |
| 1484 | { { .tb = 1 }, 0x5, {0x000000, 4096 * 1024} }, /* lower 4th */ |
| 1485 | { { .tb = 1 }, 0x6, {0x000000, 8192 * 1024} }, /* lower half */ |
| 1486 | { { .tb = 1 }, 0x7, {0x000000, 16384 * 1024} }, /* all */ |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1487 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1488 | { { .tb = 0 }, 0, {0, 0} }, /* none */ |
| 1489 | { { .tb = 0 }, 0x1, {0xfc0000, 256 * 1024} }, /* upper 64th */ |
| 1490 | { { .tb = 0 }, 0x2, {0xf80000, 512 * 1024} }, /* upper 32nd */ |
| 1491 | { { .tb = 0 }, 0x3, {0xf00000, 1024 * 1024} }, /* upper 16th */ |
| 1492 | { { .tb = 0 }, 0x4, {0xe00000, 2048 * 1024} }, /* upper 8th */ |
| 1493 | { { .tb = 0 }, 0x5, {0xc00000, 4096 * 1024} }, /* upper 4th */ |
| 1494 | { { .tb = 0 }, 0x6, {0x800000, 8192 * 1024} }, /* upper half */ |
| 1495 | { { .tb = 0 }, 0x7, {0x000000, 16384 * 1024} }, /* all */ |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1496 | }; |
| 1497 | |
| 1498 | static struct generic_wp s25fs128s_wp = { |
| 1499 | .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 }, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1500 | .get_modifier_bits = s25f_get_modifier_bits, |
| 1501 | .set_modifier_bits = s25f_set_modifier_bits, |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1502 | }; |
| 1503 | |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1504 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1505 | struct generic_range s25fl256s_ranges[] = { |
| 1506 | { { .tb = 1 }, 0, {0, 0} }, /* none */ |
| 1507 | { { .tb = 1 }, 0x1, {0x000000, 512 * 1024} }, /* lower 64th */ |
| 1508 | { { .tb = 1 }, 0x2, {0x000000, 1024 * 1024} }, /* lower 32nd */ |
| 1509 | { { .tb = 1 }, 0x3, {0x000000, 2048 * 1024} }, /* lower 16th */ |
| 1510 | { { .tb = 1 }, 0x4, {0x000000, 4096 * 1024} }, /* lower 8th */ |
| 1511 | { { .tb = 1 }, 0x5, {0x000000, 8192 * 1024} }, /* lower 4th */ |
| 1512 | { { .tb = 1 }, 0x6, {0x000000, 16384 * 1024} }, /* lower half */ |
| 1513 | { { .tb = 1 }, 0x7, {0x000000, 32768 * 1024} }, /* all */ |
| 1514 | |
| 1515 | { { .tb = 0 }, 0, {0, 0} }, /* none */ |
| 1516 | { { .tb = 0 }, 0x1, {0x1f80000, 512 * 1024} }, /* upper 64th */ |
| 1517 | { { .tb = 0 }, 0x2, {0x1f00000, 1024 * 1024} }, /* upper 32nd */ |
| 1518 | { { .tb = 0 }, 0x3, {0x1e00000, 2048 * 1024} }, /* upper 16th */ |
| 1519 | { { .tb = 0 }, 0x4, {0x1c00000, 4096 * 1024} }, /* upper 8th */ |
| 1520 | { { .tb = 0 }, 0x5, {0x1800000, 8192 * 1024} }, /* upper 4th */ |
| 1521 | { { .tb = 0 }, 0x6, {0x1000000, 16384 * 1024} }, /* upper half */ |
| 1522 | { { .tb = 0 }, 0x7, {0x000000, 32768 * 1024} }, /* all */ |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1523 | }; |
| 1524 | |
| 1525 | static struct generic_wp s25fl256s_wp = { |
| 1526 | .sr1 = { .bp0_pos = 2, .bp_bits = 3, .srp_pos = 7 }, |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1527 | .get_modifier_bits = s25f_get_modifier_bits, |
| 1528 | .set_modifier_bits = s25f_set_modifier_bits, |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1529 | }; |
| 1530 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1531 | /* Given a flash chip, this function returns its writeprotect info. */ |
| 1532 | static int generic_range_table(const struct flashchip *flash, |
| 1533 | struct generic_wp **wp, |
| 1534 | int *num_entries) |
| 1535 | { |
| 1536 | *wp = NULL; |
| 1537 | *num_entries = 0; |
| 1538 | |
| 1539 | switch (flash->manufacture_id) { |
David Hendricks | af3944a | 2014-07-28 18:37:40 -0700 | [diff] [blame] | 1540 | case GIGADEVICE_ID: |
| 1541 | switch(flash->model_id) { |
| 1542 | case GIGADEVICE_GD25Q32: { |
| 1543 | uint8_t sr1 = w25q_read_status_register_2(); |
| 1544 | |
| 1545 | *wp = &gd25q32_wp; |
| 1546 | if (!(sr1 & (1 << 6))) { /* CMP == 0 */ |
| 1547 | (*wp)->ranges = &gd25q32_cmp0_ranges[0]; |
| 1548 | *num_entries = ARRAY_SIZE(gd25q32_cmp0_ranges); |
| 1549 | } else { /* CMP == 1 */ |
| 1550 | (*wp)->ranges = &gd25q32_cmp1_ranges[0]; |
| 1551 | *num_entries = ARRAY_SIZE(gd25q32_cmp1_ranges); |
| 1552 | } |
| 1553 | |
| 1554 | break; |
| 1555 | /* TODO(shawnn): add support for other GD parts */ |
| 1556 | } |
| 1557 | default: |
| 1558 | msg_cerr("%s() %d: GigaDevice flash chip mismatch" |
| 1559 | " (0x%04x), aborting\n", __func__, __LINE__, |
| 1560 | flash->model_id); |
| 1561 | return -1; |
| 1562 | } |
| 1563 | break; |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1564 | case MACRONIX_ID: |
| 1565 | switch (flash->model_id) { |
| 1566 | case MACRONIX_MX25L6405: |
| 1567 | /* FIXME: MX25L64* chips have mixed capabilities and |
| 1568 | share IDs */ |
| 1569 | *wp = &mx25l6406e_wp; |
| 1570 | *num_entries = ARRAY_SIZE(mx25l6406e_ranges); |
| 1571 | break; |
David Hendricks | c349609 | 2014-11-13 17:20:55 -0800 | [diff] [blame] | 1572 | case MACRONIX_MX25L6495F: { |
| 1573 | uint8_t cr = mx25l_read_config_register(); |
| 1574 | |
| 1575 | *wp = &mx25l6495f_wp; |
| 1576 | if (!(cr & (1 << 3))) { /* T/B == 0 */ |
| 1577 | (*wp)->ranges = &mx25l6495f_tb0_ranges[0]; |
| 1578 | *num_entries = ARRAY_SIZE(mx25l6495f_tb0_ranges); |
| 1579 | } else { /* T/B == 1 */ |
| 1580 | (*wp)->ranges = &mx25l6495f_tb1_ranges[0]; |
| 1581 | *num_entries = ARRAY_SIZE(mx25l6495f_tb1_ranges); |
| 1582 | } |
| 1583 | break; |
| 1584 | } |
David Hendricks | 83541d3 | 2014-07-15 20:58:21 -0700 | [diff] [blame] | 1585 | default: |
| 1586 | msg_cerr("%s():%d: MXIC flash chip mismatch (0x%04x)" |
| 1587 | ", aborting\n", __func__, __LINE__, |
| 1588 | flash->model_id); |
| 1589 | return -1; |
| 1590 | } |
| 1591 | break; |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1592 | case SPANSION_ID: |
| 1593 | switch (flash->model_id) { |
| 1594 | case SPANSION_S25FS128S_L: |
| 1595 | case SPANSION_S25FS128S_S: { |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1596 | *wp = &s25fs128s_wp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1597 | (*wp)->ranges = s25fs128s_ranges; |
| 1598 | *num_entries = ARRAY_SIZE(s25fs128s_ranges); |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1599 | break; |
| 1600 | } |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1601 | case SPANSION_S25FL256S_UL: |
| 1602 | case SPANSION_S25FL256S_US: { |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1603 | *wp = &s25fl256s_wp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1604 | (*wp)->ranges = s25fl256s_ranges; |
| 1605 | *num_entries = ARRAY_SIZE(s25fl256s_ranges); |
David Hendricks | c694bb8 | 2015-02-25 14:52:17 -0800 | [diff] [blame] | 1606 | break; |
| 1607 | } |
David Hendricks | a988485 | 2014-12-11 15:31:12 -0800 | [diff] [blame] | 1608 | default: |
| 1609 | msg_cerr("%s():%d Spansion flash chip mismatch (0x%04x)" |
| 1610 | ", aborting\n", __func__, __LINE__, flash->model_id); |
| 1611 | return -1; |
| 1612 | } |
| 1613 | break; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1614 | default: |
| 1615 | msg_cerr("%s: flash vendor (0x%x) not found, aborting\n", |
| 1616 | __func__, flash->manufacture_id); |
| 1617 | return -1; |
| 1618 | } |
| 1619 | |
| 1620 | return 0; |
| 1621 | } |
| 1622 | |
| 1623 | /* Given a [start, len], this function finds a block protect bit combination |
| 1624 | * (if possible) and sets the corresponding bits in "status". Remaining bits |
| 1625 | * are preserved. */ |
| 1626 | static int generic_range_to_status(const struct flashchip *flash, |
| 1627 | unsigned int start, unsigned int len, |
| 1628 | uint8_t *status) |
| 1629 | { |
| 1630 | struct generic_wp *wp; |
| 1631 | struct generic_range *r; |
| 1632 | int i, range_found = 0, num_entries; |
| 1633 | uint8_t bp_mask; |
| 1634 | |
| 1635 | if (generic_range_table(flash, &wp, &num_entries)) |
| 1636 | return -1; |
| 1637 | |
| 1638 | bp_mask = ((1 << (wp->sr1.bp0_pos + wp->sr1.bp_bits)) - 1) - \ |
| 1639 | ((1 << wp->sr1.bp0_pos) - 1); |
| 1640 | |
| 1641 | for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) { |
| 1642 | msg_cspew("comparing range 0x%x 0x%x / 0x%x 0x%x\n", |
| 1643 | start, len, r->range.start, r->range.len); |
| 1644 | if ((start == r->range.start) && (len == r->range.len)) { |
| 1645 | *status &= ~(bp_mask); |
| 1646 | *status |= r->bp << (wp->sr1.bp0_pos); |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1647 | |
| 1648 | if (wp->set_modifier_bits) { |
| 1649 | if (wp->set_modifier_bits(flash, &r->m) < 0) { |
| 1650 | msg_cerr("error setting modifier " |
| 1651 | "bits for range.\n"); |
| 1652 | return -1; |
| 1653 | } |
| 1654 | } |
| 1655 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1656 | range_found = 1; |
| 1657 | break; |
| 1658 | } |
| 1659 | } |
| 1660 | |
| 1661 | if (!range_found) { |
| 1662 | msg_cerr("matching range not found\n"); |
| 1663 | return -1; |
| 1664 | } |
| 1665 | return 0; |
| 1666 | } |
| 1667 | |
| 1668 | static int generic_status_to_range(const struct flashchip *flash, |
| 1669 | const uint8_t sr1, unsigned int *start, unsigned int *len) |
| 1670 | { |
| 1671 | struct generic_wp *wp; |
| 1672 | struct generic_range *r; |
Duncan Laurie | 04ca117 | 2015-03-12 09:25:34 -0700 | [diff] [blame] | 1673 | int num_entries, i, status_found = 0; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1674 | uint8_t sr1_bp; |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1675 | struct generic_modifier_bits m; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1676 | |
| 1677 | if (generic_range_table(flash, &wp, &num_entries)) |
| 1678 | return -1; |
| 1679 | |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1680 | /* modifier bits may be compared more than once, so get them here */ |
| 1681 | if (wp->get_modifier_bits) { |
| 1682 | if (wp->get_modifier_bits(flash, &m) < 0) |
| 1683 | return -1; |
| 1684 | } |
| 1685 | |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1686 | sr1_bp = (sr1 >> wp->sr1.bp0_pos) & ((1 << wp->sr1.bp_bits) - 1); |
| 1687 | |
| 1688 | for (i = 0, r = &wp->ranges[0]; i < num_entries; i++, r++) { |
David Hendricks | 148a4bf | 2015-03-13 21:02:42 -0700 | [diff] [blame] | 1689 | if (wp->get_modifier_bits) { |
| 1690 | if (memcmp(&m, &r->m, sizeof(m))) |
| 1691 | continue; |
| 1692 | } |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1693 | msg_cspew("comparing 0x%02x 0x%02x\n", sr1_bp, r->bp); |
| 1694 | if (sr1_bp == r->bp) { |
| 1695 | *start = r->range.start; |
| 1696 | *len = r->range.len; |
| 1697 | status_found = 1; |
| 1698 | break; |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | if (!status_found) { |
| 1703 | msg_cerr("matching status not found\n"); |
| 1704 | return -1; |
| 1705 | } |
| 1706 | return 0; |
| 1707 | } |
| 1708 | |
| 1709 | /* Given a [start, len], this function calls generic_range_to_status() to |
| 1710 | * convert it to flash-chip-specific range bits, then sets into status register. |
| 1711 | */ |
| 1712 | static int generic_set_range(const struct flashchip *flash, |
| 1713 | unsigned int start, unsigned int len) |
| 1714 | { |
| 1715 | uint8_t status, expected; |
| 1716 | |
| 1717 | status = spi_read_status_register(); |
| 1718 | msg_cdbg("%s: old status: 0x%02x\n", __func__, status); |
| 1719 | |
| 1720 | expected = status; /* preserve non-bp bits */ |
| 1721 | if (generic_range_to_status(flash, start, len, &expected)) |
| 1722 | return -1; |
| 1723 | |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 1724 | spi_write_status_register(flash, expected); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1725 | |
| 1726 | status = spi_read_status_register(); |
| 1727 | msg_cdbg("%s: new status: 0x%02x\n", __func__, status); |
| 1728 | if (status != expected) { |
| 1729 | msg_cerr("expected=0x%02x, but actual=0x%02x.\n", |
| 1730 | expected, status); |
| 1731 | return 1; |
| 1732 | } |
| 1733 | |
| 1734 | return 0; |
| 1735 | } |
| 1736 | |
| 1737 | /* Set/clear the status regsiter write protect bit in SR1. */ |
| 1738 | static int generic_set_srp0(const struct flashchip *flash, int enable) |
| 1739 | { |
| 1740 | uint8_t status, expected; |
| 1741 | struct generic_wp *wp; |
| 1742 | int num_entries; |
| 1743 | |
| 1744 | if (generic_range_table(flash, &wp, &num_entries)) |
| 1745 | return -1; |
| 1746 | |
| 1747 | expected = spi_read_status_register(); |
| 1748 | msg_cdbg("%s: old status: 0x%02x\n", __func__, expected); |
| 1749 | |
| 1750 | if (enable) |
| 1751 | expected |= 1 << wp->sr1.srp_pos; |
| 1752 | else |
| 1753 | expected &= ~(1 << wp->sr1.srp_pos); |
| 1754 | |
David Hendricks | 6082404 | 2014-12-11 17:22:06 -0800 | [diff] [blame] | 1755 | spi_write_status_register(flash, expected); |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1756 | |
| 1757 | status = spi_read_status_register(); |
| 1758 | msg_cdbg("%s: new status: 0x%02x\n", __func__, status); |
| 1759 | if (status != expected) |
| 1760 | return -1; |
| 1761 | |
| 1762 | return 0; |
| 1763 | } |
| 1764 | |
| 1765 | static int generic_enable_writeprotect(const struct flashchip *flash, |
| 1766 | enum wp_mode wp_mode) |
| 1767 | { |
| 1768 | int ret; |
| 1769 | |
| 1770 | switch (wp_mode) { |
| 1771 | case WP_MODE_HARDWARE: |
| 1772 | ret = generic_set_srp0(flash, 1); |
| 1773 | break; |
| 1774 | default: |
| 1775 | msg_cerr("%s(): unsupported write-protect mode\n", __func__); |
| 1776 | return 1; |
| 1777 | } |
| 1778 | |
| 1779 | if (ret) |
| 1780 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1781 | return ret; |
| 1782 | } |
| 1783 | |
| 1784 | static int generic_disable_writeprotect(const struct flashchip *flash) |
| 1785 | { |
| 1786 | int ret; |
| 1787 | |
| 1788 | ret = generic_set_srp0(flash, 0); |
| 1789 | if (ret) |
| 1790 | msg_cerr("%s(): error=%d.\n", __func__, ret); |
| 1791 | return ret; |
| 1792 | } |
| 1793 | |
| 1794 | static int generic_list_ranges(const struct flashchip *flash) |
| 1795 | { |
| 1796 | struct generic_wp *wp; |
| 1797 | struct generic_range *r; |
| 1798 | int i, num_entries; |
| 1799 | |
| 1800 | if (generic_range_table(flash, &wp, &num_entries)) |
| 1801 | return -1; |
| 1802 | |
| 1803 | r = &wp->ranges[0]; |
| 1804 | for (i = 0; i < num_entries; i++) { |
| 1805 | msg_cinfo("start: 0x%06x, length: 0x%06x\n", |
| 1806 | r->range.start, r->range.len); |
| 1807 | r++; |
| 1808 | } |
| 1809 | |
| 1810 | return 0; |
| 1811 | } |
| 1812 | |
| 1813 | static int generic_wp_status(const struct flashchip *flash) |
| 1814 | { |
| 1815 | uint8_t sr1; |
| 1816 | unsigned int start, len; |
| 1817 | int ret = 0; |
| 1818 | struct generic_wp *wp; |
David Hendricks | e0512a7 | 2014-07-15 20:30:47 -0700 | [diff] [blame] | 1819 | int num_entries, wp_en; |
| 1820 | |
| 1821 | if (generic_range_table(flash, &wp, &num_entries)) |
| 1822 | return -1; |
| 1823 | |
| 1824 | sr1 = spi_read_status_register(); |
| 1825 | wp_en = (sr1 >> wp->sr1.srp_pos) & 1; |
| 1826 | |
| 1827 | msg_cinfo("WP: status: 0x%04x\n", sr1); |
| 1828 | msg_cinfo("WP: status.srp0: %x\n", wp_en); |
| 1829 | /* FIXME: SRP1 is not really generic, but we probably should print |
| 1830 | * it anyway to have consistent output. #legacycruft */ |
| 1831 | msg_cinfo("WP: status.srp1: %x\n", 0); |
| 1832 | msg_cinfo("WP: write protect is %s.\n", |
| 1833 | wp_en ? "enabled" : "disabled"); |
| 1834 | |
| 1835 | msg_cinfo("WP: write protect range: "); |
| 1836 | if (generic_status_to_range(flash, sr1, &start, &len)) { |
| 1837 | msg_cinfo("(cannot resolve the range)\n"); |
| 1838 | ret = -1; |
| 1839 | } else { |
| 1840 | msg_cinfo("start=0x%08x, len=0x%08x\n", start, len); |
| 1841 | } |
| 1842 | |
| 1843 | return ret; |
| 1844 | } |
| 1845 | |
| 1846 | struct wp wp_generic = { |
| 1847 | .list_ranges = generic_list_ranges, |
| 1848 | .set_range = generic_set_range, |
| 1849 | .enable = generic_enable_writeprotect, |
| 1850 | .disable = generic_disable_writeprotect, |
| 1851 | .wp_status = generic_wp_status, |
| 1852 | }; |