stepan | 5c3f138 | 2007-02-06 19:47:50 +0000 | [diff] [blame] | 1 | /* |
uwe | b25f1ea | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
stepan | 5c3f138 | 2007-02-06 19:47:50 +0000 | [diff] [blame] | 3 | * |
uwe | 555dd97 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com> |
stepan | 6d42c0f | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 6 | * Copyright (C) 2005-2009 coresystems GmbH |
hailfinger | 77c5d93 | 2009-06-15 12:10:57 +0000 | [diff] [blame] | 7 | * Copyright (C) 2006-2009 Carl-Daniel Hailfinger |
stepan | 5c3f138 | 2007-02-06 19:47:50 +0000 | [diff] [blame] | 8 | * |
uwe | b25f1ea | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
stepan | 5c3f138 | 2007-02-06 19:47:50 +0000 | [diff] [blame] | 13 | * |
uwe | b25f1ea | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
stepan | 5c3f138 | 2007-02-06 19:47:50 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
rminnich | 8d3ff91 | 2003-10-25 17:01:29 +0000 | [diff] [blame] | 20 | #ifndef __FLASH_H__ |
| 21 | #define __FLASH_H__ 1 |
| 22 | |
ollie | 6a60099 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 23 | #include <stdint.h> |
hailfinger | d43a4e3 | 2010-06-03 00:49:50 +0000 | [diff] [blame] | 24 | #include <stddef.h> |
Edward O'Callaghan | a74ffcd | 2019-06-17 14:59:55 +1000 | [diff] [blame] | 25 | #include <stdbool.h> |
Pavol Marko | ef4c6e8 | 2019-09-09 12:43:44 +0000 | [diff] [blame] | 26 | #ifdef _WIN32 |
oxygene | 3ad3b33 | 2010-01-06 22:14:39 +0000 | [diff] [blame] | 27 | #include <windows.h> |
| 28 | #undef min |
| 29 | #undef max |
| 30 | #endif |
hailfinger | e1f062f | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 31 | |
Stefan Reinauer | e64faaf | 2011-05-03 18:03:25 -0700 | [diff] [blame] | 32 | /* Are timers broken? */ |
| 33 | extern int broken_timer; |
| 34 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 35 | struct flashctx; /* forward declare */ |
hailfinger | f294fa2 | 2010-09-25 22:53:44 +0000 | [diff] [blame] | 36 | #define ERROR_PTR ((void*)-1) |
| 37 | |
hailfinger | ee9ee13 | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 38 | /* Error codes */ |
| 39 | #define TIMEOUT_ERROR -101 |
| 40 | |
Edward O'Callaghan | 9b520dd | 2019-05-01 21:47:21 -0400 | [diff] [blame] | 41 | #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) |
| 42 | |
Edward O'Callaghan | 1a3fd13 | 2019-06-04 14:18:55 +1000 | [diff] [blame] | 43 | /* for verify_it variable in flashrom.c and cli_classic.c */ |
Louis Yung-Chieh Lo | 5d95f04 | 2011-09-01 17:33:06 +0800 | [diff] [blame] | 44 | enum { |
| 45 | VERIFY_OFF = 0, |
| 46 | VERIFY_FULL, |
| 47 | VERIFY_PARTIAL, |
| 48 | }; |
| 49 | |
Pavol Marko | ef4c6e8 | 2019-09-09 12:43:44 +0000 | [diff] [blame] | 50 | typedef unsigned long chipaddr; |
| 51 | |
David Hendricks | 93784b4 | 2016-08-09 17:00:38 -0700 | [diff] [blame] | 52 | int register_shutdown(int (*function) (void *data), void *data); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 53 | #define CHIP_RESTORE_CALLBACK int (*func) (struct flashctx *flash, uint8_t status) |
David Hendricks | bf36f09 | 2010-11-02 23:39:29 -0700 | [diff] [blame] | 54 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 55 | int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashctx *flash, uint8_t status); |
uwe | abe92a5 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 56 | void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, |
| 57 | size_t len); |
| 58 | void programmer_unmap_flash_region(void *virt_addr, size_t len); |
hailfinger | e5829f6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 59 | void programmer_delay(int usecs); |
hailfinger | ba3761a | 2009-03-05 19:24:22 +0000 | [diff] [blame] | 60 | |
uwe | 16f9909 | 2008-03-12 11:54:51 +0000 | [diff] [blame] | 61 | #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) |
| 62 | |
hailfinger | 4016746 | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 63 | enum chipbustype { |
hailfinger | e1e41ea | 2011-07-27 07:13:06 +0000 | [diff] [blame] | 64 | BUS_NONE = 0, |
| 65 | BUS_PARALLEL = 1 << 0, |
| 66 | BUS_LPC = 1 << 1, |
| 67 | BUS_FWH = 1 << 2, |
| 68 | BUS_SPI = 1 << 3, |
hailfinger | fe7cd9e | 2011-11-04 21:35:26 +0000 | [diff] [blame] | 69 | BUS_PROG = 1 << 4, |
hailfinger | e1e41ea | 2011-07-27 07:13:06 +0000 | [diff] [blame] | 70 | BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, |
hailfinger | 4016746 | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 71 | }; |
| 72 | |
David Hendricks | 80f62d2 | 2010-10-08 11:09:35 -0700 | [diff] [blame] | 73 | /* used to select bus which target chip resides */ |
| 74 | extern enum chipbustype target_bus; |
| 75 | |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 76 | /* |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 77 | * The following enum defines possible write granularities of flash chips. These tend to reflect the properties |
| 78 | * of the actual hardware not necesserily the write function(s) defined by the respective struct flashchip. |
| 79 | * The latter might (and should) be more precisely specified, e.g. they might bail out early if their execution |
| 80 | * would result in undefined chip contents. |
| 81 | */ |
| 82 | enum write_granularity { |
| 83 | /* We assume 256 byte granularity by default. */ |
| 84 | write_gran_256bytes = 0,/* If less than 256 bytes are written, the unwritten bytes are undefined. */ |
| 85 | write_gran_1bit, /* Each bit can be cleared individually. */ |
| 86 | write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause |
| 87 | * its contents to be either undefined or to stay unchanged. */ |
| 88 | write_gran_128bytes, /* If less than 128 bytes are written, the unwritten bytes are undefined. */ |
| 89 | write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ |
| 90 | write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ |
| 91 | write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ |
| 92 | write_gran_1024bytes, /* If less than 1024 bytes are written, the unwritten bytes are undefined. */ |
| 93 | write_gran_1056bytes, /* If less than 1056 bytes are written, the unwritten bytes are undefined. */ |
| 94 | write_gran_1byte_implicit_erase, /* EEPROMs and other chips with implicit erase and 1-byte writes. */ |
| 95 | }; |
| 96 | |
| 97 | /* |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 98 | * How many different contiguous runs of erase blocks with one size each do |
| 99 | * we have for a given erase function? |
| 100 | */ |
| 101 | #define NUM_ERASEREGIONS 5 |
| 102 | |
| 103 | /* |
| 104 | * How many different erase functions do we have per chip? |
hailfinger | c33d473 | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 105 | * Atmel AT25FS010 has 6 different functions. |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 106 | */ |
hailfinger | c33d473 | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 107 | #define NUM_ERASEFUNCTIONS 6 |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 108 | |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 109 | /* Feature bits used for non-SPI only */ |
hailfinger | 80dea31 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 110 | #define FEATURE_REGISTERMAP (1 << 0) |
| 111 | #define FEATURE_BYTEWRITES (1 << 1) |
snelson | c685534 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 112 | #define FEATURE_LONG_RESET (0 << 4) |
| 113 | #define FEATURE_SHORT_RESET (1 << 4) |
| 114 | #define FEATURE_EITHER_RESET FEATURE_LONG_RESET |
hailfinger | b07dc97 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 115 | #define FEATURE_RESET_MASK (FEATURE_LONG_RESET | FEATURE_SHORT_RESET) |
hailfinger | 80dea31 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 116 | #define FEATURE_ADDR_FULL (0 << 2) |
| 117 | #define FEATURE_ADDR_MASK (3 << 2) |
snelson | c685534 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 118 | #define FEATURE_ADDR_2AA (1 << 2) |
| 119 | #define FEATURE_ADDR_AAA (2 << 2) |
mkarcher | 9ded5fe | 2010-04-03 10:27:08 +0000 | [diff] [blame] | 120 | #define FEATURE_ADDR_SHIFTED (1 << 5) |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 121 | /* Feature bits used for SPI only */ |
hailfinger | c33d473 | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 122 | #define FEATURE_WRSR_EWSR (1 << 6) |
| 123 | #define FEATURE_WRSR_WREN (1 << 7) |
| 124 | #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) |
David Hendricks | ff55cf6 | 2016-08-30 11:22:31 -0700 | [diff] [blame] | 125 | #define FEATURE_OTP (1 << 8) |
Alan Green | dbeec2b | 2019-09-16 14:36:52 +1000 | [diff] [blame] | 126 | #define FEATURE_ERASED_ZERO (1 << 9) |
Edward O'Callaghan | 2748621 | 2019-07-26 21:59:55 +1000 | [diff] [blame] | 127 | #define FEATURE_NO_ERASE (1 << 10) |
| 128 | #define FEATURE_4BA_ENTER (1 << 11) |
| 129 | #define FEATURE_4BA_ENTER_WREN (1 << 12) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN */ |
| 130 | #define FEATURE_4BA_EXT_ADDR (1 << 13) /**< Regular 3-byte operations can be used by writing the most |
Edward O'Callaghan | a74ffcd | 2019-06-17 14:59:55 +1000 | [diff] [blame] | 131 | significant address byte into an extended address register. */ |
Edward O'Callaghan | 2748621 | 2019-07-26 21:59:55 +1000 | [diff] [blame] | 132 | #define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */ |
| 133 | #define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */ |
| 134 | #define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */ |
Edward O'Callaghan | 3d0cbd4 | 2019-06-24 15:37:01 +1000 | [diff] [blame] | 135 | /* 4BA Shorthands */ |
| 136 | #define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE) |
| 137 | #define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE) |
| 138 | #define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE) |
Simon Glass | 4c21413 | 2013-07-16 10:09:28 -0600 | [diff] [blame] | 139 | |
David Hendricks | 8c08421 | 2015-11-17 22:29:36 -0800 | [diff] [blame] | 140 | struct voltage_range { |
| 141 | uint16_t min, max; |
| 142 | }; |
| 143 | |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 144 | enum test_state { |
| 145 | OK = 0, |
| 146 | NT = 1, /* Not tested */ |
| 147 | BAD, /* Known to not work */ |
| 148 | DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */ |
| 149 | NA, /* Not applicable (e.g. write support on ROM chips) */ |
| 150 | }; |
| 151 | |
Alan Green | 5447a45 | 2019-07-30 13:57:52 +1000 | [diff] [blame] | 152 | #define TEST_UNTESTED (struct tested){ .probe = NT, .read = NT, .erase = NT, .write = NT } |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 153 | |
Alan Green | 5447a45 | 2019-07-30 13:57:52 +1000 | [diff] [blame] | 154 | #define TEST_OK_PROBE (struct tested){ .probe = OK, .read = NT, .erase = NT, .write = NT } |
| 155 | #define TEST_OK_PR (struct tested){ .probe = OK, .read = OK, .erase = NT, .write = NT } |
| 156 | #define TEST_OK_PRE (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = NT } |
| 157 | #define TEST_OK_PREW (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = OK } |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 158 | |
Alan Green | 5447a45 | 2019-07-30 13:57:52 +1000 | [diff] [blame] | 159 | #define TEST_BAD_PROBE (struct tested){ .probe = BAD, .read = NT, .erase = NT, .write = NT } |
| 160 | #define TEST_BAD_PR (struct tested){ .probe = BAD, .read = BAD, .erase = NT, .write = NT } |
| 161 | #define TEST_BAD_PRE (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = NT } |
| 162 | #define TEST_BAD_PREW (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD } |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 163 | |
rminnich | 8d3ff91 | 2003-10-25 17:01:29 +0000 | [diff] [blame] | 164 | struct flashchip { |
uwe | dfcd15f | 2008-03-14 23:55:58 +0000 | [diff] [blame] | 165 | const char *vendor; |
uwe | 6ed6d95 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 166 | const char *name; |
hailfinger | 4016746 | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 167 | |
| 168 | enum chipbustype bustype; |
| 169 | |
uwe | fa98ca1 | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 170 | /* |
| 171 | * With 32bit manufacture_id and model_id we can cover IDs up to |
hailfinger | 428f201 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 172 | * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's |
| 173 | * Identification code. |
| 174 | */ |
| 175 | uint32_t manufacture_id; |
| 176 | uint32_t model_id; |
rminnich | 8d3ff91 | 2003-10-25 17:01:29 +0000 | [diff] [blame] | 177 | |
stefanct | 707f13b | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 178 | /* Total chip size in kilobytes */ |
stefanct | c5eb8a9 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 179 | unsigned int total_size; |
stefanct | 707f13b | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 180 | /* Chip page size in bytes */ |
stefanct | c5eb8a9 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 181 | unsigned int page_size; |
snelson | 63133f9 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 182 | int feature_bits; |
rminnich | 8d3ff91 | 2003-10-25 17:01:29 +0000 | [diff] [blame] | 183 | |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 184 | /* Indicate how well flashrom supports different operations of this flash chip. */ |
| 185 | struct tested { |
| 186 | enum test_state probe; |
| 187 | enum test_state read; |
| 188 | enum test_state erase; |
| 189 | enum test_state write; |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 190 | } tested; |
stuge | 9cd64bd | 2008-05-03 04:34:37 +0000 | [diff] [blame] | 191 | |
Edward O'Callaghan | cc1d0c9 | 2019-02-24 15:35:07 +1100 | [diff] [blame] | 192 | /* |
| 193 | * Group chips that have common command sets. This should ensure that |
| 194 | * no chip gets confused by a probing command for a very different class |
| 195 | * of chips. |
| 196 | */ |
| 197 | enum { |
| 198 | /* SPI25 is very common. Keep it at zero so we don't have |
| 199 | to specify it for each and every chip in the database.*/ |
| 200 | SPI25 = 0, |
Edward O'Callaghan | a9c8100 | 2019-02-24 15:54:40 +1100 | [diff] [blame] | 201 | SPI_EDI = 1, |
Edward O'Callaghan | cc1d0c9 | 2019-02-24 15:35:07 +1100 | [diff] [blame] | 202 | } spi_cmd_set; |
| 203 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 204 | int (*probe) (struct flashctx *flash); |
hailfinger | d5b3592 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 205 | |
stefanct | c5eb8a9 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 206 | /* Delay after "enter/exit ID mode" commands in microseconds. |
| 207 | * NB: negative values have special meanings, see TIMING_* below. |
| 208 | */ |
| 209 | signed int probe_timing; |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 210 | |
| 211 | /* |
hailfinger | c4fac58 | 2009-12-22 13:04:53 +0000 | [diff] [blame] | 212 | * Erase blocks and associated erase function. Any chip erase function |
| 213 | * is stored as chip-sized virtual block together with said function. |
stefanct | 707f13b | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 214 | * The first one that fits will be chosen. There is currently no way to |
| 215 | * influence that behaviour. For testing just comment out the other |
| 216 | * elements or set the function pointer to NULL. |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 217 | */ |
| 218 | struct block_eraser { |
Patrick Georgi | ac3423f | 2017-02-03 20:58:06 +0100 | [diff] [blame] | 219 | struct eraseblock { |
stefanct | 312d9ff | 2011-06-12 19:47:55 +0000 | [diff] [blame] | 220 | unsigned int size; /* Eraseblock size in bytes */ |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 221 | unsigned int count; /* Number of contiguous blocks with that size */ |
| 222 | } eraseblocks[NUM_ERASEREGIONS]; |
stefanct | 9e6b98a | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 223 | /* a block_erase function should try to erase one block of size |
| 224 | * 'blocklen' at address 'blockaddr' and return 0 on success. */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 225 | int (*block_erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); |
hailfinger | 7df2136 | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 226 | } block_erasers[NUM_ERASEFUNCTIONS]; |
| 227 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 228 | int (*printlock) (struct flashctx *flash); |
| 229 | int (*unlock) (struct flashctx *flash); |
Patrick Georgi | ab8353e | 2017-02-03 18:32:01 +0100 | [diff] [blame] | 230 | int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 231 | int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); |
Edward O'Callaghan | 4fe3a97 | 2019-06-19 16:56:10 +1000 | [diff] [blame] | 232 | int (*set_4ba) (struct flashctx *flash); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 233 | uint8_t (*read_status) (const struct flashctx *flash); |
| 234 | int (*write_status) (const struct flashctx *flash, int status); |
Duncan Laurie | 25a4ca2 | 2019-04-25 12:08:52 -0700 | [diff] [blame] | 235 | int (*check_access) (const struct flashctx *flash, unsigned int start, unsigned int len, int read); |
David Hendricks | 8c08421 | 2015-11-17 22:29:36 -0800 | [diff] [blame] | 236 | struct voltage_range voltage; |
Edward O'Callaghan | 10e63d9 | 2019-06-17 14:12:52 +1000 | [diff] [blame] | 237 | enum write_granularity gran; |
Edward O'Callaghan | 2d00129 | 2019-06-26 14:35:03 +1000 | [diff] [blame] | 238 | |
| 239 | /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */ |
| 240 | uint8_t wrea_override; /**< override opcode for write extended address register */ |
| 241 | |
David Hendricks | f7924d1 | 2010-06-10 21:26:44 -0700 | [diff] [blame] | 242 | struct wp *wp; |
rminnich | 8d3ff91 | 2003-10-25 17:01:29 +0000 | [diff] [blame] | 243 | }; |
| 244 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 245 | /* struct flashctx must always contain struct flashchip at the beginning. */ |
| 246 | struct flashctx { |
Patrick Georgi | f3fa299 | 2017-02-02 16:24:44 +0100 | [diff] [blame] | 247 | struct flashchip *chip; |
| 248 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 249 | chipaddr virtual_memory; |
| 250 | /* Some flash devices have an additional register space. */ |
| 251 | chipaddr virtual_registers; |
Edward O'Callaghan | 20596a8 | 2019-06-13 14:47:03 +1000 | [diff] [blame] | 252 | struct registered_master *mst; |
Edward O'Callaghan | a74ffcd | 2019-06-17 14:59:55 +1000 | [diff] [blame] | 253 | |
| 254 | /* We cache the state of the extended address register (highest byte |
| 255 | * of a 4BA for 3BA instructions) and the state of the 4BA mode here. |
| 256 | * If possible, we enter 4BA mode early. If that fails, we make use |
| 257 | * of the extended address register. |
| 258 | */ |
| 259 | int address_high_byte; |
| 260 | bool in_4ba_mode; |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | |
Simon Glass | 4c21413 | 2013-07-16 10:09:28 -0600 | [diff] [blame] | 264 | /* This is the byte value we expect to see in erased regions of the flash */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 265 | int flash_erase_value(struct flashctx *flash); |
Simon Glass | 4c21413 | 2013-07-16 10:09:28 -0600 | [diff] [blame] | 266 | |
| 267 | /* This is a byte value that indicates that the region is not erased */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 268 | int flash_unerased_value(struct flashctx *flash); |
Simon Glass | 4c21413 | 2013-07-16 10:09:28 -0600 | [diff] [blame] | 269 | |
David Hendricks | 40df5b5 | 2016-12-22 15:36:28 -0800 | [diff] [blame] | 270 | /* Given RDID info, return pointer to entry in flashchips[] */ |
| 271 | const struct flashchip *flash_id_to_entry(uint32_t mfg_id, uint32_t model_id); |
| 272 | |
hailfinger | d5b3592 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 273 | /* Timing used in probe routines. ZERO is -2 to differentiate between an unset |
| 274 | * field and zero delay. |
Simon Glass | 8dc8273 | 2013-07-16 10:13:51 -0600 | [diff] [blame] | 275 | * |
hailfinger | d5b3592 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 276 | * SPI devices will always have zero delay and ignore this field. |
| 277 | */ |
| 278 | #define TIMING_FIXME -1 |
| 279 | /* this is intentionally same value as fixme */ |
| 280 | #define TIMING_IGNORED -1 |
| 281 | #define TIMING_ZERO -2 |
| 282 | |
hailfinger | 48ed3e2 | 2011-05-04 00:39:50 +0000 | [diff] [blame] | 283 | extern const struct flashchip flashchips[]; |
Edward O'Callaghan | 6240c85 | 2019-07-02 15:49:58 +1000 | [diff] [blame] | 284 | extern const unsigned int flashchips_size; |
| 285 | |
Ramya Vijaykumar | e6a7ca8 | 2015-05-12 14:27:29 +0530 | [diff] [blame] | 286 | extern const struct flashchip flashchips_hwseq[]; |
ollie | 6a60099 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 287 | |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 288 | void chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); |
| 289 | void chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr); |
| 290 | void chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr); |
| 291 | void chip_writen(const struct flashctx *flash, uint8_t *buf, chipaddr addr, size_t len); |
| 292 | uint8_t chip_readb(const struct flashctx *flash, const chipaddr addr); |
| 293 | uint16_t chip_readw(const struct flashctx *flash, const chipaddr addr); |
| 294 | uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr); |
| 295 | void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); |
| 296 | |
uwe | 884cc8b | 2009-06-17 12:07:12 +0000 | [diff] [blame] | 297 | /* print.c */ |
hailfinger | a50d60e | 2009-11-17 09:57:34 +0000 | [diff] [blame] | 298 | void print_supported(void); |
hailfinger | a50d60e | 2009-11-17 09:57:34 +0000 | [diff] [blame] | 299 | void print_supported_wiki(void); |
uwe | a3a82c9 | 2009-05-15 17:02:34 +0000 | [diff] [blame] | 300 | |
Edward O'Callaghan | 8dd5792 | 2019-03-15 16:21:34 +1100 | [diff] [blame] | 301 | /* helpers.c */ |
| 302 | uint32_t address_to_bits(uint32_t addr); |
Edward O'Callaghan | 2fc166e | 2019-09-09 00:51:20 +1000 | [diff] [blame] | 303 | unsigned int bitcount(unsigned long a); |
Edward O'Callaghan | d2799ab | 2019-09-09 16:30:31 +1000 | [diff] [blame] | 304 | #undef MIN |
| 305 | #define MIN(a, b) ((a) < (b) ? (a) : (b)) |
| 306 | #undef MAX |
| 307 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) |
Edward O'Callaghan | 8dd5792 | 2019-03-15 16:21:34 +1100 | [diff] [blame] | 308 | int max(int a, int b); |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 309 | int min(int a, int b); |
Edward O'Callaghan | 8dd5792 | 2019-03-15 16:21:34 +1100 | [diff] [blame] | 310 | char *strcat_realloc(char *dest, const char *src); |
| 311 | void tolower_string(char *str); |
| 312 | |
uwe | 4529d20 | 2007-08-23 13:34:59 +0000 | [diff] [blame] | 313 | /* flashrom.c */ |
krause | 2eb7621 | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 314 | extern const char flashrom_version[]; |
hailfinger | 92cd8e3 | 2010-01-07 03:24:05 +0000 | [diff] [blame] | 315 | extern char *chip_to_probe; |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 316 | char *flashbuses_to_text(enum chipbustype bustype); |
| 317 | extern enum chipbustype buses_supported; |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 318 | void map_flash_registers(struct flashctx *flash); |
| 319 | int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); |
| 320 | int erase_flash(struct flashctx *flash); |
Edward O'Callaghan | 20596a8 | 2019-06-13 14:47:03 +1000 | [diff] [blame] | 321 | int probe_flash(struct registered_master *master, int startchip, struct flashctx *fill_flash, int force); |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 322 | int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 323 | int read_flash_to_file(struct flashctx *flash, const char *filename); |
stefanct | 5270028 | 2011-06-26 17:38:17 +0000 | [diff] [blame] | 324 | char *extract_param(char **haystack, const char *needle, const char *delim); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 325 | int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); |
hailfinger | 92cd8e3 | 2010-01-07 03:24:05 +0000 | [diff] [blame] | 326 | void print_version(void); |
Souvik Ghosh | 3c963a4 | 2016-07-19 18:48:15 -0700 | [diff] [blame] | 327 | void print_buildinfo(void); |
hailfinger | 74819ad | 2010-05-15 15:04:37 +0000 | [diff] [blame] | 328 | void print_banner(void); |
hailfinger | f79d171 | 2010-10-06 23:48:34 +0000 | [diff] [blame] | 329 | void list_programmers_linebreak(int startcol, int cols, int paren); |
hailfinger | 92cd8e3 | 2010-01-07 03:24:05 +0000 | [diff] [blame] | 330 | int selfcheck(void); |
Edward O'Callaghan | f78fffc | 2019-06-17 12:40:12 +1000 | [diff] [blame] | 331 | int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename); |
| 332 | int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filename); |
Vadim Bendebury | 2f346a3 | 2018-05-21 10:24:18 -0700 | [diff] [blame] | 333 | |
| 334 | /* |
| 335 | * |
| 336 | * The main processing function of flashrom utility; it is invoked once |
| 337 | * command line parameters are processed and verified, and the type of the |
| 338 | * flash chip the programmer operates on has been determined. |
| 339 | * |
| 340 | * @flash pointer to the flash context matching the chip detected |
| 341 | * during initialization. |
| 342 | * @force when set proceed even if the chip is not known to work |
| 343 | * @filename pointer to the name of the file to read from or write to |
| 344 | * @read_it when true, flash contents are read into 'filename' |
| 345 | * @write_it when true, flash is programmed with 'filename' contents |
| 346 | * @erase_it when true, flash chip is erased |
| 347 | * @verify_it depending on the value verify the full chip, only changed |
| 348 | * areas, or none |
| 349 | * @extract_it extract all known flash chip regions into separate files |
| 350 | * @diff_file when deciding what areas to program, use this file's |
| 351 | * contents instead of reading the current chip contents |
| 352 | * @do_diff when true - compare result of the operation with either the |
| 353 | * original chip contents for 'diff_file' contents, is present. |
| 354 | * When false - do not diff, consider the chip erased before |
| 355 | * operation starts. |
| 356 | * |
| 357 | * Only one of 'read_it', 'write_it', and 'erase_it' is expected to be set, |
| 358 | * but this is not enforced. |
| 359 | * |
| 360 | * 'do_diff' must be set if 'diff_file' is set. If 'do_diff' is set, but |
| 361 | * 'diff_file' is not - comparison is done against the pre-operation chip |
| 362 | * contents. |
| 363 | */ |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 364 | int doit(struct flashctx *flash, int force, const char *filename, int read_it, |
Simon Glass | 9ad06c1 | 2013-07-03 22:08:17 +0900 | [diff] [blame] | 365 | int write_it, int erase_it, int verify_it, int extract_it, |
Vadim Bendebury | 2f346a3 | 2018-05-21 10:24:18 -0700 | [diff] [blame] | 366 | const char *diff_file, int do_diff); |
uwe | 884cc8b | 2009-06-17 12:07:12 +0000 | [diff] [blame] | 367 | |
| 368 | #define OK 0 |
| 369 | #define NT 1 /* Not tested */ |
uwe | 4529d20 | 2007-08-23 13:34:59 +0000 | [diff] [blame] | 370 | |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 371 | /* what to do in case of an error */ |
| 372 | enum error_action { |
| 373 | error_fail, /* fail immediately */ |
| 374 | error_ignore, /* non-fatal error; continue */ |
| 375 | }; |
| 376 | |
uwe | 97e8e27 | 2011-09-03 17:15:00 +0000 | [diff] [blame] | 377 | /* Something happened that shouldn't happen, but we can go on. */ |
mkarcher | 74d3013 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 378 | #define ERROR_NONFATAL 0x100 |
| 379 | |
uwe | 97e8e27 | 2011-09-03 17:15:00 +0000 | [diff] [blame] | 380 | /* Something happened that shouldn't happen, we'll abort. */ |
| 381 | #define ERROR_FATAL -0xee |
Edward O'Callaghan | 20596a8 | 2019-06-13 14:47:03 +1000 | [diff] [blame] | 382 | #define ERROR_FLASHROM_BUG -200 |
| 383 | /* We reached one of the hardcoded limits of flashrom. This can be fixed by |
| 384 | * increasing the limit of a compile-time allocation or by switching to dynamic |
| 385 | * allocation. |
| 386 | * Note: If this warning is triggered, check first for runaway registrations. |
| 387 | */ |
| 388 | #define ERROR_FLASHROM_LIMIT -201 |
| 389 | |
David Hendricks | 1ed1d35 | 2011-11-23 17:54:37 -0800 | [diff] [blame] | 390 | /* Operation failed due to access restriction set in programmer or flash chip */ |
| 391 | #define ACCESS_DENIED -7 |
| 392 | extern enum error_action access_denied_action; |
| 393 | |
| 394 | /* convenience function for checking return codes */ |
| 395 | extern int ignore_error(int x); |
| 396 | |
Edward O'Callaghan | 83c7700 | 2019-06-04 15:56:19 +1000 | [diff] [blame] | 397 | /* cli_common.c */ |
Edward O'Callaghan | 71e30b4 | 2019-06-04 16:16:13 +1000 | [diff] [blame] | 398 | void print_chip_support_status(const struct flashchip *chip); |
Edward O'Callaghan | 83c7700 | 2019-06-04 15:56:19 +1000 | [diff] [blame] | 399 | |
snelson | 9cba3c6 | 2010-01-07 20:09:33 +0000 | [diff] [blame] | 400 | /* cli_output.c */ |
Edward O'Callaghan | 83c7700 | 2019-06-04 15:56:19 +1000 | [diff] [blame] | 401 | extern enum flashrom_log_level verbose_screen; |
| 402 | extern enum flashrom_log_level verbose_logfile; |
Souvik Ghosh | 3c963a4 | 2016-07-19 18:48:15 -0700 | [diff] [blame] | 403 | #ifndef STANDALONE |
| 404 | int open_logfile(const char * const filename); |
| 405 | int close_logfile(void); |
| 406 | void start_logging(void); |
| 407 | #endif |
Edward O'Callaghan | 8d8d397 | 2019-02-24 20:40:10 +1100 | [diff] [blame] | 408 | enum flashrom_log_level { |
| 409 | FLASHROM_MSG_ERROR = 0, |
| 410 | FLASHROM_MSG_WARN = 1, |
| 411 | FLASHROM_MSG_INFO = 2, |
| 412 | FLASHROM_MSG_DEBUG = 3, |
| 413 | FLASHROM_MSG_DEBUG2 = 4, |
| 414 | FLASHROM_MSG_SPEW = 5, |
Patrick Georgi | dbde2f1 | 2017-02-03 18:07:45 +0100 | [diff] [blame] | 415 | }; |
hailfinger | 63932d4 | 2010-06-04 23:20:21 +0000 | [diff] [blame] | 416 | /* Let gcc and clang check for correct printf-style format strings. */ |
Edward O'Callaghan | 8d8d397 | 2019-02-24 20:40:10 +1100 | [diff] [blame] | 417 | int print(enum flashrom_log_level level, const char *fmt, ...) |
Patrick Georgi | dbde2f1 | 2017-02-03 18:07:45 +0100 | [diff] [blame] | 418 | #ifdef __MINGW32__ |
Pavol Marko | ef4c6e8 | 2019-09-09 12:43:44 +0000 | [diff] [blame] | 419 | __attribute__((format(gnu_printf, 2, 3))); |
Patrick Georgi | dbde2f1 | 2017-02-03 18:07:45 +0100 | [diff] [blame] | 420 | #else |
| 421 | __attribute__((format(printf, 2, 3))); |
| 422 | #endif |
Edward O'Callaghan | 8d8d397 | 2019-02-24 20:40:10 +1100 | [diff] [blame] | 423 | #define msg_gerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* general errors */ |
| 424 | #define msg_perr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* programmer errors */ |
| 425 | #define msg_cerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* chip errors */ |
| 426 | #define msg_gwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* general warnings */ |
| 427 | #define msg_pwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* programmer warnings */ |
| 428 | #define msg_cwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* chip warnings */ |
| 429 | #define msg_ginfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* general info */ |
| 430 | #define msg_pinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* programmer info */ |
| 431 | #define msg_cinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* chip info */ |
| 432 | #define msg_gdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* general debug */ |
| 433 | #define msg_pdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* programmer debug */ |
| 434 | #define msg_cdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* chip debug */ |
| 435 | #define msg_gdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ |
| 436 | #define msg_pdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ |
| 437 | #define msg_cdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ |
| 438 | #define msg_gspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* general debug spew */ |
| 439 | #define msg_pspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ |
| 440 | #define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */ |
snelson | 9cba3c6 | 2010-01-07 20:09:33 +0000 | [diff] [blame] | 441 | |
stepan | 745615e | 2007-10-15 21:44:47 +0000 | [diff] [blame] | 442 | /* spi.c */ |
hailfinger | 68002c2 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 443 | struct spi_command { |
| 444 | unsigned int writecnt; |
| 445 | unsigned int readcnt; |
| 446 | const unsigned char *writearr; |
| 447 | unsigned char *readarr; |
| 448 | }; |
Nico Huber | 4c8a956 | 2017-10-15 11:20:58 +0200 | [diff] [blame] | 449 | #define NULL_SPI_CMD { 0, 0, NULL, NULL, } |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 450 | int spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, |
uwe | fa98ca1 | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 451 | const unsigned char *writearr, unsigned char *readarr); |
Souvik Ghosh | d75cd67 | 2016-06-17 14:21:39 -0700 | [diff] [blame] | 452 | int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds); |
| 453 | uint32_t spi_get_valid_read_addr(struct flashctx *flash); |
uwe | af9b4df | 2008-09-26 13:19:02 +0000 | [diff] [blame] | 454 | |
David Hendricks | 8c08421 | 2015-11-17 22:29:36 -0800 | [diff] [blame] | 455 | #define NUM_VOLTAGE_RANGES 16 |
| 456 | extern struct voltage_range voltage_ranges[]; |
| 457 | /* returns number of unique voltage ranges, or <0 to indicate failure */ |
| 458 | extern int flash_supported_voltage_ranges(enum chipbustype bus); |
| 459 | |
Edward O'Callaghan | 4b94057 | 2019-08-02 01:44:47 +1000 | [diff] [blame] | 460 | enum chipbustype get_buses_supported(void); |
ollie | 5b62157 | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 461 | #endif /* !__FLASH_H__ */ |