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hailfinger2c361e42008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
hailfinger4500b082009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
hailfinger2c361e42008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
stepan3bdf6182008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
hailfinger2c361e42008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
hailfinger324a9cc2010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
hailfinger2c361e42008-05-13 23:03:12 +000028#include <string.h>
hailfinger4500b082009-07-11 18:05:42 +000029#include <stdlib.h>
Patrick Georgi048dbdb2017-04-11 20:45:07 +020030#include <errno.h>
hailfinger2c361e42008-05-13 23:03:12 +000031#include "flash.h"
snelson8913d082010-02-26 05:48:29 +000032#include "chipdrivers.h"
hailfinger428f6852010-07-27 22:41:39 +000033#include "programmer.h"
Patrick Georgi048dbdb2017-04-11 20:45:07 +020034#include "hwaccess.h"
hailfinger2c361e42008-05-13 23:03:12 +000035#include "spi.h"
36
37#define ITE_SUPERIO_PORT1 0x2e
38#define ITE_SUPERIO_PORT2 0x4e
39
Patrick Georgi048dbdb2017-04-11 20:45:07 +020040static uint16_t it8716f_flashport = 0;
hailfinger2c361e42008-05-13 23:03:12 +000041/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
hailfinger1ff33dc2010-07-03 11:02:10 +000042static int fast_spi = 1;
hailfinger2c361e42008-05-13 23:03:12 +000043
hailfinger2c361e42008-05-13 23:03:12 +000044/* Helper functions for most recent ITE IT87xx Super I/O chips */
45#define CHIP_ID_BYTE1_REG 0x20
46#define CHIP_ID_BYTE2_REG 0x21
hailfinger94e090c2011-04-27 14:34:08 +000047#define CHIP_VER_REG 0x22
hailfinger7bac0e52009-05-25 23:26:50 +000048void enter_conf_mode_ite(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +000049{
hailfingere1f062f2008-05-22 13:22:45 +000050 OUTB(0x87, port);
51 OUTB(0x01, port);
52 OUTB(0x55, port);
hailfinger2c361e42008-05-13 23:03:12 +000053 if (port == ITE_SUPERIO_PORT1)
hailfingere1f062f2008-05-22 13:22:45 +000054 OUTB(0x55, port);
hailfinger2c361e42008-05-13 23:03:12 +000055 else
hailfingere1f062f2008-05-22 13:22:45 +000056 OUTB(0xaa, port);
hailfinger2c361e42008-05-13 23:03:12 +000057}
58
hailfinger7bac0e52009-05-25 23:26:50 +000059void exit_conf_mode_ite(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +000060{
hailfinger7bac0e52009-05-25 23:26:50 +000061 sio_write(port, 0x02, 0x02);
hailfinger2c361e42008-05-13 23:03:12 +000062}
63
hailfingerc236f9e2009-12-22 23:42:04 +000064uint16_t probe_id_ite(uint16_t port)
65{
66 uint16_t id;
67
68 enter_conf_mode_ite(port);
69 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
70 id |= sio_read(port, CHIP_ID_BYTE2_REG);
71 exit_conf_mode_ite(port);
72
73 return id;
74}
75
hailfinger94e090c2011-04-27 14:34:08 +000076void probe_superio_ite(void)
hailfingerc236f9e2009-12-22 23:42:04 +000077{
Patrick Georgi8ddfee92017-03-20 14:54:28 +010078 struct superio s = {0};
hailfingerc236f9e2009-12-22 23:42:04 +000079 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
80 uint16_t *i = ite_ports;
81
hailfinger94e090c2011-04-27 14:34:08 +000082 s.vendor = SUPERIO_VENDOR_ITE;
hailfingerc236f9e2009-12-22 23:42:04 +000083 for (; *i; i++) {
hailfinger94e090c2011-04-27 14:34:08 +000084 s.port = *i;
85 s.model = probe_id_ite(s.port);
86 switch (s.model >> 8) {
hailfingerc236f9e2009-12-22 23:42:04 +000087 case 0x82:
88 case 0x86:
89 case 0x87:
hailfinger94e090c2011-04-27 14:34:08 +000090 /* FIXME: Print revision for all models? */
Patrick Georgi05482992017-03-20 21:56:33 +010091 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port 0x%x\n", s.model, s.port);
hailfinger94e090c2011-04-27 14:34:08 +000092 register_superio(s);
93 break;
94 case 0x85:
Patrick Georgi05482992017-03-20 21:56:33 +010095 msg_pdbg("Found ITE EC, ID 0x%04hx, Rev 0x%02x on port 0x%x.\n",
96 s.model, sio_read(s.port, CHIP_VER_REG), s.port);
hailfinger94e090c2011-04-27 14:34:08 +000097 register_superio(s);
98 break;
hailfingerc236f9e2009-12-22 23:42:04 +000099 }
100 }
101
hailfinger94e090c2011-04-27 14:34:08 +0000102 return;
hailfingerc236f9e2009-12-22 23:42:04 +0000103}
104
Patrick Georgi05482992017-03-20 21:56:33 +0100105static int it8716f_spi_send_command(const struct flashctx *flash,
106 unsigned int writecnt, unsigned int readcnt,
107 const unsigned char *writearr,
108 unsigned char *readarr);
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700109static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000110 unsigned int start, unsigned int len);
Patrick Georgiab8353e2017-02-03 18:32:01 +0100111static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000112 unsigned int start, unsigned int len);
mkarcherd264e9e2011-05-11 17:07:07 +0000113
Patrick Georgif4f1e2f2017-03-10 17:38:40 +0100114static const struct spi_master spi_master_it87xx = {
uwe8d342eb2011-07-28 08:13:25 +0000115 .type = SPI_CONTROLLER_IT87XX,
116 .max_data_read = MAX_DATA_UNSPECIFIED,
117 .max_data_write = MAX_DATA_UNSPECIFIED,
118 .command = it8716f_spi_send_command,
119 .multicommand = default_spi_send_multicommand,
120 .read = it8716f_spi_chip_read,
121 .write_256 = it8716f_spi_chip_write_256,
mkarcherd264e9e2011-05-11 17:07:07 +0000122};
123
hailfingerc73ce6e2010-07-10 16:56:32 +0000124static uint16_t it87spi_probe(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +0000125{
126 uint8_t tmp = 0;
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200127 char *param = NULL;
hailfingerc236f9e2009-12-22 23:42:04 +0000128 uint16_t flashport = 0;
hailfinger2c361e42008-05-13 23:03:12 +0000129
hailfingerc73ce6e2010-07-10 16:56:32 +0000130 enter_conf_mode_ite(port);
131 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
132 tmp = sio_read(port, 0x24) & 0xFE;
hailfinger969e2f32011-09-08 00:00:29 +0000133 /* Check if LPC->SPI translation is active. */
134 if (!(tmp & 0x0e)) {
hailfingerc73ce6e2010-07-10 16:56:32 +0000135 msg_pdbg("No IT87* serial flash segment enabled.\n");
136 exit_conf_mode_ite(port);
137 /* Nothing to do. */
David Hendricks5e79c9f2013-11-04 22:05:08 -0800138 return 1;
hailfingerc73ce6e2010-07-10 16:56:32 +0000139 }
140 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
141 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
142 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
143 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
144 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
145 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
146 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
147 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
148 msg_pdbg("LPC write to serial flash %sabled\n",
149 (tmp & 1 << 4) ? "en" : "dis");
150 /* The LPC->SPI force write enable below only makes sense for
151 * non-programmer mode.
152 */
153 /* If any serial flash segment is enabled, enable writing. */
154 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
155 msg_pdbg("Enabling LPC write to serial flash\n");
156 tmp |= 1 << 4;
157 sio_write(port, 0x24, tmp);
158 }
159 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
160 /* LDN 0x7, reg 0x64/0x65 */
161 sio_write(port, 0x07, 0x7);
162 flashport = sio_read(port, 0x64) << 8;
163 flashport |= sio_read(port, 0x65);
164 msg_pdbg("Serial flash port 0x%04x\n", flashport);
165 /* Non-default port requested? */
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200166 param = extract_programmer_param("it87spiport");
167 if (param) {
hailfingerc73ce6e2010-07-10 16:56:32 +0000168 char *endptr = NULL;
169 unsigned long forced_flashport;
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200170 forced_flashport = strtoul(param, &endptr, 0);
hailfingerc73ce6e2010-07-10 16:56:32 +0000171 /* Port 0, port >0x1000, unaligned ports and garbage strings
172 * are rejected.
hailfingerddd5d7b2010-03-25 02:50:40 +0000173 */
hailfingerc73ce6e2010-07-10 16:56:32 +0000174 if (!forced_flashport || (forced_flashport >= 0x1000) ||
175 (forced_flashport & 0x7) || (*endptr != '\0')) {
176 /* Using ports below 0x100 is a really bad idea, and
177 * should only be done if no port between 0x100 and
178 * 0xff8 works due to routing issues.
179 */
180 msg_perr("Error: it87spiport specified, but no valid "
181 "port specified.\nPort must be a multiple of "
182 "0x8 and lie between 0x100 and 0xff8.\n");
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200183 exit_conf_mode_ite(port);
184 free(param);
hailfinger94e090c2011-04-27 14:34:08 +0000185 return 1;
hailfingerc73ce6e2010-07-10 16:56:32 +0000186 } else {
187 flashport = (uint16_t)forced_flashport;
188 msg_pinfo("Forcing serial flash port 0x%04x\n",
189 flashport);
190 sio_write(port, 0x64, (flashport >> 8));
191 sio_write(port, 0x65, (flashport & 0xff));
hailfinger4500b082009-07-11 18:05:42 +0000192 }
hailfinger2c361e42008-05-13 23:03:12 +0000193 }
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200194 free(param);
hailfingerc73ce6e2010-07-10 16:56:32 +0000195 exit_conf_mode_ite(port);
196 it8716f_flashport = flashport;
hailfinger76bb7e92011-11-09 23:40:00 +0000197 if (internal_buses_supported & BUS_SPI)
hailfingerc73ce6e2010-07-10 16:56:32 +0000198 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
hailfinger94e090c2011-04-27 14:34:08 +0000199 /* FIXME: Add the SPI bus or replace the other buses with it? */
Patrick Georgif4f1e2f2017-03-10 17:38:40 +0100200 register_spi_master(&spi_master_it87xx);
hailfingerc73ce6e2010-07-10 16:56:32 +0000201 return 0;
hailfinger2c361e42008-05-13 23:03:12 +0000202}
203
David Hendricksac1d25c2016-08-09 17:00:58 -0700204int init_superio_ite(void)
hailfinger2c361e42008-05-13 23:03:12 +0000205{
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200206 int i;
207 int ret = 0;
208 int chips_found = 0;
stepan3bdf6182008-06-30 23:45:22 +0000209
hailfinger94e090c2011-04-27 14:34:08 +0000210 for (i = 0; i < superio_count; i++) {
211 if (superios[i].vendor != SUPERIO_VENDOR_ITE)
212 continue;
hailfinger2c361e42008-05-13 23:03:12 +0000213
hailfinger94e090c2011-04-27 14:34:08 +0000214 switch (superios[i].model) {
215 case 0x8500:
216 case 0x8502:
217 case 0x8510:
218 case 0x8511:
219 case 0x8512:
220 /* FIXME: This should be enabled, but we need a check
221 * for laptop whitelisting due to the amount of things
222 * which can go wrong if the EC firmware does not
223 * implement the interface we want.
224 */
David Hendricksac1d25c2016-08-09 17:00:58 -0700225 if (!it85xx_spi_init(superios[i]))
David Hendricks5e79c9f2013-11-04 22:05:08 -0800226 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000227 break;
Shawn Nematbakhsh3404b1a2012-07-26 15:19:58 -0700228 case 0x8518:
David Hendricksac1d25c2016-08-09 17:00:58 -0700229 if (!it8518_spi_init(superios[i]))
David Hendricks5e79c9f2013-11-04 22:05:08 -0800230 chips_found++;
Shawn Nematbakhsh3404b1a2012-07-26 15:19:58 -0700231 break;
hailfinger94e090c2011-04-27 14:34:08 +0000232 case 0x8705:
David Hendricks5e79c9f2013-11-04 22:05:08 -0800233 if (!it8705f_write_enable(superios[i].port))
234 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000235 break;
236 case 0x8716:
237 case 0x8718:
238 case 0x8720:
David Hendricks5e79c9f2013-11-04 22:05:08 -0800239 if (!it87spi_probe(superios[i].port))
240 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000241 break;
242 default:
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200243 msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
244 superios[i].model);
hailfinger94e090c2011-04-27 14:34:08 +0000245 }
hailfingerd9f5da22009-06-28 10:57:58 +0000246 }
David Hendricks5e79c9f2013-11-04 22:05:08 -0800247
248 if (chips_found == 0) {
249 ret = 1; /* failed to probe/initialize/enable chip */
250 } else if (chips_found == 1) {
251 ret = 0; /* success */
252 } else {
253 msg_pdbg("%s: Found %d programmable ECs/SuperIOs, aborting.\n",
254 __func__, chips_found);
255 ret = 1;
256 }
hailfingera916b422009-06-01 02:08:58 +0000257 return ret;
hailfinger26e212b2009-05-31 18:00:57 +0000258}
259
uwefa98ca12008-10-18 21:14:13 +0000260/*
261 * The IT8716F only supports commands with length 1,2,4,5 bytes including
262 * command byte and can not read more than 3 bytes from the device.
263 *
264 * This function expects writearr[0] to be the first byte sent to the device,
265 * whereas the IT8716F splits commands internally into address and non-address
266 * commands with the address in inverse wire order. That's why the register
267 * ordering in case 4 and 5 may seem strange.
268 */
Patrick Georgi05482992017-03-20 21:56:33 +0100269static int it8716f_spi_send_command(const struct flashctx *flash,
270 unsigned int writecnt, unsigned int readcnt,
271 const unsigned char *writearr,
272 unsigned char *readarr)
hailfinger2c361e42008-05-13 23:03:12 +0000273{
274 uint8_t busy, writeenc;
275 int i;
276
277 do {
hailfingere1f062f2008-05-22 13:22:45 +0000278 busy = INB(it8716f_flashport) & 0x80;
hailfinger2c361e42008-05-13 23:03:12 +0000279 } while (busy);
280 if (readcnt > 3) {
snelson55fe91c2010-01-10 01:09:58 +0000281 msg_pinfo("%s called with unsupported readcnt %i.\n",
uwe8d342eb2011-07-28 08:13:25 +0000282 __func__, readcnt);
hailfinger9c290a72009-07-14 10:26:56 +0000283 return SPI_INVALID_LENGTH;
hailfinger2c361e42008-05-13 23:03:12 +0000284 }
285 switch (writecnt) {
286 case 1:
hailfingere1f062f2008-05-22 13:22:45 +0000287 OUTB(writearr[0], it8716f_flashport + 1);
hailfinger2c361e42008-05-13 23:03:12 +0000288 writeenc = 0x0;
289 break;
290 case 2:
hailfingere1f062f2008-05-22 13:22:45 +0000291 OUTB(writearr[0], it8716f_flashport + 1);
292 OUTB(writearr[1], it8716f_flashport + 7);
hailfinger2c361e42008-05-13 23:03:12 +0000293 writeenc = 0x1;
294 break;
295 case 4:
hailfingere1f062f2008-05-22 13:22:45 +0000296 OUTB(writearr[0], it8716f_flashport + 1);
297 OUTB(writearr[1], it8716f_flashport + 4);
298 OUTB(writearr[2], it8716f_flashport + 3);
299 OUTB(writearr[3], it8716f_flashport + 2);
hailfinger2c361e42008-05-13 23:03:12 +0000300 writeenc = 0x2;
301 break;
302 case 5:
hailfingere1f062f2008-05-22 13:22:45 +0000303 OUTB(writearr[0], it8716f_flashport + 1);
304 OUTB(writearr[1], it8716f_flashport + 4);
305 OUTB(writearr[2], it8716f_flashport + 3);
306 OUTB(writearr[3], it8716f_flashport + 2);
307 OUTB(writearr[4], it8716f_flashport + 7);
hailfinger2c361e42008-05-13 23:03:12 +0000308 writeenc = 0x3;
309 break;
310 default:
snelson55fe91c2010-01-10 01:09:58 +0000311 msg_pinfo("%s called with unsupported writecnt %i.\n",
uwe8d342eb2011-07-28 08:13:25 +0000312 __func__, writecnt);
hailfinger9c290a72009-07-14 10:26:56 +0000313 return SPI_INVALID_LENGTH;
hailfinger2c361e42008-05-13 23:03:12 +0000314 }
uwefa98ca12008-10-18 21:14:13 +0000315 /*
316 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
hailfinger2c361e42008-05-13 23:03:12 +0000317 * Note:
318 * We can't use writecnt directly, but have to use a strange encoding.
uwefa98ca12008-10-18 21:14:13 +0000319 */
320 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
321 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
hailfinger2c361e42008-05-13 23:03:12 +0000322
323 if (readcnt > 0) {
324 do {
hailfingere1f062f2008-05-22 13:22:45 +0000325 busy = INB(it8716f_flashport) & 0x80;
hailfinger2c361e42008-05-13 23:03:12 +0000326 } while (busy);
327
uwefa98ca12008-10-18 21:14:13 +0000328 for (i = 0; i < readcnt; i++)
hailfingere1f062f2008-05-22 13:22:45 +0000329 readarr[i] = INB(it8716f_flashport + 5 + i);
hailfinger2c361e42008-05-13 23:03:12 +0000330 }
331
332 return 0;
333}
334
335/* Page size is usually 256 bytes */
Patrick Georgi05482992017-03-20 21:56:33 +0100336static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start)
uwefa98ca12008-10-18 21:14:13 +0000337{
stefanctc5eb8a92011-11-23 09:13:48 +0000338 unsigned int i;
339 int result;
hailfinger4500b082009-07-11 18:05:42 +0000340 chipaddr bios = flash->virtual_memory;
hailfinger2c361e42008-05-13 23:03:12 +0000341
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700342 result = spi_write_enable(flash);
hailfinger61949942009-05-09 02:09:45 +0000343 if (result)
344 return result;
hailfingerec9334b2009-07-12 12:06:18 +0000345 /* FIXME: The command below seems to be redundant or wrong. */
uwefa98ca12008-10-18 21:14:13 +0000346 OUTB(0x06, it8716f_flashport + 1);
hailfingere1f062f2008-05-22 13:22:45 +0000347 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
Patrick Georgif3fa2992017-02-02 16:24:44 +0100348 for (i = 0; i < flash->chip->page_size; i++)
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700349 chip_writeb(flash, buf[i], bios + start + i);
hailfingere1f062f2008-05-22 13:22:45 +0000350 OUTB(0, it8716f_flashport);
hailfinger2c361e42008-05-13 23:03:12 +0000351 /* Wait until the Write-In-Progress bit is cleared.
352 * This usually takes 1-10 ms, so wait in 1 ms steps.
353 */
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530354 while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
hailfingere5829f62009-06-05 17:48:08 +0000355 programmer_delay(1000);
hailfinger61949942009-05-09 02:09:45 +0000356 return 0;
hailfinger2c361e42008-05-13 23:03:12 +0000357}
358
359/*
hailfinger2c361e42008-05-13 23:03:12 +0000360 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
361 * Need to read this big flash using firmware cycles 3 byte at a time.
362 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700363static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000364 unsigned int start, unsigned int len)
hailfinger2c361e42008-05-13 23:03:12 +0000365{
hailfinger2c361e42008-05-13 23:03:12 +0000366 fast_spi = 0;
367
hailfinger94e090c2011-04-27 14:34:08 +0000368 /* FIXME: Check if someone explicitly requested to use IT87 SPI although
369 * the mainboard does not use IT87 SPI translation. This should be done
370 * via a programmer parameter for the internal programmer.
371 */
Patrick Georgif3fa2992017-02-02 16:24:44 +0100372 if ((flash->chip->total_size * 1024 > 512 * 1024)) {
hailfinger0f08b7a2009-06-16 08:55:44 +0000373 spi_read_chunked(flash, buf, start, len, 3);
hailfinger2c361e42008-05-13 23:03:12 +0000374 } else {
hailfinger0f08b7a2009-06-16 08:55:44 +0000375 read_memmapped(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000376 }
uwefa98ca12008-10-18 21:14:13 +0000377
hailfinger2c361e42008-05-13 23:03:12 +0000378 return 0;
379}
380
Patrick Georgiab8353e2017-02-03 18:32:01 +0100381static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000382 unsigned int start, unsigned int len)
uwefa98ca12008-10-18 21:14:13 +0000383{
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200384 const struct flashchip *chip = flash->chip;
hailfingered063f52009-05-09 02:30:21 +0000385 /*
386 * IT8716F only allows maximum of 512 kb SPI chip size for memory
hailfingerdef852d2010-10-27 22:07:11 +0000387 * mapped access. It also can't write more than 1+3+256 bytes at once,
388 * so page_size > 256 bytes needs a fallback.
389 * FIXME: Split too big page writes into chunks IT87* can handle instead
390 * of degrading to single-byte program.
hailfinger94e090c2011-04-27 14:34:08 +0000391 * FIXME: Check if someone explicitly requested to use IT87 SPI although
392 * the mainboard does not use IT87 SPI translation. This should be done
393 * via a programmer parameter for the internal programmer.
hailfingered063f52009-05-09 02:30:21 +0000394 */
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200395 if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) {
hailfinger71e1bd42010-10-13 22:26:56 +0000396 spi_chip_write_1(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000397 } else {
stefanctc5eb8a92011-11-23 09:13:48 +0000398 unsigned int lenhere;
hailfingerc7d06c62010-07-14 16:19:05 +0000399
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200400 if (start % chip->page_size) {
hailfingerdef852d2010-10-27 22:07:11 +0000401 /* start to the end of the page or to start + len,
402 * whichever is smaller.
hailfingerc7d06c62010-07-14 16:19:05 +0000403 */
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200404 lenhere = min(len, chip->page_size - start % chip->page_size);
hailfinger71e1bd42010-10-13 22:26:56 +0000405 spi_chip_write_1(flash, buf, start, lenhere);
hailfingerc7d06c62010-07-14 16:19:05 +0000406 start += lenhere;
407 len -= lenhere;
408 buf += lenhere;
hailfingere8b674c2009-08-10 02:29:21 +0000409 }
hailfingerc7d06c62010-07-14 16:19:05 +0000410
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200411 while (len >= chip->page_size) {
hailfingerc7d06c62010-07-14 16:19:05 +0000412 it8716f_spi_page_program(flash, buf, start);
Patrick Georgi048dbdb2017-04-11 20:45:07 +0200413 start += chip->page_size;
414 len -= chip->page_size;
415 buf += chip->page_size;
hailfinger2c361e42008-05-13 23:03:12 +0000416 }
hailfingerc7d06c62010-07-14 16:19:05 +0000417 if (len)
hailfinger71e1bd42010-10-13 22:26:56 +0000418 spi_chip_write_1(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000419 }
uwefa98ca12008-10-18 21:14:13 +0000420
hailfinger2c361e42008-05-13 23:03:12 +0000421 return 0;
422}
hailfinger324a9cc2010-05-26 01:45:41 +0000423
424#endif