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hailfinger2c361e42008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
hailfinger4500b082009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
hailfinger2c361e42008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
stepan3bdf6182008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
hailfinger2c361e42008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
hailfinger324a9cc2010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
hailfinger2c361e42008-05-13 23:03:12 +000028#include <string.h>
hailfinger4500b082009-07-11 18:05:42 +000029#include <stdlib.h>
hailfinger2c361e42008-05-13 23:03:12 +000030#include "flash.h"
snelson8913d082010-02-26 05:48:29 +000031#include "chipdrivers.h"
hailfinger428f6852010-07-27 22:41:39 +000032#include "programmer.h"
hailfinger2c361e42008-05-13 23:03:12 +000033#include "spi.h"
34
35#define ITE_SUPERIO_PORT1 0x2e
36#define ITE_SUPERIO_PORT2 0x4e
37
hailfinger2c361e42008-05-13 23:03:12 +000038uint16_t it8716f_flashport = 0;
39/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
hailfinger1ff33dc2010-07-03 11:02:10 +000040static int fast_spi = 1;
hailfinger2c361e42008-05-13 23:03:12 +000041
hailfinger2c361e42008-05-13 23:03:12 +000042/* Helper functions for most recent ITE IT87xx Super I/O chips */
43#define CHIP_ID_BYTE1_REG 0x20
44#define CHIP_ID_BYTE2_REG 0x21
hailfinger94e090c2011-04-27 14:34:08 +000045#define CHIP_VER_REG 0x22
hailfinger7bac0e52009-05-25 23:26:50 +000046void enter_conf_mode_ite(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +000047{
hailfingere1f062f2008-05-22 13:22:45 +000048 OUTB(0x87, port);
49 OUTB(0x01, port);
50 OUTB(0x55, port);
hailfinger2c361e42008-05-13 23:03:12 +000051 if (port == ITE_SUPERIO_PORT1)
hailfingere1f062f2008-05-22 13:22:45 +000052 OUTB(0x55, port);
hailfinger2c361e42008-05-13 23:03:12 +000053 else
hailfingere1f062f2008-05-22 13:22:45 +000054 OUTB(0xaa, port);
hailfinger2c361e42008-05-13 23:03:12 +000055}
56
hailfinger7bac0e52009-05-25 23:26:50 +000057void exit_conf_mode_ite(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +000058{
hailfinger7bac0e52009-05-25 23:26:50 +000059 sio_write(port, 0x02, 0x02);
hailfinger2c361e42008-05-13 23:03:12 +000060}
61
hailfingerc236f9e2009-12-22 23:42:04 +000062uint16_t probe_id_ite(uint16_t port)
63{
64 uint16_t id;
65
66 enter_conf_mode_ite(port);
67 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
68 id |= sio_read(port, CHIP_ID_BYTE2_REG);
69 exit_conf_mode_ite(port);
70
71 return id;
72}
73
hailfinger94e090c2011-04-27 14:34:08 +000074void probe_superio_ite(void)
hailfingerc236f9e2009-12-22 23:42:04 +000075{
hailfinger94e090c2011-04-27 14:34:08 +000076 struct superio s = {};
hailfingerc236f9e2009-12-22 23:42:04 +000077 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
78 uint16_t *i = ite_ports;
79
hailfinger94e090c2011-04-27 14:34:08 +000080 s.vendor = SUPERIO_VENDOR_ITE;
hailfingerc236f9e2009-12-22 23:42:04 +000081 for (; *i; i++) {
hailfinger94e090c2011-04-27 14:34:08 +000082 s.port = *i;
83 s.model = probe_id_ite(s.port);
84 switch (s.model >> 8) {
hailfingerc236f9e2009-12-22 23:42:04 +000085 case 0x82:
86 case 0x86:
87 case 0x87:
hailfinger94e090c2011-04-27 14:34:08 +000088 /* FIXME: Print revision for all models? */
89 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
90 "0x%x\n", s.model, s.port);
91 register_superio(s);
92 break;
93 case 0x85:
94 msg_pdbg("Found ITE EC, ID 0x%04hx,"
95 "Rev 0x%02x on port 0x%x.\n",
uwe8d342eb2011-07-28 08:13:25 +000096 s.model, sio_read(s.port, CHIP_VER_REG),
hailfinger94e090c2011-04-27 14:34:08 +000097 s.port);
98 register_superio(s);
99 break;
hailfingerc236f9e2009-12-22 23:42:04 +0000100 }
101 }
102
hailfinger94e090c2011-04-27 14:34:08 +0000103 return;
hailfingerc236f9e2009-12-22 23:42:04 +0000104}
105
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700106static int it8716f_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
mkarcherd264e9e2011-05-11 17:07:07 +0000107 const unsigned char *writearr, unsigned char *readarr);
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700108static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000109 unsigned int start, unsigned int len);
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700110static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000111 unsigned int start, unsigned int len);
mkarcherd264e9e2011-05-11 17:07:07 +0000112
113static const struct spi_programmer spi_programmer_it87xx = {
uwe8d342eb2011-07-28 08:13:25 +0000114 .type = SPI_CONTROLLER_IT87XX,
115 .max_data_read = MAX_DATA_UNSPECIFIED,
116 .max_data_write = MAX_DATA_UNSPECIFIED,
117 .command = it8716f_spi_send_command,
118 .multicommand = default_spi_send_multicommand,
119 .read = it8716f_spi_chip_read,
120 .write_256 = it8716f_spi_chip_write_256,
mkarcherd264e9e2011-05-11 17:07:07 +0000121};
122
hailfingerc73ce6e2010-07-10 16:56:32 +0000123static uint16_t it87spi_probe(uint16_t port)
hailfinger2c361e42008-05-13 23:03:12 +0000124{
125 uint8_t tmp = 0;
hailfinger4500b082009-07-11 18:05:42 +0000126 char *portpos = NULL;
hailfingerc236f9e2009-12-22 23:42:04 +0000127 uint16_t flashport = 0;
hailfinger2c361e42008-05-13 23:03:12 +0000128
hailfingerc73ce6e2010-07-10 16:56:32 +0000129 enter_conf_mode_ite(port);
130 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
131 tmp = sio_read(port, 0x24) & 0xFE;
hailfinger969e2f32011-09-08 00:00:29 +0000132 /* Check if LPC->SPI translation is active. */
133 if (!(tmp & 0x0e)) {
hailfingerc73ce6e2010-07-10 16:56:32 +0000134 msg_pdbg("No IT87* serial flash segment enabled.\n");
135 exit_conf_mode_ite(port);
136 /* Nothing to do. */
David Hendricks5e79c9f2013-11-04 22:05:08 -0800137 return 1;
hailfingerc73ce6e2010-07-10 16:56:32 +0000138 }
139 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
140 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
141 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
142 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
143 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
144 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
145 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
146 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
147 msg_pdbg("LPC write to serial flash %sabled\n",
148 (tmp & 1 << 4) ? "en" : "dis");
149 /* The LPC->SPI force write enable below only makes sense for
150 * non-programmer mode.
151 */
152 /* If any serial flash segment is enabled, enable writing. */
153 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
154 msg_pdbg("Enabling LPC write to serial flash\n");
155 tmp |= 1 << 4;
156 sio_write(port, 0x24, tmp);
157 }
158 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
159 /* LDN 0x7, reg 0x64/0x65 */
160 sio_write(port, 0x07, 0x7);
161 flashport = sio_read(port, 0x64) << 8;
162 flashport |= sio_read(port, 0x65);
163 msg_pdbg("Serial flash port 0x%04x\n", flashport);
164 /* Non-default port requested? */
165 portpos = extract_programmer_param("it87spiport");
166 if (portpos) {
167 char *endptr = NULL;
168 unsigned long forced_flashport;
169 forced_flashport = strtoul(portpos, &endptr, 0);
170 /* Port 0, port >0x1000, unaligned ports and garbage strings
171 * are rejected.
hailfingerddd5d7b2010-03-25 02:50:40 +0000172 */
hailfingerc73ce6e2010-07-10 16:56:32 +0000173 if (!forced_flashport || (forced_flashport >= 0x1000) ||
174 (forced_flashport & 0x7) || (*endptr != '\0')) {
175 /* Using ports below 0x100 is a really bad idea, and
176 * should only be done if no port between 0x100 and
177 * 0xff8 works due to routing issues.
178 */
179 msg_perr("Error: it87spiport specified, but no valid "
180 "port specified.\nPort must be a multiple of "
181 "0x8 and lie between 0x100 and 0xff8.\n");
hailfinger1ef766d2010-07-06 09:55:48 +0000182 free(portpos);
hailfinger94e090c2011-04-27 14:34:08 +0000183 return 1;
hailfingerc73ce6e2010-07-10 16:56:32 +0000184 } else {
185 flashport = (uint16_t)forced_flashport;
186 msg_pinfo("Forcing serial flash port 0x%04x\n",
187 flashport);
188 sio_write(port, 0x64, (flashport >> 8));
189 sio_write(port, 0x65, (flashport & 0xff));
hailfinger4500b082009-07-11 18:05:42 +0000190 }
hailfinger2c361e42008-05-13 23:03:12 +0000191 }
hailfingerc73ce6e2010-07-10 16:56:32 +0000192 free(portpos);
193 exit_conf_mode_ite(port);
194 it8716f_flashport = flashport;
hailfinger76bb7e92011-11-09 23:40:00 +0000195 if (internal_buses_supported & BUS_SPI)
hailfingerc73ce6e2010-07-10 16:56:32 +0000196 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
hailfinger94e090c2011-04-27 14:34:08 +0000197 /* FIXME: Add the SPI bus or replace the other buses with it? */
mkarcherd264e9e2011-05-11 17:07:07 +0000198 register_spi_programmer(&spi_programmer_it87xx);
hailfingerc73ce6e2010-07-10 16:56:32 +0000199 return 0;
hailfinger2c361e42008-05-13 23:03:12 +0000200}
201
hailfingerc73ce6e2010-07-10 16:56:32 +0000202int init_superio_ite(void)
hailfinger2c361e42008-05-13 23:03:12 +0000203{
David Hendricks5e79c9f2013-11-04 22:05:08 -0800204 int i, ret, chips_found = 0;
stepan3bdf6182008-06-30 23:45:22 +0000205
hailfinger94e090c2011-04-27 14:34:08 +0000206 for (i = 0; i < superio_count; i++) {
207 if (superios[i].vendor != SUPERIO_VENDOR_ITE)
208 continue;
hailfinger2c361e42008-05-13 23:03:12 +0000209
hailfinger94e090c2011-04-27 14:34:08 +0000210 switch (superios[i].model) {
211 case 0x8500:
212 case 0x8502:
213 case 0x8510:
214 case 0x8511:
215 case 0x8512:
216 /* FIXME: This should be enabled, but we need a check
217 * for laptop whitelisting due to the amount of things
218 * which can go wrong if the EC firmware does not
219 * implement the interface we want.
220 */
David Hendricks5e79c9f2013-11-04 22:05:08 -0800221 if (!it85xx_spi_init(superios[i]))
222 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000223 break;
Shawn Nematbakhsh3404b1a2012-07-26 15:19:58 -0700224 case 0x8518:
David Hendricks5e79c9f2013-11-04 22:05:08 -0800225 if (!it8518_spi_init(superios[i]))
226 chips_found++;
Shawn Nematbakhsh3404b1a2012-07-26 15:19:58 -0700227 break;
hailfinger94e090c2011-04-27 14:34:08 +0000228 case 0x8705:
David Hendricks5e79c9f2013-11-04 22:05:08 -0800229 if (!it8705f_write_enable(superios[i].port))
230 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000231 break;
232 case 0x8716:
233 case 0x8718:
234 case 0x8720:
David Hendricks5e79c9f2013-11-04 22:05:08 -0800235 if (!it87spi_probe(superios[i].port))
236 chips_found++;
hailfinger94e090c2011-04-27 14:34:08 +0000237 break;
238 default:
239 msg_pdbg("Super I/O ID 0x%04hx is not on the list of "
240 "flash capable controllers.\n",
241 superios[i].model);
242 }
hailfingerd9f5da22009-06-28 10:57:58 +0000243 }
David Hendricks5e79c9f2013-11-04 22:05:08 -0800244
245 if (chips_found == 0) {
246 ret = 1; /* failed to probe/initialize/enable chip */
247 } else if (chips_found == 1) {
248 ret = 0; /* success */
249 } else {
250 msg_pdbg("%s: Found %d programmable ECs/SuperIOs, aborting.\n",
251 __func__, chips_found);
252 ret = 1;
253 }
hailfingera916b422009-06-01 02:08:58 +0000254 return ret;
hailfinger26e212b2009-05-31 18:00:57 +0000255}
256
uwefa98ca12008-10-18 21:14:13 +0000257/*
258 * The IT8716F only supports commands with length 1,2,4,5 bytes including
259 * command byte and can not read more than 3 bytes from the device.
260 *
261 * This function expects writearr[0] to be the first byte sent to the device,
262 * whereas the IT8716F splits commands internally into address and non-address
263 * commands with the address in inverse wire order. That's why the register
264 * ordering in case 4 and 5 may seem strange.
265 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700266static int it8716f_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
uwefa98ca12008-10-18 21:14:13 +0000267 const unsigned char *writearr, unsigned char *readarr)
hailfinger2c361e42008-05-13 23:03:12 +0000268{
269 uint8_t busy, writeenc;
270 int i;
271
272 do {
hailfingere1f062f2008-05-22 13:22:45 +0000273 busy = INB(it8716f_flashport) & 0x80;
hailfinger2c361e42008-05-13 23:03:12 +0000274 } while (busy);
275 if (readcnt > 3) {
snelson55fe91c2010-01-10 01:09:58 +0000276 msg_pinfo("%s called with unsupported readcnt %i.\n",
uwe8d342eb2011-07-28 08:13:25 +0000277 __func__, readcnt);
hailfinger9c290a72009-07-14 10:26:56 +0000278 return SPI_INVALID_LENGTH;
hailfinger2c361e42008-05-13 23:03:12 +0000279 }
280 switch (writecnt) {
281 case 1:
hailfingere1f062f2008-05-22 13:22:45 +0000282 OUTB(writearr[0], it8716f_flashport + 1);
hailfinger2c361e42008-05-13 23:03:12 +0000283 writeenc = 0x0;
284 break;
285 case 2:
hailfingere1f062f2008-05-22 13:22:45 +0000286 OUTB(writearr[0], it8716f_flashport + 1);
287 OUTB(writearr[1], it8716f_flashport + 7);
hailfinger2c361e42008-05-13 23:03:12 +0000288 writeenc = 0x1;
289 break;
290 case 4:
hailfingere1f062f2008-05-22 13:22:45 +0000291 OUTB(writearr[0], it8716f_flashport + 1);
292 OUTB(writearr[1], it8716f_flashport + 4);
293 OUTB(writearr[2], it8716f_flashport + 3);
294 OUTB(writearr[3], it8716f_flashport + 2);
hailfinger2c361e42008-05-13 23:03:12 +0000295 writeenc = 0x2;
296 break;
297 case 5:
hailfingere1f062f2008-05-22 13:22:45 +0000298 OUTB(writearr[0], it8716f_flashport + 1);
299 OUTB(writearr[1], it8716f_flashport + 4);
300 OUTB(writearr[2], it8716f_flashport + 3);
301 OUTB(writearr[3], it8716f_flashport + 2);
302 OUTB(writearr[4], it8716f_flashport + 7);
hailfinger2c361e42008-05-13 23:03:12 +0000303 writeenc = 0x3;
304 break;
305 default:
snelson55fe91c2010-01-10 01:09:58 +0000306 msg_pinfo("%s called with unsupported writecnt %i.\n",
uwe8d342eb2011-07-28 08:13:25 +0000307 __func__, writecnt);
hailfinger9c290a72009-07-14 10:26:56 +0000308 return SPI_INVALID_LENGTH;
hailfinger2c361e42008-05-13 23:03:12 +0000309 }
uwefa98ca12008-10-18 21:14:13 +0000310 /*
311 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
hailfinger2c361e42008-05-13 23:03:12 +0000312 * Note:
313 * We can't use writecnt directly, but have to use a strange encoding.
uwefa98ca12008-10-18 21:14:13 +0000314 */
315 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
316 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
hailfinger2c361e42008-05-13 23:03:12 +0000317
318 if (readcnt > 0) {
319 do {
hailfingere1f062f2008-05-22 13:22:45 +0000320 busy = INB(it8716f_flashport) & 0x80;
hailfinger2c361e42008-05-13 23:03:12 +0000321 } while (busy);
322
uwefa98ca12008-10-18 21:14:13 +0000323 for (i = 0; i < readcnt; i++)
hailfingere1f062f2008-05-22 13:22:45 +0000324 readarr[i] = INB(it8716f_flashport + 5 + i);
hailfinger2c361e42008-05-13 23:03:12 +0000325 }
326
327 return 0;
328}
329
330/* Page size is usually 256 bytes */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700331static int it8716f_spi_page_program(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000332 unsigned int start)
uwefa98ca12008-10-18 21:14:13 +0000333{
stefanctc5eb8a92011-11-23 09:13:48 +0000334 unsigned int i;
335 int result;
hailfinger4500b082009-07-11 18:05:42 +0000336 chipaddr bios = flash->virtual_memory;
hailfinger2c361e42008-05-13 23:03:12 +0000337
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700338 result = spi_write_enable(flash);
hailfinger61949942009-05-09 02:09:45 +0000339 if (result)
340 return result;
hailfingerec9334b2009-07-12 12:06:18 +0000341 /* FIXME: The command below seems to be redundant or wrong. */
uwefa98ca12008-10-18 21:14:13 +0000342 OUTB(0x06, it8716f_flashport + 1);
hailfingere1f062f2008-05-22 13:22:45 +0000343 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
uwe8d342eb2011-07-28 08:13:25 +0000344 for (i = 0; i < flash->page_size; i++)
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700345 chip_writeb(flash, buf[i], bios + start + i);
hailfingere1f062f2008-05-22 13:22:45 +0000346 OUTB(0, it8716f_flashport);
hailfinger2c361e42008-05-13 23:03:12 +0000347 /* Wait until the Write-In-Progress bit is cleared.
348 * This usually takes 1-10 ms, so wait in 1 ms steps.
349 */
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530350 while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
hailfingere5829f62009-06-05 17:48:08 +0000351 programmer_delay(1000);
hailfinger61949942009-05-09 02:09:45 +0000352 return 0;
hailfinger2c361e42008-05-13 23:03:12 +0000353}
354
355/*
hailfinger2c361e42008-05-13 23:03:12 +0000356 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
357 * Need to read this big flash using firmware cycles 3 byte at a time.
358 */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700359static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000360 unsigned int start, unsigned int len)
hailfinger2c361e42008-05-13 23:03:12 +0000361{
hailfinger2c361e42008-05-13 23:03:12 +0000362 fast_spi = 0;
363
hailfinger94e090c2011-04-27 14:34:08 +0000364 /* FIXME: Check if someone explicitly requested to use IT87 SPI although
365 * the mainboard does not use IT87 SPI translation. This should be done
366 * via a programmer parameter for the internal programmer.
367 */
368 if ((flash->total_size * 1024 > 512 * 1024)) {
hailfinger0f08b7a2009-06-16 08:55:44 +0000369 spi_read_chunked(flash, buf, start, len, 3);
hailfinger2c361e42008-05-13 23:03:12 +0000370 } else {
hailfinger0f08b7a2009-06-16 08:55:44 +0000371 read_memmapped(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000372 }
uwefa98ca12008-10-18 21:14:13 +0000373
hailfinger2c361e42008-05-13 23:03:12 +0000374 return 0;
375}
376
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700377static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf,
stefanctc5eb8a92011-11-23 09:13:48 +0000378 unsigned int start, unsigned int len)
uwefa98ca12008-10-18 21:14:13 +0000379{
hailfingered063f52009-05-09 02:30:21 +0000380 /*
381 * IT8716F only allows maximum of 512 kb SPI chip size for memory
hailfingerdef852d2010-10-27 22:07:11 +0000382 * mapped access. It also can't write more than 1+3+256 bytes at once,
383 * so page_size > 256 bytes needs a fallback.
384 * FIXME: Split too big page writes into chunks IT87* can handle instead
385 * of degrading to single-byte program.
hailfinger94e090c2011-04-27 14:34:08 +0000386 * FIXME: Check if someone explicitly requested to use IT87 SPI although
387 * the mainboard does not use IT87 SPI translation. This should be done
388 * via a programmer parameter for the internal programmer.
hailfingered063f52009-05-09 02:30:21 +0000389 */
hailfinger94e090c2011-04-27 14:34:08 +0000390 if ((flash->total_size * 1024 > 512 * 1024) ||
hailfinger71e1bd42010-10-13 22:26:56 +0000391 (flash->page_size > 256)) {
392 spi_chip_write_1(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000393 } else {
stefanctc5eb8a92011-11-23 09:13:48 +0000394 unsigned int lenhere;
hailfingerc7d06c62010-07-14 16:19:05 +0000395
hailfinger71e1bd42010-10-13 22:26:56 +0000396 if (start % flash->page_size) {
hailfingerdef852d2010-10-27 22:07:11 +0000397 /* start to the end of the page or to start + len,
398 * whichever is smaller.
hailfingerc7d06c62010-07-14 16:19:05 +0000399 */
hailfinger71e1bd42010-10-13 22:26:56 +0000400 lenhere = min(len, flash->page_size - start % flash->page_size);
401 spi_chip_write_1(flash, buf, start, lenhere);
hailfingerc7d06c62010-07-14 16:19:05 +0000402 start += lenhere;
403 len -= lenhere;
404 buf += lenhere;
hailfingere8b674c2009-08-10 02:29:21 +0000405 }
hailfingerc7d06c62010-07-14 16:19:05 +0000406
hailfinger71e1bd42010-10-13 22:26:56 +0000407 while (len >= flash->page_size) {
hailfingerc7d06c62010-07-14 16:19:05 +0000408 it8716f_spi_page_program(flash, buf, start);
hailfinger71e1bd42010-10-13 22:26:56 +0000409 start += flash->page_size;
410 len -= flash->page_size;
411 buf += flash->page_size;
hailfinger2c361e42008-05-13 23:03:12 +0000412 }
hailfingerc7d06c62010-07-14 16:19:05 +0000413 if (len)
hailfinger71e1bd42010-10-13 22:26:56 +0000414 spi_chip_write_1(flash, buf, start, len);
hailfinger2c361e42008-05-13 23:03:12 +0000415 }
uwefa98ca12008-10-18 21:14:13 +0000416
hailfinger2c361e42008-05-13 23:03:12 +0000417 return 0;
418}
hailfinger324a9cc2010-05-26 01:45:41 +0000419
420#endif