| Thomas Gleixner | 1802d0b | 2019-05-27 08:55:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Freescale DSPI controller driver |
| 4 | * |
| 5 | * Copyright (c) 2017 Angelo Dureghello <angelo@sysam.it> |
| Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef SPI_FSL_DSPI_HEADER_H |
| 9 | #define SPI_FSL_DSPI_HEADER_H |
| 10 | |
| 11 | /** |
| 12 | * struct fsl_dspi_platform_data - platform data for the Freescale DSPI driver |
| 13 | * @bus_num: board specific identifier for this DSPI driver. |
| 14 | * @cs_num: number of chip selects supported by this DSPI driver. |
| 15 | */ |
| 16 | struct fsl_dspi_platform_data { |
| 17 | u32 cs_num; |
| 18 | u32 bus_num; |
| 19 | u32 sck_cs_delay; |
| 20 | u32 cs_sck_delay; |
| 21 | }; |
| 22 | |
| 23 | #endif /* SPI_FSL_DSPI_HEADER_H */ |