Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-at91/include/mach/at91_rtc.h |
| 4 | * |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * Copyright (C) SAN People |
| 7 | * |
| 8 | * Real Time Clock (RTC) - System peripheral registers. |
| 9 | * Based on AT91RM9200 datasheet revision E. |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef AT91_RTC_H |
| 13 | #define AT91_RTC_H |
| 14 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 15 | #define AT91_RTC_CR 0x00 /* Control Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 16 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ |
| 17 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ |
| 18 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ |
| 19 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) |
| 20 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) |
| 21 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) |
| 22 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) |
| 23 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ |
| 24 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) |
| 25 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) |
| 26 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) |
| 27 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 28 | #define AT91_RTC_MR 0x04 /* Mode Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 29 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ |
| 30 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 31 | #define AT91_RTC_TIMR 0x08 /* Time Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 32 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ |
| 33 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ |
| 34 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ |
| 35 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ |
| 36 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 37 | #define AT91_RTC_CALR 0x0c /* Calendar Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 38 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ |
| 39 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ |
| 40 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ |
| 41 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ |
| 42 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ |
| 43 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 44 | #define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 45 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ |
| 46 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ |
| 47 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ |
| 48 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 49 | #define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 50 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ |
| 51 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ |
| 52 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 53 | #define AT91_RTC_SR 0x18 /* Status Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 54 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ |
| 55 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ |
| 56 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ |
| 57 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ |
| 58 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ |
| 59 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 60 | #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */ |
| 61 | #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */ |
| 62 | #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ |
Johan Hovold | e24b0bf | 2013-04-05 18:16:34 +0200 | [diff] [blame] | 63 | #define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 64 | |
Jean-Christophe PLAGNIOL-VILLARD | d28bdfc | 2011-11-14 14:24:53 +0800 | [diff] [blame] | 65 | #define AT91_RTC_VER 0x2c /* Valid Entry Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 66 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ |
| 67 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ |
| 68 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ |
| 69 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ |
| 70 | |
| 71 | #endif |