Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 2 | /* |
| 3 | * linux/arch/arm/lib/copy_from_user.S |
| 4 | * |
| 5 | * Author: Nicolas Pitre |
| 6 | * Created: Sep 29, 2005 |
| 7 | * Copyright: MontaVista Software, Inc. |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <linux/linkage.h> |
| 11 | #include <asm/assembler.h> |
Lin Yongting | 279f487 | 2014-11-26 14:38:33 +0100 | [diff] [blame] | 12 | #include <asm/unwind.h> |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * Prototype: |
| 16 | * |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 17 | * size_t arm_copy_from_user(void *to, const void *from, size_t n) |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 18 | * |
| 19 | * Purpose: |
| 20 | * |
| 21 | * copy a block to kernel memory from user memory |
| 22 | * |
| 23 | * Params: |
| 24 | * |
| 25 | * to = kernel memory |
| 26 | * from = user memory |
| 27 | * n = number of bytes to copy |
| 28 | * |
| 29 | * Return value: |
| 30 | * |
| 31 | * Number of bytes NOT copied. |
| 32 | */ |
| 33 | |
Vincent Whitchurch | f441882 | 2018-11-09 10:09:48 +0100 | [diff] [blame] | 34 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 35 | |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 36 | #ifndef CONFIG_THUMB2_KERNEL |
| 37 | #define LDR1W_SHIFT 0 |
| 38 | #else |
| 39 | #define LDR1W_SHIFT 1 |
| 40 | #endif |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 41 | |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 42 | .macro ldr1w ptr reg abort |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 43 | ldrusr \reg, \ptr, 4, abort=\abort |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 44 | .endm |
| 45 | |
| 46 | .macro ldr4w ptr reg1 reg2 reg3 reg4 abort |
| 47 | ldr1w \ptr, \reg1, \abort |
| 48 | ldr1w \ptr, \reg2, \abort |
| 49 | ldr1w \ptr, \reg3, \abort |
| 50 | ldr1w \ptr, \reg4, \abort |
| 51 | .endm |
| 52 | |
| 53 | .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort |
| 54 | ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort |
| 55 | ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort |
| 56 | .endm |
| 57 | |
Vincent Whitchurch | f441882 | 2018-11-09 10:09:48 +0100 | [diff] [blame] | 58 | #else |
| 59 | |
| 60 | #define LDR1W_SHIFT 0 |
| 61 | |
| 62 | .macro ldr1w ptr reg abort |
| 63 | USERL(\abort, W(ldr) \reg, [\ptr], #4) |
| 64 | .endm |
| 65 | |
| 66 | .macro ldr4w ptr reg1 reg2 reg3 reg4 abort |
| 67 | USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}) |
| 68 | .endm |
| 69 | |
| 70 | .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort |
| 71 | USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}) |
| 72 | .endm |
| 73 | |
| 74 | #endif /* CONFIG_CPU_USE_DOMAINS */ |
| 75 | |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 76 | .macro ldr1b ptr reg cond=al abort |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 77 | ldrusr \reg, \ptr, 1, \cond, abort=\abort |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 78 | .endm |
| 79 | |
Vincent Whitchurch | f441882 | 2018-11-09 10:09:48 +0100 | [diff] [blame] | 80 | #define STR1W_SHIFT 0 |
| 81 | |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 82 | .macro str1w ptr reg abort |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 83 | W(str) \reg, [\ptr], #4 |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 84 | .endm |
| 85 | |
| 86 | .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort |
| 87 | stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} |
| 88 | .endm |
| 89 | |
| 90 | .macro str1b ptr reg cond=al abort |
Stefan Agner | a216376 | 2019-02-18 00:54:36 +0100 | [diff] [blame] | 91 | strb\cond \reg, [\ptr], #1 |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 92 | .endm |
| 93 | |
| 94 | .macro enter reg1 reg2 |
| 95 | mov r3, #0 |
| 96 | stmdb sp!, {r0, r2, r3, \reg1, \reg2} |
| 97 | .endm |
| 98 | |
Lin Yongting | 279f487 | 2014-11-26 14:38:33 +0100 | [diff] [blame] | 99 | .macro usave reg1 reg2 |
| 100 | UNWIND( .save {r0, r2, r3, \reg1, \reg2} ) |
| 101 | .endm |
| 102 | |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 103 | .macro exit reg1 reg2 |
| 104 | add sp, sp, #8 |
| 105 | ldmfd sp!, {r0, \reg1, \reg2} |
| 106 | .endm |
| 107 | |
| 108 | .text |
| 109 | |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 110 | ENTRY(arm_copy_from_user) |
Russell King | a3c0f847 | 2018-05-14 09:40:24 +0100 | [diff] [blame] | 111 | #ifdef CONFIG_CPU_SPECTRE |
| 112 | get_thread_info r3 |
| 113 | ldr r3, [r3, #TI_ADDR_LIMIT] |
Julien Thierry | afaf683 | 2018-09-11 10:14:50 +0100 | [diff] [blame] | 114 | uaccess_mask_range_ptr r1, r2, r3, ip |
Russell King | a3c0f847 | 2018-05-14 09:40:24 +0100 | [diff] [blame] | 115 | #endif |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 116 | |
| 117 | #include "copy_template.S" |
| 118 | |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 119 | ENDPROC(arm_copy_from_user) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 120 | |
Russell King | 4260415 | 2010-04-19 10:15:03 +0100 | [diff] [blame] | 121 | .pushsection .fixup,"ax" |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 122 | .align 0 |
| 123 | copy_abort_preamble |
Al Viro | 9134449 | 2016-09-10 16:44:03 -0400 | [diff] [blame] | 124 | ldmfd sp!, {r1, r2, r3} |
| 125 | sub r0, r0, r1 |
| 126 | rsb r0, r0, r2 |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 127 | copy_abort_end |
Russell King | 4260415 | 2010-04-19 10:15:03 +0100 | [diff] [blame] | 128 | .popsection |
Nicolas Pitre | fadab09 | 2005-11-01 19:52:24 +0000 | [diff] [blame] | 129 | |