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Matthew Wilcoxb60503b2011-01-20 12:50:14 -05001/*
2 * Definitions for the NVM Express interface
Matthew Wilcox8757ad62014-04-11 10:37:39 -04003 * Copyright (c) 2011-2014, Intel Corporation.
Matthew Wilcoxb60503b2011-01-20 12:50:14 -05004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050013 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
Christoph Hellwig2812dfe2015-10-09 18:19:20 +020018#include <linux/types.h>
Christoph Hellwig8e412262017-05-17 09:54:27 +020019#include <linux/uuid.h>
Christoph Hellwigeb793e22016-06-13 16:45:25 +020020
21/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256
23
24/* However the max length of a qualified name is another size */
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
Arnav Dawn62346ea2017-07-12 16:11:53 +053035#define NVME_NSID_ALL 0xffffffff
36
Christoph Hellwigeb793e22016-06-13 16:45:25 +020037enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40};
41
42/* Address Family codes for Discovery Log Page entry ADRFAM field */
43enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49};
50
51/* Transport Type codes for Discovery Log Page entry TRTYPE field */
52enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57};
58
59/* Transport Requirements codes for Discovery Log Page entry TREQ field */
60enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64};
65
66/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69enum {
Roland Dreierbf17aa362017-03-01 18:22:01 -080070 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
Christoph Hellwigeb793e22016-06-13 16:45:25 +020072};
73
74/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77enum {
Roland Dreierbf17aa362017-03-01 18:22:01 -080078 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
Christoph Hellwigeb793e22016-06-13 16:45:25 +020083};
84
85/* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88enum {
Roland Dreierbf17aa362017-03-01 18:22:01 -080089 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
Christoph Hellwigeb793e22016-06-13 16:45:25 +020090};
91
Sagi Grimberg7aa1f422017-06-18 16:15:59 +030092#define NVME_AQ_DEPTH 32
Keith Busch38dabe22017-11-07 15:13:10 -070093#define NVME_NR_AEN_COMMANDS 1
94#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95
96/*
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
99 */
100#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
Christoph Hellwig2812dfe2015-10-09 18:19:20 +0200101
Christoph Hellwig7a67cbe2015-11-20 08:58:10 +0100102enum {
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
Wang Sheng-Huia5b714a2016-04-27 20:10:16 +0800106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
Christoph Hellwig7a67cbe2015-11-20 08:58:10 +0100107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
Wang Sheng-Huia5b714a2016-04-27 20:10:16 +0800112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
Christoph Hellwig7a67cbe2015-11-20 08:58:10 +0100113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
Xu Yu97f6ef62017-05-24 16:39:55 +0800115 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500116};
117
Keith Buscha0cadb82012-07-27 13:57:23 -0400118#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
Matthew Wilcox22605f92011-04-19 15:04:20 -0400119#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
Matthew Wilcoxf1938f62011-10-20 17:00:41 -0400120#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
Keith Buschdfbac8c2015-08-10 15:20:40 -0600121#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
Keith Busch8fc23e02012-07-26 11:29:57 -0600122#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
Keith Busch1d090622014-06-23 11:34:01 -0600123#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
Matthew Wilcox22605f92011-04-19 15:04:20 -0400124
Jon Derrick8ffaadf2015-07-20 10:14:09 -0600125#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
127#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
128#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
129
130#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
131#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
132#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
133#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
134#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
135
Christoph Hellwig69cd27e2016-06-06 23:20:45 +0200136/*
137 * Submission and Completion Queue Entry Sizes for the NVM command set.
138 * (In bytes and specified as a power of two (2^n)).
139 */
140#define NVME_NVM_IOSQES 6
141#define NVME_NVM_IOCQES 4
142
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500143enum {
144 NVME_CC_ENABLE = 1 << 0,
145 NVME_CC_CSS_NVM = 0 << 4,
Max Gurtovoyad4e05b2017-08-13 19:21:06 +0300146 NVME_CC_EN_SHIFT = 0,
147 NVME_CC_CSS_SHIFT = 4,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500148 NVME_CC_MPS_SHIFT = 7,
Max Gurtovoyad4e05b2017-08-13 19:21:06 +0300149 NVME_CC_AMS_SHIFT = 11,
150 NVME_CC_SHN_SHIFT = 14,
151 NVME_CC_IOSQES_SHIFT = 16,
152 NVME_CC_IOCQES_SHIFT = 20,
Max Gurtovoy60b43f62017-08-13 19:21:07 +0300153 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
154 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
155 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
Max Gurtovoyad4e05b2017-08-13 19:21:06 +0300156 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
157 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
158 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
159 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
160 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
161 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500162 NVME_CSTS_RDY = 1 << 0,
163 NVME_CSTS_CFS = 1 << 1,
Keith Buschdfbac8c2015-08-10 15:20:40 -0600164 NVME_CSTS_NSSRO = 1 << 4,
Arnav Dawnb6dccf72017-07-12 16:10:40 +0530165 NVME_CSTS_PP = 1 << 5,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500166 NVME_CSTS_SHST_NORMAL = 0 << 2,
167 NVME_CSTS_SHST_OCCUR = 1 << 2,
168 NVME_CSTS_SHST_CMPLT = 2 << 2,
Keith Busch1894d8f2013-07-15 15:02:22 -0600169 NVME_CSTS_SHST_MASK = 3 << 2,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500170};
171
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200172struct nvme_id_power_state {
173 __le16 max_power; /* centiwatts */
174 __u8 rsvd2;
175 __u8 flags;
176 __le32 entry_lat; /* microseconds */
177 __le32 exit_lat; /* microseconds */
178 __u8 read_tput;
179 __u8 read_lat;
180 __u8 write_tput;
181 __u8 write_lat;
182 __le16 idle_power;
183 __u8 idle_scale;
184 __u8 rsvd19;
185 __le16 active_power;
186 __u8 active_work_scale;
187 __u8 rsvd23[9];
188};
189
190enum {
191 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
192 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
193};
194
195struct nvme_id_ctrl {
196 __le16 vid;
197 __le16 ssvid;
198 char sn[20];
199 char mn[40];
200 char fr[8];
201 __u8 rab;
202 __u8 ieee[3];
Christoph Hellwiga446c082016-09-30 13:51:06 +0200203 __u8 cmic;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200204 __u8 mdts;
Christoph Hellwig08c69642015-10-02 15:27:16 +0200205 __le16 cntlid;
206 __le32 ver;
Christoph Hellwig14e974a2016-06-06 23:20:43 +0200207 __le32 rtd3r;
208 __le32 rtd3e;
209 __le32 oaes;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200210 __le32 ctratt;
211 __u8 rsvd100[156];
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200212 __le16 oacs;
213 __u8 acl;
214 __u8 aerl;
215 __u8 frmw;
216 __u8 lpa;
217 __u8 elpe;
218 __u8 npss;
219 __u8 avscc;
220 __u8 apsta;
221 __le16 wctemp;
222 __le16 cctemp;
Christoph Hellwiga446c082016-09-30 13:51:06 +0200223 __le16 mtfa;
224 __le32 hmpre;
225 __le32 hmmin;
226 __u8 tnvmcap[16];
227 __u8 unvmcap[16];
228 __le32 rpmbs;
Guan Junxiong435e8092017-06-13 09:26:15 +0800229 __le16 edstt;
230 __u8 dsto;
231 __u8 fwug;
Sagi Grimberg7b89eae2016-06-13 16:45:27 +0200232 __le16 kas;
Guan Junxiong435e8092017-06-13 09:26:15 +0800233 __le16 hctma;
234 __le16 mntmt;
235 __le16 mxtmt;
236 __le32 sanicap;
Christoph Hellwig044a9df2017-09-11 12:09:28 -0400237 __le32 hmminds;
238 __le16 hmmaxd;
239 __u8 rsvd338[174];
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200240 __u8 sqes;
241 __u8 cqes;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200242 __le16 maxcmd;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200243 __le32 nn;
244 __le16 oncs;
245 __le16 fuses;
246 __u8 fna;
247 __u8 vwc;
248 __le16 awun;
249 __le16 awupf;
250 __u8 nvscc;
251 __u8 rsvd531;
252 __le16 acwu;
253 __u8 rsvd534[2];
254 __le32 sgls;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200255 __u8 rsvd540[228];
256 char subnqn[256];
257 __u8 rsvd1024[768];
258 __le32 ioccsz;
259 __le32 iorcsz;
260 __le16 icdoff;
261 __u8 ctrattr;
262 __u8 msdbd;
263 __u8 rsvd1804[244];
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200264 struct nvme_id_power_state psd[32];
265 __u8 vs[1024];
266};
267
268enum {
269 NVME_CTRL_ONCS_COMPARE = 1 << 0,
270 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
271 NVME_CTRL_ONCS_DSM = 1 << 2,
Chaitanya Kulkarni3b7c33b2016-11-30 12:29:00 -0800272 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
Jon Derrickdbf86b32017-08-16 09:51:29 +0200273 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200274 NVME_CTRL_VWC_PRESENT = 1 << 0,
Scott Bauer8a9ae522017-02-17 13:59:40 +0100275 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
Jens Axboef5d11842017-06-27 12:03:06 -0600276 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
Changpeng Liu223694b2017-08-31 11:22:49 +0800277 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
Keith Busch84fef622017-11-07 10:28:32 -0700278 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200279};
280
281struct nvme_lbaf {
282 __le16 ms;
283 __u8 ds;
284 __u8 rp;
285};
286
287struct nvme_id_ns {
288 __le64 nsze;
289 __le64 ncap;
290 __le64 nuse;
291 __u8 nsfeat;
292 __u8 nlbaf;
293 __u8 flbas;
294 __u8 mc;
295 __u8 dpc;
296 __u8 dps;
297 __u8 nmic;
298 __u8 rescap;
299 __u8 fpi;
300 __u8 rsvd33;
301 __le16 nawun;
302 __le16 nawupf;
303 __le16 nacwu;
304 __le16 nabsn;
305 __le16 nabo;
306 __le16 nabspf;
Scott Bauer6b8190d2017-06-15 10:44:30 -0600307 __le16 noiob;
Christoph Hellwiga446c082016-09-30 13:51:06 +0200308 __u8 nvmcap[16];
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200309 __u8 rsvd64[40];
310 __u8 nguid[16];
311 __u8 eui64[8];
312 struct nvme_lbaf lbaf[16];
313 __u8 rsvd192[192];
314 __u8 vs[3712];
315};
316
317enum {
Christoph Hellwig329dd762016-09-30 13:51:08 +0200318 NVME_ID_CNS_NS = 0x00,
319 NVME_ID_CNS_CTRL = 0x01,
320 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
Johannes Thumshirnaf8b86e2017-06-07 11:45:30 +0200321 NVME_ID_CNS_NS_DESC_LIST = 0x03,
Christoph Hellwig329dd762016-09-30 13:51:08 +0200322 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
323 NVME_ID_CNS_NS_PRESENT = 0x11,
324 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
325 NVME_ID_CNS_CTRL_LIST = 0x13,
326};
327
328enum {
Jens Axboef5d11842017-06-27 12:03:06 -0600329 NVME_DIR_IDENTIFY = 0x00,
330 NVME_DIR_STREAMS = 0x01,
331 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
332 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
333 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
334 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
335 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
336 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
337 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
338 NVME_DIR_ENDIR = 0x01,
339};
340
341enum {
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200342 NVME_NS_FEAT_THIN = 1 << 0,
343 NVME_NS_FLBAS_LBA_MASK = 0xf,
344 NVME_NS_FLBAS_META_EXT = 0x10,
345 NVME_LBAF_RP_BEST = 0,
346 NVME_LBAF_RP_BETTER = 1,
347 NVME_LBAF_RP_GOOD = 2,
348 NVME_LBAF_RP_DEGRADED = 3,
349 NVME_NS_DPC_PI_LAST = 1 << 4,
350 NVME_NS_DPC_PI_FIRST = 1 << 3,
351 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
352 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
353 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
354 NVME_NS_DPS_PI_FIRST = 1 << 3,
355 NVME_NS_DPS_PI_MASK = 0x7,
356 NVME_NS_DPS_PI_TYPE1 = 1,
357 NVME_NS_DPS_PI_TYPE2 = 2,
358 NVME_NS_DPS_PI_TYPE3 = 3,
359};
360
Johannes Thumshirnaf8b86e2017-06-07 11:45:30 +0200361struct nvme_ns_id_desc {
362 __u8 nidt;
363 __u8 nidl;
364 __le16 reserved;
365};
366
367#define NVME_NIDT_EUI64_LEN 8
368#define NVME_NIDT_NGUID_LEN 16
369#define NVME_NIDT_UUID_LEN 16
370
371enum {
372 NVME_NIDT_EUI64 = 0x01,
373 NVME_NIDT_NGUID = 0x02,
374 NVME_NIDT_UUID = 0x03,
375};
376
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200377struct nvme_smart_log {
378 __u8 critical_warning;
379 __u8 temperature[2];
380 __u8 avail_spare;
381 __u8 spare_thresh;
382 __u8 percent_used;
383 __u8 rsvd6[26];
384 __u8 data_units_read[16];
385 __u8 data_units_written[16];
386 __u8 host_reads[16];
387 __u8 host_writes[16];
388 __u8 ctrl_busy_time[16];
389 __u8 power_cycles[16];
390 __u8 power_on_hours[16];
391 __u8 unsafe_shutdowns[16];
392 __u8 media_errors[16];
393 __u8 num_err_log_entries[16];
394 __le32 warning_temp_time;
395 __le32 critical_comp_time;
396 __le16 temp_sensor[8];
397 __u8 rsvd216[296];
398};
399
Arnav Dawnb6dccf72017-07-12 16:10:40 +0530400struct nvme_fw_slot_info_log {
401 __u8 afi;
402 __u8 rsvd1[7];
403 __le64 frs[7];
404 __u8 rsvd64[448];
405};
406
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200407enum {
Keith Busch84fef622017-11-07 10:28:32 -0700408 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
409 NVME_CMD_EFFECTS_LBCC = 1 << 1,
410 NVME_CMD_EFFECTS_NCC = 1 << 2,
411 NVME_CMD_EFFECTS_NIC = 1 << 3,
412 NVME_CMD_EFFECTS_CCC = 1 << 4,
413 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
414};
415
416struct nvme_effects_log {
417 __le32 acs[256];
418 __le32 iocs[256];
419 __u8 resv[2048];
420};
421
422enum {
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200423 NVME_SMART_CRIT_SPARE = 1 << 0,
424 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
425 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
426 NVME_SMART_CRIT_MEDIA = 1 << 3,
427 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
428};
429
430enum {
431 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
Arnav Dawnb6dccf72017-07-12 16:10:40 +0530432 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200433};
434
435struct nvme_lba_range_type {
436 __u8 type;
437 __u8 attributes;
438 __u8 rsvd2[14];
439 __u64 slba;
440 __u64 nlb;
441 __u8 guid[16];
442 __u8 rsvd48[16];
443};
444
445enum {
446 NVME_LBART_TYPE_FS = 0x01,
447 NVME_LBART_TYPE_RAID = 0x02,
448 NVME_LBART_TYPE_CACHE = 0x03,
449 NVME_LBART_TYPE_SWAP = 0x04,
450
451 NVME_LBART_ATTRIB_TEMP = 1 << 0,
452 NVME_LBART_ATTRIB_HIDE = 1 << 1,
453};
454
455struct nvme_reservation_status {
456 __le32 gen;
457 __u8 rtype;
458 __u8 regctl[2];
459 __u8 resv5[2];
460 __u8 ptpls;
461 __u8 resv10[13];
462 struct {
463 __le16 cntlid;
464 __u8 rcsts;
465 __u8 resv3[5];
466 __le64 hostid;
467 __le64 rkey;
468 } regctl_ds[];
469};
470
Christoph Hellwig79f370e2016-06-06 23:20:46 +0200471enum nvme_async_event_type {
472 NVME_AER_TYPE_ERROR = 0,
473 NVME_AER_TYPE_SMART = 1,
474 NVME_AER_TYPE_NOTICE = 2,
475};
476
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200477/* I/O commands */
478
479enum nvme_opcode {
480 nvme_cmd_flush = 0x00,
481 nvme_cmd_write = 0x01,
482 nvme_cmd_read = 0x02,
483 nvme_cmd_write_uncor = 0x04,
484 nvme_cmd_compare = 0x05,
485 nvme_cmd_write_zeroes = 0x08,
486 nvme_cmd_dsm = 0x09,
487 nvme_cmd_resv_register = 0x0d,
488 nvme_cmd_resv_report = 0x0e,
489 nvme_cmd_resv_acquire = 0x11,
490 nvme_cmd_resv_release = 0x15,
491};
492
James Smart3972be22016-06-06 23:20:47 +0200493/*
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200494 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
495 *
496 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
497 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
James Smartd85cf202017-09-07 13:20:23 -0700498 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200499 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
500 * request subtype
501 */
502enum {
503 NVME_SGL_FMT_ADDRESS = 0x00,
504 NVME_SGL_FMT_OFFSET = 0x01,
James Smartd85cf202017-09-07 13:20:23 -0700505 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200506 NVME_SGL_FMT_INVALIDATE = 0x0f,
507};
508
509/*
510 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
511 *
512 * For struct nvme_sgl_desc:
513 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
514 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
515 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
516 *
517 * For struct nvme_keyed_sgl_desc:
518 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
James Smartd85cf202017-09-07 13:20:23 -0700519 *
520 * Transport-specific SGL types:
521 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200522 */
523enum {
524 NVME_SGL_FMT_DATA_DESC = 0x00,
525 NVME_SGL_FMT_SEG_DESC = 0x02,
526 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
527 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
James Smartd85cf202017-09-07 13:20:23 -0700528 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200529};
530
531struct nvme_sgl_desc {
532 __le64 addr;
533 __le32 length;
534 __u8 rsvd[3];
535 __u8 type;
536};
537
538struct nvme_keyed_sgl_desc {
539 __le64 addr;
540 __u8 length[3];
541 __u8 key[4];
542 __u8 type;
543};
544
545union nvme_data_ptr {
546 struct {
547 __le64 prp1;
548 __le64 prp2;
549 };
550 struct nvme_sgl_desc sgl;
551 struct nvme_keyed_sgl_desc ksgl;
552};
553
554/*
James Smart3972be22016-06-06 23:20:47 +0200555 * Lowest two bits of our flags field (FUSE field in the spec):
556 *
557 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
558 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
559 *
560 * Highest two bits in our flags field (PSDT field in the spec):
561 *
562 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
563 * If used, MPTR contains addr of single physical buffer (byte aligned).
564 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
565 * If used, MPTR contains an address of an SGL segment containing
566 * exactly 1 SGL descriptor (qword aligned).
567 */
568enum {
569 NVME_CMD_FUSE_FIRST = (1 << 0),
570 NVME_CMD_FUSE_SECOND = (1 << 1),
571
572 NVME_CMD_SGL_METABUF = (1 << 6),
573 NVME_CMD_SGL_METASEG = (1 << 7),
574 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
575};
576
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200577struct nvme_common_command {
578 __u8 opcode;
579 __u8 flags;
580 __u16 command_id;
581 __le32 nsid;
582 __le32 cdw2[2];
583 __le64 metadata;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200584 union nvme_data_ptr dptr;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200585 __le32 cdw10[6];
586};
587
588struct nvme_rw_command {
589 __u8 opcode;
590 __u8 flags;
591 __u16 command_id;
592 __le32 nsid;
593 __u64 rsvd2;
594 __le64 metadata;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200595 union nvme_data_ptr dptr;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200596 __le64 slba;
597 __le16 length;
598 __le16 control;
599 __le32 dsmgmt;
600 __le32 reftag;
601 __le16 apptag;
602 __le16 appmask;
603};
604
605enum {
606 NVME_RW_LR = 1 << 15,
607 NVME_RW_FUA = 1 << 14,
608 NVME_RW_DSM_FREQ_UNSPEC = 0,
609 NVME_RW_DSM_FREQ_TYPICAL = 1,
610 NVME_RW_DSM_FREQ_RARE = 2,
611 NVME_RW_DSM_FREQ_READS = 3,
612 NVME_RW_DSM_FREQ_WRITES = 4,
613 NVME_RW_DSM_FREQ_RW = 5,
614 NVME_RW_DSM_FREQ_ONCE = 6,
615 NVME_RW_DSM_FREQ_PREFETCH = 7,
616 NVME_RW_DSM_FREQ_TEMP = 8,
617 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
618 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
619 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
620 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
621 NVME_RW_DSM_SEQ_REQ = 1 << 6,
622 NVME_RW_DSM_COMPRESSED = 1 << 7,
623 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
624 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
625 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
626 NVME_RW_PRINFO_PRACT = 1 << 13,
Jens Axboef5d11842017-06-27 12:03:06 -0600627 NVME_RW_DTYPE_STREAMS = 1 << 4,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200628};
629
630struct nvme_dsm_cmd {
631 __u8 opcode;
632 __u8 flags;
633 __u16 command_id;
634 __le32 nsid;
635 __u64 rsvd2[2];
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200636 union nvme_data_ptr dptr;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200637 __le32 nr;
638 __le32 attributes;
639 __u32 rsvd12[4];
640};
641
642enum {
643 NVME_DSMGMT_IDR = 1 << 0,
644 NVME_DSMGMT_IDW = 1 << 1,
645 NVME_DSMGMT_AD = 1 << 2,
646};
647
Christoph Hellwigb35ba012017-02-08 14:46:50 +0100648#define NVME_DSM_MAX_RANGES 256
649
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200650struct nvme_dsm_range {
651 __le32 cattr;
652 __le32 nlb;
653 __le64 slba;
654};
655
Chaitanya Kulkarni3b7c33b2016-11-30 12:29:00 -0800656struct nvme_write_zeroes_cmd {
657 __u8 opcode;
658 __u8 flags;
659 __u16 command_id;
660 __le32 nsid;
661 __u64 rsvd2;
662 __le64 metadata;
663 union nvme_data_ptr dptr;
664 __le64 slba;
665 __le16 length;
666 __le16 control;
667 __le32 dsmgmt;
668 __le32 reftag;
669 __le16 apptag;
670 __le16 appmask;
671};
672
Andy Lutomirskic5552fd2017-02-07 10:08:45 -0800673/* Features */
674
675struct nvme_feat_auto_pst {
676 __le64 entries[32];
677};
678
Christoph Hellwig39673e12017-01-09 15:36:28 +0100679enum {
680 NVME_HOST_MEM_ENABLE = (1 << 0),
681 NVME_HOST_MEM_RETURN = (1 << 1),
682};
683
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200684/* Admin commands */
685
686enum nvme_admin_opcode {
687 nvme_admin_delete_sq = 0x00,
688 nvme_admin_create_sq = 0x01,
689 nvme_admin_get_log_page = 0x02,
690 nvme_admin_delete_cq = 0x04,
691 nvme_admin_create_cq = 0x05,
692 nvme_admin_identify = 0x06,
693 nvme_admin_abort_cmd = 0x08,
694 nvme_admin_set_features = 0x09,
695 nvme_admin_get_features = 0x0a,
696 nvme_admin_async_event = 0x0c,
Christoph Hellwiga446c082016-09-30 13:51:06 +0200697 nvme_admin_ns_mgmt = 0x0d,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200698 nvme_admin_activate_fw = 0x10,
699 nvme_admin_download_fw = 0x11,
Christoph Hellwiga446c082016-09-30 13:51:06 +0200700 nvme_admin_ns_attach = 0x15,
Sagi Grimberg7b89eae2016-06-13 16:45:27 +0200701 nvme_admin_keep_alive = 0x18,
Jens Axboef5d11842017-06-27 12:03:06 -0600702 nvme_admin_directive_send = 0x19,
703 nvme_admin_directive_recv = 0x1a,
Helen Koikef9f38e32017-04-10 12:51:07 -0300704 nvme_admin_dbbuf = 0x7C,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200705 nvme_admin_format_nvm = 0x80,
706 nvme_admin_security_send = 0x81,
707 nvme_admin_security_recv = 0x82,
Keith Busch84fef622017-11-07 10:28:32 -0700708 nvme_admin_sanitize_nvm = 0x84,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200709};
710
711enum {
712 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
713 NVME_CQ_IRQ_ENABLED = (1 << 1),
714 NVME_SQ_PRIO_URGENT = (0 << 1),
715 NVME_SQ_PRIO_HIGH = (1 << 1),
716 NVME_SQ_PRIO_MEDIUM = (2 << 1),
717 NVME_SQ_PRIO_LOW = (3 << 1),
718 NVME_FEAT_ARBITRATION = 0x01,
719 NVME_FEAT_POWER_MGMT = 0x02,
720 NVME_FEAT_LBA_RANGE = 0x03,
721 NVME_FEAT_TEMP_THRESH = 0x04,
722 NVME_FEAT_ERR_RECOVERY = 0x05,
723 NVME_FEAT_VOLATILE_WC = 0x06,
724 NVME_FEAT_NUM_QUEUES = 0x07,
725 NVME_FEAT_IRQ_COALESCE = 0x08,
726 NVME_FEAT_IRQ_CONFIG = 0x09,
727 NVME_FEAT_WRITE_ATOMIC = 0x0a,
728 NVME_FEAT_ASYNC_EVENT = 0x0b,
729 NVME_FEAT_AUTO_PST = 0x0c,
Christoph Hellwiga446c082016-09-30 13:51:06 +0200730 NVME_FEAT_HOST_MEM_BUF = 0x0d,
Jon Derrickdbf86b32017-08-16 09:51:29 +0200731 NVME_FEAT_TIMESTAMP = 0x0e,
Sagi Grimberg7b89eae2016-06-13 16:45:27 +0200732 NVME_FEAT_KATO = 0x0f,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200733 NVME_FEAT_SW_PROGRESS = 0x80,
734 NVME_FEAT_HOST_ID = 0x81,
735 NVME_FEAT_RESV_MASK = 0x82,
736 NVME_FEAT_RESV_PERSIST = 0x83,
737 NVME_LOG_ERROR = 0x01,
738 NVME_LOG_SMART = 0x02,
739 NVME_LOG_FW_SLOT = 0x03,
Keith Busch84fef622017-11-07 10:28:32 -0700740 NVME_LOG_CMD_EFFECTS = 0x05,
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200741 NVME_LOG_DISC = 0x70,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200742 NVME_LOG_RESERVATION = 0x80,
743 NVME_FWACT_REPL = (0 << 3),
744 NVME_FWACT_REPL_ACTV = (1 << 3),
745 NVME_FWACT_ACTV = (2 << 3),
746};
747
748struct nvme_identify {
749 __u8 opcode;
750 __u8 flags;
751 __u16 command_id;
752 __le32 nsid;
753 __u64 rsvd2[2];
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200754 union nvme_data_ptr dptr;
Parav Pandit986994a2017-01-26 17:17:28 +0200755 __u8 cns;
756 __u8 rsvd3;
757 __le16 ctrlid;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200758 __u32 rsvd11[5];
759};
760
Johannes Thumshirn0add5e82017-06-07 11:45:29 +0200761#define NVME_IDENTIFY_DATA_SIZE 4096
762
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200763struct nvme_features {
764 __u8 opcode;
765 __u8 flags;
766 __u16 command_id;
767 __le32 nsid;
768 __u64 rsvd2[2];
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200769 union nvme_data_ptr dptr;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200770 __le32 fid;
771 __le32 dword11;
Arnav Dawnb85cf732017-05-12 17:12:03 +0200772 __le32 dword12;
773 __le32 dword13;
774 __le32 dword14;
775 __le32 dword15;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200776};
777
Christoph Hellwig39673e12017-01-09 15:36:28 +0100778struct nvme_host_mem_buf_desc {
779 __le64 addr;
780 __le32 size;
781 __u32 rsvd;
782};
783
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200784struct nvme_create_cq {
785 __u8 opcode;
786 __u8 flags;
787 __u16 command_id;
788 __u32 rsvd1[5];
789 __le64 prp1;
790 __u64 rsvd8;
791 __le16 cqid;
792 __le16 qsize;
793 __le16 cq_flags;
794 __le16 irq_vector;
795 __u32 rsvd12[4];
796};
797
798struct nvme_create_sq {
799 __u8 opcode;
800 __u8 flags;
801 __u16 command_id;
802 __u32 rsvd1[5];
803 __le64 prp1;
804 __u64 rsvd8;
805 __le16 sqid;
806 __le16 qsize;
807 __le16 sq_flags;
808 __le16 cqid;
809 __u32 rsvd12[4];
810};
811
812struct nvme_delete_queue {
813 __u8 opcode;
814 __u8 flags;
815 __u16 command_id;
816 __u32 rsvd1[9];
817 __le16 qid;
818 __u16 rsvd10;
819 __u32 rsvd11[5];
820};
821
822struct nvme_abort_cmd {
823 __u8 opcode;
824 __u8 flags;
825 __u16 command_id;
826 __u32 rsvd1[9];
827 __le16 sqid;
828 __u16 cid;
829 __u32 rsvd11[5];
830};
831
832struct nvme_download_firmware {
833 __u8 opcode;
834 __u8 flags;
835 __u16 command_id;
836 __u32 rsvd1[5];
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200837 union nvme_data_ptr dptr;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +0200838 __le32 numd;
839 __le32 offset;
840 __u32 rsvd12[4];
841};
842
843struct nvme_format_cmd {
844 __u8 opcode;
845 __u8 flags;
846 __u16 command_id;
847 __le32 nsid;
848 __u64 rsvd2[4];
849 __le32 cdw10;
850 __u32 rsvd11[5];
851};
852
Armen Baloyan725b3582016-06-06 23:20:44 +0200853struct nvme_get_log_page_command {
854 __u8 opcode;
855 __u8 flags;
856 __u16 command_id;
857 __le32 nsid;
858 __u64 rsvd2[2];
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200859 union nvme_data_ptr dptr;
Armen Baloyan725b3582016-06-06 23:20:44 +0200860 __u8 lid;
861 __u8 rsvd10;
862 __le16 numdl;
863 __le16 numdu;
864 __u16 rsvd11;
865 __le32 lpol;
866 __le32 lpou;
867 __u32 rsvd14[2];
868};
869
Jens Axboef5d11842017-06-27 12:03:06 -0600870struct nvme_directive_cmd {
871 __u8 opcode;
872 __u8 flags;
873 __u16 command_id;
874 __le32 nsid;
875 __u64 rsvd2[2];
876 union nvme_data_ptr dptr;
877 __le32 numd;
878 __u8 doper;
879 __u8 dtype;
880 __le16 dspec;
881 __u8 endir;
882 __u8 tdtype;
883 __u16 rsvd15;
884
885 __u32 rsvd16[3];
886};
887
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200888/*
889 * Fabrics subcommands.
890 */
891enum nvmf_fabrics_opcode {
892 nvme_fabrics_command = 0x7f,
893};
894
895enum nvmf_capsule_command {
896 nvme_fabrics_type_property_set = 0x00,
897 nvme_fabrics_type_connect = 0x01,
898 nvme_fabrics_type_property_get = 0x04,
899};
900
901struct nvmf_common_command {
902 __u8 opcode;
903 __u8 resv1;
904 __u16 command_id;
905 __u8 fctype;
906 __u8 resv2[35];
907 __u8 ts[24];
908};
909
910/*
911 * The legal cntlid range a NVMe Target will provide.
912 * Note that cntlid of value 0 is considered illegal in the fabrics world.
913 * Devices based on earlier specs did not have the subsystem concept;
914 * therefore, those devices had their cntlid value set to 0 as a result.
915 */
916#define NVME_CNTLID_MIN 1
917#define NVME_CNTLID_MAX 0xffef
918#define NVME_CNTLID_DYNAMIC 0xffff
919
920#define MAX_DISC_LOGS 255
921
922/* Discovery log page entry */
923struct nvmf_disc_rsp_page_entry {
924 __u8 trtype;
925 __u8 adrfam;
Christoph Hellwiga446c082016-09-30 13:51:06 +0200926 __u8 subtype;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200927 __u8 treq;
928 __le16 portid;
929 __le16 cntlid;
930 __le16 asqsz;
931 __u8 resv8[22];
932 char trsvcid[NVMF_TRSVCID_SIZE];
933 __u8 resv64[192];
934 char subnqn[NVMF_NQN_FIELD_LEN];
935 char traddr[NVMF_TRADDR_SIZE];
936 union tsas {
937 char common[NVMF_TSAS_SIZE];
938 struct rdma {
939 __u8 qptype;
940 __u8 prtype;
941 __u8 cms;
942 __u8 resv3[5];
943 __u16 pkey;
944 __u8 resv10[246];
945 } rdma;
946 } tsas;
947};
948
949/* Discovery log page header */
950struct nvmf_disc_rsp_page_hdr {
951 __le64 genctr;
952 __le64 numrec;
953 __le16 recfmt;
954 __u8 resv14[1006];
955 struct nvmf_disc_rsp_page_entry entries[0];
956};
957
958struct nvmf_connect_command {
959 __u8 opcode;
960 __u8 resv1;
961 __u16 command_id;
962 __u8 fctype;
963 __u8 resv2[19];
964 union nvme_data_ptr dptr;
965 __le16 recfmt;
966 __le16 qid;
967 __le16 sqsize;
968 __u8 cattr;
969 __u8 resv3;
970 __le32 kato;
971 __u8 resv4[12];
972};
973
974struct nvmf_connect_data {
Christoph Hellwig8e412262017-05-17 09:54:27 +0200975 uuid_t hostid;
Christoph Hellwigeb793e22016-06-13 16:45:25 +0200976 __le16 cntlid;
977 char resv4[238];
978 char subsysnqn[NVMF_NQN_FIELD_LEN];
979 char hostnqn[NVMF_NQN_FIELD_LEN];
980 char resv5[256];
981};
982
983struct nvmf_property_set_command {
984 __u8 opcode;
985 __u8 resv1;
986 __u16 command_id;
987 __u8 fctype;
988 __u8 resv2[35];
989 __u8 attrib;
990 __u8 resv3[3];
991 __le32 offset;
992 __le64 value;
993 __u8 resv4[8];
994};
995
996struct nvmf_property_get_command {
997 __u8 opcode;
998 __u8 resv1;
999 __u16 command_id;
1000 __u8 fctype;
1001 __u8 resv2[35];
1002 __u8 attrib;
1003 __u8 resv3[3];
1004 __le32 offset;
1005 __u8 resv4[16];
1006};
1007
Helen Koikef9f38e32017-04-10 12:51:07 -03001008struct nvme_dbbuf {
1009 __u8 opcode;
1010 __u8 flags;
1011 __u16 command_id;
1012 __u32 rsvd1[5];
1013 __le64 prp1;
1014 __le64 prp2;
1015 __u32 rsvd12[6];
1016};
1017
Jens Axboef5d11842017-06-27 12:03:06 -06001018struct streams_directive_params {
Christoph Hellwigdc1a0af2017-07-14 11:12:09 +02001019 __le16 msl;
1020 __le16 nssa;
1021 __le16 nsso;
Jens Axboef5d11842017-06-27 12:03:06 -06001022 __u8 rsvd[10];
Christoph Hellwigdc1a0af2017-07-14 11:12:09 +02001023 __le32 sws;
1024 __le16 sgs;
1025 __le16 nsa;
1026 __le16 nso;
Jens Axboef5d11842017-06-27 12:03:06 -06001027 __u8 rsvd2[6];
1028};
1029
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001030struct nvme_command {
1031 union {
1032 struct nvme_common_command common;
1033 struct nvme_rw_command rw;
1034 struct nvme_identify identify;
1035 struct nvme_features features;
1036 struct nvme_create_cq create_cq;
1037 struct nvme_create_sq create_sq;
1038 struct nvme_delete_queue delete_queue;
1039 struct nvme_download_firmware dlfw;
1040 struct nvme_format_cmd format;
1041 struct nvme_dsm_cmd dsm;
Chaitanya Kulkarni3b7c33b2016-11-30 12:29:00 -08001042 struct nvme_write_zeroes_cmd write_zeroes;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001043 struct nvme_abort_cmd abort;
Armen Baloyan725b3582016-06-06 23:20:44 +02001044 struct nvme_get_log_page_command get_log_page;
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001045 struct nvmf_common_command fabrics;
1046 struct nvmf_connect_command connect;
1047 struct nvmf_property_set_command prop_set;
1048 struct nvmf_property_get_command prop_get;
Helen Koikef9f38e32017-04-10 12:51:07 -03001049 struct nvme_dbbuf dbbuf;
Jens Axboef5d11842017-06-27 12:03:06 -06001050 struct nvme_directive_cmd directive;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001051 };
1052};
1053
Christoph Hellwig7a5abb42016-06-06 23:20:49 +02001054static inline bool nvme_is_write(struct nvme_command *cmd)
1055{
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001056 /*
1057 * What a mess...
1058 *
1059 * Why can't we simply have a Fabrics In and Fabrics out command?
1060 */
1061 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
Jon Derrick2fd41672017-07-12 10:58:19 -06001062 return cmd->fabrics.fctype & 1;
Christoph Hellwig7a5abb42016-06-06 23:20:49 +02001063 return cmd->common.opcode & 1;
1064}
1065
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001066enum {
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001067 /*
1068 * Generic Command Status:
1069 */
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001070 NVME_SC_SUCCESS = 0x0,
1071 NVME_SC_INVALID_OPCODE = 0x1,
1072 NVME_SC_INVALID_FIELD = 0x2,
1073 NVME_SC_CMDID_CONFLICT = 0x3,
1074 NVME_SC_DATA_XFER_ERROR = 0x4,
1075 NVME_SC_POWER_LOSS = 0x5,
1076 NVME_SC_INTERNAL = 0x6,
1077 NVME_SC_ABORT_REQ = 0x7,
1078 NVME_SC_ABORT_QUEUE = 0x8,
1079 NVME_SC_FUSED_FAIL = 0x9,
1080 NVME_SC_FUSED_MISSING = 0xa,
1081 NVME_SC_INVALID_NS = 0xb,
1082 NVME_SC_CMD_SEQ_ERROR = 0xc,
1083 NVME_SC_SGL_INVALID_LAST = 0xd,
1084 NVME_SC_SGL_INVALID_COUNT = 0xe,
1085 NVME_SC_SGL_INVALID_DATA = 0xf,
1086 NVME_SC_SGL_INVALID_METADATA = 0x10,
1087 NVME_SC_SGL_INVALID_TYPE = 0x11,
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001088
1089 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1090 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1091
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001092 NVME_SC_LBA_RANGE = 0x80,
1093 NVME_SC_CAP_EXCEEDED = 0x81,
1094 NVME_SC_NS_NOT_READY = 0x82,
1095 NVME_SC_RESERVATION_CONFLICT = 0x83,
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001096
1097 /*
1098 * Command Specific Status:
1099 */
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001100 NVME_SC_CQ_INVALID = 0x100,
1101 NVME_SC_QID_INVALID = 0x101,
1102 NVME_SC_QUEUE_SIZE = 0x102,
1103 NVME_SC_ABORT_LIMIT = 0x103,
1104 NVME_SC_ABORT_MISSING = 0x104,
1105 NVME_SC_ASYNC_LIMIT = 0x105,
1106 NVME_SC_FIRMWARE_SLOT = 0x106,
1107 NVME_SC_FIRMWARE_IMAGE = 0x107,
1108 NVME_SC_INVALID_VECTOR = 0x108,
1109 NVME_SC_INVALID_LOG_PAGE = 0x109,
1110 NVME_SC_INVALID_FORMAT = 0x10a,
Christoph Hellwiga446c082016-09-30 13:51:06 +02001111 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001112 NVME_SC_INVALID_QUEUE = 0x10c,
1113 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1114 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1115 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
Christoph Hellwiga446c082016-09-30 13:51:06 +02001116 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1117 NVME_SC_FW_NEEDS_RESET = 0x111,
1118 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1119 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1120 NVME_SC_OVERLAPPING_RANGE = 0x114,
1121 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1122 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1123 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1124 NVME_SC_NS_IS_PRIVATE = 0x119,
1125 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1126 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1127 NVME_SC_CTRL_LIST_INVALID = 0x11c,
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001128
1129 /*
1130 * I/O Command Set Specific - NVM commands:
1131 */
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001132 NVME_SC_BAD_ATTRIBUTES = 0x180,
1133 NVME_SC_INVALID_PI = 0x181,
1134 NVME_SC_READ_ONLY = 0x182,
Chaitanya Kulkarni3b7c33b2016-11-30 12:29:00 -08001135 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001136
1137 /*
1138 * I/O Command Set Specific - Fabrics commands:
1139 */
1140 NVME_SC_CONNECT_FORMAT = 0x180,
1141 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1142 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1143 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1144 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1145
1146 NVME_SC_DISCOVERY_RESTART = 0x190,
1147 NVME_SC_AUTH_REQUIRED = 0x191,
1148
1149 /*
1150 * Media and Data Integrity Errors:
1151 */
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001152 NVME_SC_WRITE_FAULT = 0x280,
1153 NVME_SC_READ_ERROR = 0x281,
1154 NVME_SC_GUARD_CHECK = 0x282,
1155 NVME_SC_APPTAG_CHECK = 0x283,
1156 NVME_SC_REFTAG_CHECK = 0x284,
1157 NVME_SC_COMPARE_FAILED = 0x285,
1158 NVME_SC_ACCESS_DENIED = 0x286,
Christoph Hellwiga446c082016-09-30 13:51:06 +02001159 NVME_SC_UNWRITTEN_BLOCK = 0x287,
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001160
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001161 NVME_SC_DNR = 0x4000,
1162};
1163
1164struct nvme_completion {
Christoph Hellwigeb793e22016-06-13 16:45:25 +02001165 /*
1166 * Used by Admin and Fabrics commands to return data:
1167 */
Christoph Hellwigd49187e2016-11-10 07:32:33 -08001168 union nvme_result {
1169 __le16 u16;
1170 __le32 u32;
1171 __le64 u64;
1172 } result;
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001173 __le16 sq_head; /* how much of this queue may be reclaimed */
1174 __le16 sq_id; /* submission queue that generated this entry */
1175 __u16 command_id; /* of the command which completed */
1176 __le16 status; /* did the command fail, and if so, why? */
1177};
1178
Gabriel Krisman Bertazi8ef20742016-10-19 09:51:05 -06001179#define NVME_VS(major, minor, tertiary) \
1180 (((major) << 16) | ((minor) << 8) | (tertiary))
Christoph Hellwig9d99a8d2015-10-02 15:25:49 +02001181
Johannes Thumshirnc61d7882017-06-07 11:45:36 +02001182#define NVME_MAJOR(ver) ((ver) >> 16)
1183#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1184#define NVME_TERTIARY(ver) ((ver) & 0xff)
1185
Matthew Wilcoxb60503b2011-01-20 12:50:14 -05001186#endif /* _LINUX_NVME_H */