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Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
Andrei Konovalovae918c02007-07-17 04:04:11 -07002 * Xilinx SPI controller driver (master mode only)
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
Grant Likely8fd88212010-10-14 09:04:29 -06007 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
10
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
Andrei Konovalovae918c02007-07-17 04:04:11 -070014 */
15
16#include <linux/module.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070017#include <linux/interrupt.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060018#include <linux/of.h>
Grant Likely8fd88212010-10-14 09:04:29 -060019#include <linux/platform_device.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070020#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010022#include <linux/spi/xilinx_spi.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060023#include <linux/io.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010024
Ricardo Ribaldaeb25f162015-01-28 20:53:39 +010025#define XILINX_SPI_MAX_CS 32
26
David Brownellfc3ba952007-08-30 23:56:24 -070027#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070028
29/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
30 * Product Specification", DS464
31 */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010032#define XSPI_CR_OFFSET 0x60 /* Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070033
Michal Simek082339b2013-06-04 16:02:36 +020034#define XSPI_CR_LOOP 0x01
Andrei Konovalovae918c02007-07-17 04:04:11 -070035#define XSPI_CR_ENABLE 0x02
36#define XSPI_CR_MASTER_MODE 0x04
37#define XSPI_CR_CPOL 0x08
38#define XSPI_CR_CPHA 0x10
Ricardo Ribalda Delgadobca690d2015-01-23 17:08:33 +010039#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
Ricardo Ribalda Delgado0240f942015-01-23 17:08:34 +010040 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
Andrei Konovalovae918c02007-07-17 04:04:11 -070041#define XSPI_CR_TXFIFO_RESET 0x20
42#define XSPI_CR_RXFIFO_RESET 0x40
43#define XSPI_CR_MANUAL_SSELECT 0x80
44#define XSPI_CR_TRANS_INHIBIT 0x100
Richard Röjforsc9da2e12009-11-13 12:28:55 +010045#define XSPI_CR_LSB_FIRST 0x200
Andrei Konovalovae918c02007-07-17 04:04:11 -070046
Richard Röjforsc9da2e12009-11-13 12:28:55 +010047#define XSPI_SR_OFFSET 0x64 /* Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070048
49#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
50#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
51#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
52#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
53#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
54
Richard Röjforsc9da2e12009-11-13 12:28:55 +010055#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
56#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070057
58#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
59
60/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
61 * IPIF registers are 32 bit
62 */
63#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
64#define XIPIF_V123B_GINTR_ENABLE 0x80000000
65
66#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
67#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
68
69#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
70#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
71 * disabled */
72#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
73#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
74#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
75#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010076#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
Andrei Konovalovae918c02007-07-17 04:04:11 -070077
78#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
79#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
80
81struct xilinx_spi {
82 /* bitbang has to be first */
83 struct spi_bitbang bitbang;
84 struct completion done;
Andrei Konovalovae918c02007-07-17 04:04:11 -070085 void __iomem *regs; /* virt. address of the control registers */
86
Dan Carpenter9ca12732013-07-17 18:34:48 +030087 int irq;
Andrei Konovalovae918c02007-07-17 04:04:11 -070088
Andrei Konovalovae918c02007-07-17 04:04:11 -070089 u8 *rx_ptr; /* pointer in the Tx buffer */
90 const u8 *tx_ptr; /* pointer in the Rx buffer */
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +010091 u8 bytes_per_word;
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +010092 int buffer_size; /* buffer size in words */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +010093 u32 cs_inactive; /* Level of the CS pins when inactive*/
Jingoo Han6ff86722014-02-26 10:24:47 +090094 unsigned int (*read_fn)(void __iomem *);
95 void (*write_fn)(u32, void __iomem *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070096};
97
Mark Brown06352872015-01-30 13:42:00 +010098static void xspi_write32(u32 val, void __iomem *addr)
99{
100 iowrite32(val, addr);
101}
102
103static unsigned int xspi_read32(void __iomem *addr)
104{
105 return ioread32(addr);
106}
107
108static void xspi_write32_be(u32 val, void __iomem *addr)
109{
110 iowrite32be(val, addr);
111}
112
113static unsigned int xspi_read32_be(void __iomem *addr)
114{
115 return ioread32be(addr);
116}
117
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100118static void xilinx_spi_tx(struct xilinx_spi *xspi)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100119{
Ricardo Ribalda Delgadoc3092942015-01-28 13:23:48 +0100120 if (!xspi->tx_ptr) {
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
122 return;
123 }
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100124 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100125 xspi->tx_ptr += xspi->bytes_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100126}
127
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100128static void xilinx_spi_rx(struct xilinx_spi *xspi)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100129{
130 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100131
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100132 if (!xspi->rx_ptr)
133 return;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100134
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100135 switch (xspi->bytes_per_word) {
136 case 1:
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100137 *(u8 *)(xspi->rx_ptr) = data;
138 break;
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100139 case 2:
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100140 *(u16 *)(xspi->rx_ptr) = data;
141 break;
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100142 case 4:
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100143 *(u32 *)(xspi->rx_ptr) = data;
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100144 break;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100145 }
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100146
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100147 xspi->rx_ptr += xspi->bytes_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100148}
149
Richard Röjfors86fc5932009-11-13 12:28:49 +0100150static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700151{
Richard Röjfors86fc5932009-11-13 12:28:49 +0100152 void __iomem *regs_base = xspi->regs;
153
Andrei Konovalovae918c02007-07-17 04:04:11 -0700154 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100155 xspi->write_fn(XIPIF_V123B_RESET_MASK,
156 regs_base + XIPIF_V123B_RESETR_OFFSET);
Ricardo Ribalda Delgado899929b2015-01-28 13:23:41 +0100157 /* Enable the transmit empty interrupt, which we use to determine
158 * progress on the transmission.
159 */
160 xspi->write_fn(XSPI_INTR_TX_EMPTY,
161 regs_base + XIPIF_V123B_IIER_OFFSET);
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100162 /* Disable the global IPIF interrupt */
163 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700164 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100165 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700166 /* Disable the transmitter, enable Manual Slave Select Assertion,
167 * put SPI controller into master mode, and enable it */
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100168 xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
169 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
170 regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700171}
172
173static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
174{
175 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100176 u16 cr;
177 u32 cs;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700178
179 if (is_on == BITBANG_CS_INACTIVE) {
180 /* Deselect the slave on the SPI bus */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100181 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
182 return;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700183 }
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100184
185 /* Set the SPI clock phase and polarity */
186 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
187 if (spi->mode & SPI_CPHA)
188 cr |= XSPI_CR_CPHA;
189 if (spi->mode & SPI_CPOL)
190 cr |= XSPI_CR_CPOL;
191 if (spi->mode & SPI_LSB_FIRST)
192 cr |= XSPI_CR_LSB_FIRST;
193 if (spi->mode & SPI_LOOP)
194 cr |= XSPI_CR_LOOP;
195 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
196
197 /* We do not check spi->max_speed_hz here as the SPI clock
198 * frequency is not software programmable (the IP block design
199 * parameter)
200 */
201
202 cs = xspi->cs_inactive;
203 cs ^= BIT(spi->chip_select);
204
205 /* Activate the chip select */
206 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700207}
208
209/* spi_bitbang requires custom setup_transfer() to be defined if there is a
Axel Lin9bf46f62014-02-14 21:06:43 +0800210 * custom txrx_bufs().
Andrei Konovalovae918c02007-07-17 04:04:11 -0700211 */
212static int xilinx_spi_setup_transfer(struct spi_device *spi,
213 struct spi_transfer *t)
214{
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100215 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
216
217 if (spi->mode & SPI_CS_HIGH)
218 xspi->cs_inactive &= ~BIT(spi->chip_select);
219 else
220 xspi->cs_inactive |= BIT(spi->chip_select);
221
Andrei Konovalovae918c02007-07-17 04:04:11 -0700222 return 0;
223}
224
Andrei Konovalovae918c02007-07-17 04:04:11 -0700225static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
226{
227 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100228 int remaining_words; /* the number of words left to transfer */
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100229 bool use_irq = false;
230 u16 cr = 0;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700231
232 /* We get here with transmitter inhibited */
233
234 xspi->tx_ptr = t->tx_buf;
235 xspi->rx_ptr = t->rx_buf;
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100236 remaining_words = t->len / xspi->bytes_per_word;
Wolfram Sang16735d02013-11-14 14:32:02 -0800237 reinit_completion(&xspi->done);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700238
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100239 if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
240 use_irq = true;
241 xspi->write_fn(XSPI_INTR_TX_EMPTY,
242 xspi->regs + XIPIF_V123B_IISR_OFFSET);
243 /* Enable the global IPIF interrupt */
244 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
245 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
246 /* Inhibit irq to avoid spurious irqs on tx_empty*/
247 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
248 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
249 xspi->regs + XSPI_CR_OFFSET);
250 }
251
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100252 while (remaining_words) {
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100253 int n_words, tx_words, rx_words;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700254
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100255 n_words = min(remaining_words, xspi->buffer_size);
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100256
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100257 tx_words = n_words;
258 while (tx_words--)
259 xilinx_spi_tx(xspi);
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200260
261 /* Start the transfer by not inhibiting the transmitter any
262 * longer
263 */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200264
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100265 if (use_irq) {
Ricardo Ribalda Delgadod9f58812015-01-28 13:23:45 +0100266 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100267 wait_for_completion(&xspi->done);
Ricardo Ribalda Delgadod9f58812015-01-28 13:23:45 +0100268 } else
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100269 while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) &
270 XSPI_SR_TX_EMPTY_MASK))
271 ;
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200272
273 /* A transmit has just completed. Process received data and
274 * check for more data to transmit. Always inhibit the
275 * transmitter while the Isr refills the transmit register/FIFO,
276 * or make sure it is stopped if we're done.
277 */
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100278 if (use_irq)
Ricardo Ribalda Delgadod9f58812015-01-28 13:23:45 +0100279 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200280 xspi->regs + XSPI_CR_OFFSET);
281
282 /* Read out all the data from the Rx FIFO */
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100283 rx_words = n_words;
284 while (rx_words--)
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100285 xilinx_spi_rx(xspi);
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100286
287 remaining_words -= n_words;
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200288 }
Andrei Konovalovae918c02007-07-17 04:04:11 -0700289
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100290 if (use_irq)
291 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
292
Ricardo Ribalda Delgadod79b2d02015-01-28 13:23:49 +0100293 return t->len;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700294}
295
296
297/* This driver supports single master mode only. Hence Tx FIFO Empty
298 * is the only interrupt we care about.
299 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
300 * Fault are not to happen.
301 */
302static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
303{
304 struct xilinx_spi *xspi = dev_id;
305 u32 ipif_isr;
306
307 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100308 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
309 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700310
311 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200312 complete(&xspi->done);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700313 }
314
315 return IRQ_HANDLED;
316}
317
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100318static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
319{
320 u8 sr;
321 int n_words = 0;
322
323 /*
324 * Before the buffer_size detection we reset the core
325 * to make sure we start with a clean state.
326 */
327 xspi->write_fn(XIPIF_V123B_RESET_MASK,
328 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
329
330 /* Fill the Tx FIFO with as many words as possible */
331 do {
332 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
333 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
334 n_words++;
335 } while (!(sr & XSPI_SR_TX_FULL_MASK));
336
337 return n_words;
338}
339
Grant Likelyeae6cb32010-10-14 09:32:53 -0600340static const struct of_device_id xilinx_spi_of_match[] = {
341 { .compatible = "xlnx,xps-spi-2.00.a", },
342 { .compatible = "xlnx,xps-spi-2.00.b", },
343 {}
344};
345MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
Grant Likelyeae6cb32010-10-14 09:32:53 -0600346
Mark Brown7cb2abd2013-07-05 11:24:26 +0100347static int xilinx_spi_probe(struct platform_device *pdev)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700348{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700349 struct xilinx_spi *xspi;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100350 struct xspi_platform_data *pdata;
Michal Simekad3fdbc2013-07-08 15:29:15 +0200351 struct resource *res;
Michal Simek7b3b7432013-07-09 18:05:16 +0200352 int ret, num_cs = 0, bits_per_word = 8;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100353 struct spi_master *master;
Michal Simek082339b2013-06-04 16:02:36 +0200354 u32 tmp;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100355 u8 i;
John Linnff82c582009-01-09 16:01:53 -0700356
Jingoo Han8074cf02013-07-30 16:58:59 +0900357 pdata = dev_get_platdata(&pdev->dev);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100358 if (pdata) {
359 num_cs = pdata->num_chipselect;
360 bits_per_word = pdata->bits_per_word;
Michal Simekbe3acdf2013-07-08 15:29:17 +0200361 } else {
362 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
363 &num_cs);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100364 }
Mark Brownd81c0bb2013-07-03 12:05:42 +0100365
366 if (!num_cs) {
Mark Brown7cb2abd2013-07-05 11:24:26 +0100367 dev_err(&pdev->dev,
368 "Missing slave select configuration data\n");
Mark Brownd81c0bb2013-07-03 12:05:42 +0100369 return -EINVAL;
370 }
371
Ricardo Ribaldaeb25f162015-01-28 20:53:39 +0100372 if (num_cs > XILINX_SPI_MAX_CS) {
373 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
374 return -EINVAL;
375 }
376
Mark Brown7cb2abd2013-07-05 11:24:26 +0100377 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100378 if (!master)
Mark Brownd81c0bb2013-07-03 12:05:42 +0100379 return -ENODEV;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700380
David Brownelle7db06b2009-06-17 16:26:04 -0700381 /* the spi->mode bits understood by this driver: */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100382 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
383 SPI_CS_HIGH;
David Brownelle7db06b2009-06-17 16:26:04 -0700384
Andrei Konovalovae918c02007-07-17 04:04:11 -0700385 xspi = spi_master_get_devdata(master);
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100386 xspi->cs_inactive = 0xffffffff;
Axel Lin94c69f72013-09-10 15:43:41 +0800387 xspi->bitbang.master = master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700388 xspi->bitbang.chipselect = xilinx_spi_chipselect;
389 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
390 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700391 init_completion(&xspi->done);
392
Michal Simekad3fdbc2013-07-08 15:29:15 +0200393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
394 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
Mark Brownc40537d2013-07-01 20:33:01 +0100395 if (IS_ERR(xspi->regs)) {
396 ret = PTR_ERR(xspi->regs);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700397 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700398 }
399
Lars-Peter Clausen4b153a22014-07-10 10:30:20 +0200400 master->bus_num = pdev->id;
Grant Likely91565c42010-10-14 08:54:55 -0600401 master->num_chipselect = num_cs;
Mark Brown7cb2abd2013-07-05 11:24:26 +0100402 master->dev.of_node = pdev->dev.of_node;
Michal Simek082339b2013-06-04 16:02:36 +0200403
404 /*
405 * Detect endianess on the IP via loop bit in CR. Detection
406 * must be done before reset is sent because incorrect reset
407 * value generates error interrupt.
408 * Setup little endian helper functions first and try to use them
409 * and check if bit was correctly setup or not.
410 */
Mark Brown06352872015-01-30 13:42:00 +0100411 xspi->read_fn = xspi_read32;
412 xspi->write_fn = xspi_write32;
Michal Simek082339b2013-06-04 16:02:36 +0200413
414 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
415 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
416 tmp &= XSPI_CR_LOOP;
417 if (tmp != XSPI_CR_LOOP) {
Mark Brown06352872015-01-30 13:42:00 +0100418 xspi->read_fn = xspi_read32_be;
419 xspi->write_fn = xspi_write32_be;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100420 }
Michal Simek082339b2013-06-04 16:02:36 +0200421
Axel Lin9bf46f62014-02-14 21:06:43 +0800422 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100423 xspi->bytes_per_word = bits_per_word / 8;
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100424 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
425
Michal Simek7b3b7432013-07-09 18:05:16 +0200426 xspi->irq = platform_get_irq(pdev, 0);
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100427 if (xspi->irq >= 0) {
428 /* Register for SPI Interrupt */
429 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
430 dev_name(&pdev->dev), xspi);
431 if (ret)
432 goto put_master;
Michal Simek7b3b7432013-07-09 18:05:16 +0200433 }
434
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100435 /* SPI controller initializations */
436 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700437
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100438 ret = spi_bitbang_start(&xspi->bitbang);
439 if (ret) {
Mark Brown7cb2abd2013-07-05 11:24:26 +0100440 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
Michal Simek7b3b7432013-07-09 18:05:16 +0200441 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700442 }
443
Mark Brown7cb2abd2013-07-05 11:24:26 +0100444 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
Michal Simekad3fdbc2013-07-08 15:29:15 +0200445 (unsigned long long)res->start, xspi->regs, xspi->irq);
Grant Likely8fd88212010-10-14 09:04:29 -0600446
Grant Likelyeae6cb32010-10-14 09:32:53 -0600447 if (pdata) {
448 for (i = 0; i < pdata->num_devices; i++)
449 spi_new_device(master, pdata->devices + i);
450 }
Grant Likely8fd88212010-10-14 09:04:29 -0600451
Mark Brown7cb2abd2013-07-05 11:24:26 +0100452 platform_set_drvdata(pdev, master);
Grant Likely8fd88212010-10-14 09:04:29 -0600453 return 0;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100454
Mark Brownd81c0bb2013-07-03 12:05:42 +0100455put_master:
456 spi_master_put(master);
457
458 return ret;
Grant Likely8fd88212010-10-14 09:04:29 -0600459}
460
Mark Brown7cb2abd2013-07-05 11:24:26 +0100461static int xilinx_spi_remove(struct platform_device *pdev)
Grant Likely8fd88212010-10-14 09:04:29 -0600462{
Mark Brown7cb2abd2013-07-05 11:24:26 +0100463 struct spi_master *master = platform_get_drvdata(pdev);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100464 struct xilinx_spi *xspi = spi_master_get_devdata(master);
Michal Simek7b3b7432013-07-09 18:05:16 +0200465 void __iomem *regs_base = xspi->regs;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100466
467 spi_bitbang_stop(&xspi->bitbang);
Michal Simek7b3b7432013-07-09 18:05:16 +0200468
469 /* Disable all the interrupts just in case */
470 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
471 /* Disable the global IPIF interrupt */
472 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100473
474 spi_master_put(xspi->bitbang.master);
Grant Likely8fd88212010-10-14 09:04:29 -0600475
476 return 0;
477}
478
479/* work with hotplug and coldplug */
480MODULE_ALIAS("platform:" XILINX_SPI_NAME);
481
482static struct platform_driver xilinx_spi_driver = {
483 .probe = xilinx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000484 .remove = xilinx_spi_remove,
Grant Likely8fd88212010-10-14 09:04:29 -0600485 .driver = {
486 .name = XILINX_SPI_NAME,
Grant Likelyeae6cb32010-10-14 09:32:53 -0600487 .of_match_table = xilinx_spi_of_match,
Grant Likely8fd88212010-10-14 09:04:29 -0600488 },
489};
Grant Likely940ab882011-10-05 11:29:49 -0600490module_platform_driver(xilinx_spi_driver);
Grant Likely8fd88212010-10-14 09:04:29 -0600491
Andrei Konovalovae918c02007-07-17 04:04:11 -0700492MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
493MODULE_DESCRIPTION("Xilinx SPI driver");
494MODULE_LICENSE("GPL");