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Johan RUDHOLMa8bfde72012-02-12 11:46:44 -05001/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public
4 * License v2 as published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public
12 * License along with this program; if not, write to the
13 * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
14 * Boston, MA 021110-1307, USA.
15 */
16
17#include <asm-generic/int-ll64.h>
18#include <linux/mmc/ioctl.h>
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050019#include <stdio.h>
20
21#define CHECK(expr, msg, err_stmt) { if (expr) { fprintf(stderr, msg); err_stmt; } }
22
Oleg Matcovschi294bf862013-05-23 17:11:06 -070023/* From kernel linux/major.h */
24#define MMC_BLOCK_MAJOR 179
25
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050026/* From kernel linux/mmc/mmc.h */
27#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
28#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
Ben Gardiner27c357d2013-05-30 17:12:47 -040029#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
30#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050031#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
32
33/*
34 * EXT_CSD fields
35 */
Giuseppe CAVALLAROa5bf4a22012-02-20 09:45:29 +010036#define EXT_CSD_S_CMD_SET 504
37#define EXT_CSD_HPI_FEATURE 503
Jaehoon Chung86496512012-09-21 10:08:05 +000038#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Giuseppe CAVALLAROa5bf4a22012-02-20 09:45:29 +010039#define EXT_CSD_BOOT_INFO 228 /* R/W */
Ben Gardiner4e850232013-05-30 17:12:49 -040040#define EXT_CSD_SEC_COUNT_3 215
41#define EXT_CSD_SEC_COUNT_2 214
42#define EXT_CSD_SEC_COUNT_1 213
43#define EXT_CSD_SEC_COUNT_0 212
Giuseppe CAVALLAROa5bf4a22012-02-20 09:45:29 +010044#define EXT_CSD_PART_SWITCH_TIME 199
45#define EXT_CSD_BOOT_CFG 179
Giuseppe CAVALLARO7bd13202012-04-19 10:58:37 +020046#define EXT_CSD_PART_CONFIG 179
Ben Gardinerd91d3692013-05-30 17:12:51 -040047#define EXT_CSD_ERASE_GROUP_DEF 175
Saugata Dasb7e25992012-05-17 09:26:34 -040048#define EXT_CSD_BOOT_WP 173
Ben Gardiner4da1c0d2013-09-19 11:14:28 -040049#define EXT_CSD_WR_REL_SET 167
Saugata Dasb7e25992012-05-17 09:26:34 -040050#define EXT_CSD_WR_REL_PARAM 166
Yaniv Gardi21bb4732013-05-26 13:25:33 -040051#define EXT_CSD_SANITIZE_START 165
Jaehoon Chung86496512012-09-21 10:08:05 +000052#define EXT_CSD_BKOPS_EN 163 /* R/W */
Chris Ballf74dfe22012-10-19 16:49:55 -040053#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Ben Gardiner82bd9502013-06-27 11:04:10 -040054#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Oliver Metz22f26412013-09-23 08:40:51 +020055#define EXT_CSD_MAX_ENH_SIZE_MULT_2 159
56#define EXT_CSD_MAX_ENH_SIZE_MULT_1 158
57#define EXT_CSD_MAX_ENH_SIZE_MULT_0 157
Ben Gardinerd91d3692013-05-30 17:12:51 -040058#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Ben Gardinera6cd98d2013-05-30 17:12:46 -040059#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
Ben Gardinerf82e27a2013-05-30 17:12:50 -040060#define EXT_CSD_ENH_SIZE_MULT_2 142
61#define EXT_CSD_ENH_SIZE_MULT_1 141
62#define EXT_CSD_ENH_SIZE_MULT_0 140
Ben Gardiner68f490b2013-05-30 17:12:48 -040063#define EXT_CSD_ENH_START_ADDR_3 139
64#define EXT_CSD_ENH_START_ADDR_2 138
65#define EXT_CSD_ENH_START_ADDR_1 137
66#define EXT_CSD_ENH_START_ADDR_0 136
Saugata Dasb7e25992012-05-17 09:26:34 -040067#define EXT_CSD_NATIVE_SECTOR_SIZE 63 /* R */
68#define EXT_CSD_USE_NATIVE_SECTOR 62 /* R/W */
69#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
70
71/*
72 * WR_REL_PARAM field definitions
73 */
74#define HS_CTRL_REL (1<<0)
75#define EN_REL_WR (1<<2)
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050076
77/*
Jaehoon Chung86496512012-09-21 10:08:05 +000078 * BKOPS_EN field definition
79 */
80#define BKOPS_ENABLE (1<<0)
81
82/*
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050083 * EXT_CSD field definitions
84 */
Giuseppe CAVALLAROa5bf4a22012-02-20 09:45:29 +010085#define EXT_CSD_HPI_SUPP (1<<0)
86#define EXT_CSD_HPI_IMPL (1<<1)
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -050087#define EXT_CSD_CMD_SET_NORMAL (1<<0)
88#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
89#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
90#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
91#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
Giuseppe CAVALLAROa5bf4a22012-02-20 09:45:29 +010092#define EXT_CSD_BOOT_INFO_HS_MODE (1<<2)
93#define EXT_CSD_BOOT_INFO_DDR_DDR (1<<1)
94#define EXT_CSD_BOOT_INFO_ALT (1<<0)
95#define EXT_CSD_BOOT_CFG_ACK (1<<6)
96#define EXT_CSD_BOOT_CFG_EN (0x38)
Mario Schuknecht8c0c40d2013-05-15 08:28:04 +020097#define EXT_CSD_BOOT_CFG_ACC (0x07)
Chris Ballf74dfe22012-10-19 16:49:55 -040098#define EXT_CSD_RST_N_EN_MASK (0x03)
99#define EXT_CSD_HW_RESET_EN (0x01)
100#define EXT_CSD_HW_RESET_DIS (0x02)
Giuseppe CAVALLARO7bd13202012-04-19 10:58:37 +0200101#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
102#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
103#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2)
104#define EXT_CSD_PART_CONFIG_ACC_USER_AREA (0x7)
105#define EXT_CSD_PART_CONFIG_ACC_ACK (0x40)
Ben Gardiner82bd9502013-06-27 11:04:10 -0400106#define EXT_CSD_PARTITIONING_EN (1<<0)
107#define EXT_CSD_ENH_ATTRIBUTE_EN (1<<1)
Ben Gardinerd91d3692013-05-30 17:12:51 -0400108#define EXT_CSD_ENH_USR (1<<0)
Johan RUDHOLMa8bfde72012-02-12 11:46:44 -0500109
110/* From kernel linux/mmc/core.h */
111#define MMC_RSP_PRESENT (1 << 0)
112#define MMC_RSP_136 (1 << 1) /* 136 bit response */
113#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
114#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
115#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
116
117#define MMC_CMD_AC (0 << 5)
118#define MMC_CMD_ADTC (1 << 5)
119
120#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
121#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
122
123#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
124#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY)
125
126#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
127#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)