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Bert Vermeulend4eabea2014-09-05 03:23:32 +02001/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
Bert Vermeulen22c18b02014-09-05 03:49:25 +020020#include <string.h>
Bert Vermeulend4eabea2014-09-05 03:23:32 +020021#include "protocol.h"
22
23#define CH_IDX(x) (1 << x)
24
Bert Vermeulen22c18b02014-09-05 03:49:25 +020025const char *pps_vendors[][2] = {
26 { "RIGOL TECHNOLOGIES", "Rigol" },
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +020027 { "HEWLETT-PACKARD", "HP" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +020028};
29
Bert Vermeulen22c18b02014-09-05 03:49:25 +020030const char *get_vendor(const char *raw_vendor)
31{
32 unsigned int i;
33
34 for (i = 0; i < ARRAY_SIZE(pps_vendors); i++) {
35 if (!strcasecmp(raw_vendor, pps_vendors[i][0]))
36 return pps_vendors[i][1];
37 }
38
39 return raw_vendor;
40}
41
Bert Vermeulen584560f2014-09-16 17:49:20 +020042static const uint32_t devopts_none[] = { };
Bert Vermeulenbfc86792014-09-09 13:22:24 +020043
Bert Vermeulend4eabea2014-09-05 03:23:32 +020044/* Rigol DP800 series */
Bert Vermeulen584560f2014-09-16 17:49:20 +020045static const uint32_t rigol_dp800_devopts[] = {
Bert Vermeulend4eabea2014-09-05 03:23:32 +020046 SR_CONF_POWER_SUPPLY,
47 SR_CONF_CONTINUOUS,
Bert Vermeulen5827f612014-09-17 15:28:29 +020048 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
Bert Vermeulend4eabea2014-09-05 03:23:32 +020049};
50
Bert Vermeulen584560f2014-09-16 17:49:20 +020051static const uint32_t rigol_dp800_devopts_cg[] = {
Bert Vermeulen5827f612014-09-17 15:28:29 +020052 SR_CONF_OUTPUT_REGULATION | SR_CONF_GET,
53 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
54 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
55 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
56 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
57 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
58 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
59 SR_CONF_OUTPUT_VOLTAGE | SR_CONF_GET,
Bert Vermeulenca95e902014-10-15 12:03:00 +020060 SR_CONF_OUTPUT_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
Bert Vermeulen5827f612014-09-17 15:28:29 +020061 SR_CONF_OUTPUT_CURRENT | SR_CONF_GET,
Bert Vermeulenca95e902014-10-15 12:03:00 +020062 SR_CONF_OUTPUT_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
Bert Vermeulen5827f612014-09-17 15:28:29 +020063 SR_CONF_OUTPUT_ENABLED | SR_CONF_GET | SR_CONF_SET,
Bert Vermeulend4eabea2014-09-05 03:23:32 +020064};
65
Bert Vermeulen3222ee12014-09-05 12:52:57 +020066struct channel_spec rigol_dp831_ch[] = {
67 { "1", { 0, 8, 0.001 }, { 0, 5, 0.0003 } },
68 { "2", { 0, 30, 0.001 }, { 0, 2, 0.0001 } },
69 { "3", { 0, -30, 0.001 }, { 0, 2, 0.0001 } },
Bert Vermeulend4eabea2014-09-05 03:23:32 +020070};
71
Bert Vermeulen3222ee12014-09-05 12:52:57 +020072struct channel_spec rigol_dp832_ch[] = {
73 { "1", { 0, 30, 0.001 }, { 0, 3, 0.001 } },
74 { "2", { 0, 30, 0.001 }, { 0, 3, 0.001 } },
75 { "3", { 0, 5, 0.001 }, { 0, 3, 0.001 } },
76};
77
78struct channel_group_spec rigol_dp800_cg[] = {
Bert Vermeulend4eabea2014-09-05 03:23:32 +020079 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
80 { "2", CH_IDX(1), PPS_OVP | PPS_OCP },
81 { "3", CH_IDX(2), PPS_OVP | PPS_OCP },
82};
83
Bert Vermeulen3222ee12014-09-05 12:52:57 +020084struct scpi_command rigol_dp800_cmd[] = {
Bert Vermeulend4eabea2014-09-05 03:23:32 +020085 { SCPI_CMD_KEY_UNLOCK, "SYST:KLOCK OFF" },
86 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT? CH%s" },
87 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR? CH%s" },
88 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE? CH%s" },
Bert Vermeulenca95e902014-10-15 12:03:00 +020089 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR%s:VOLT?" },
90 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR%s:VOLT %.6f" },
91 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR%s:CURR?" },
92 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR%s:CURR %.6f" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +020093 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP? CH%s" },
Bert Vermeulen53a81802014-10-10 16:00:33 +020094 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP CH%s,ON" },
95 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP CH%s,OFF" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +020096 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE? CH%s" },
97 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
Bert Vermeulen53a81802014-10-10 16:00:33 +020098 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
99 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200100 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP? CH%s" },
Bert Vermeulen53a81802014-10-10 16:00:33 +0200101 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP CH%s,ON" },
102 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP CH%s,OFF" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200103 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES? CH%s" },
104 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL? CH%s" },
105 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL CH%s,%.6f" },
106 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP? CH%s" },
Bert Vermeulen53a81802014-10-10 16:00:33 +0200107 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP CH%s,ON" },
108 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP CH%s,OFF" },
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200109 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES? CH%s" },
110 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL? CH%s" },
111 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL CH%s,%.6f" },
112};
113
Bert Vermeulenbfc86792014-09-09 13:22:24 +0200114/* HP 663xx series */
Bert Vermeulen584560f2014-09-16 17:49:20 +0200115static const uint32_t hp_6632b_devopts[] = {
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200116 SR_CONF_POWER_SUPPLY,
117 SR_CONF_CONTINUOUS,
Bert Vermeulen5827f612014-09-17 15:28:29 +0200118 SR_CONF_OUTPUT_ENABLED | SR_CONF_GET | SR_CONF_SET,
119 SR_CONF_OUTPUT_VOLTAGE | SR_CONF_GET,
120 SR_CONF_OUTPUT_CURRENT | SR_CONF_GET,
Bert Vermeulenca95e902014-10-15 12:03:00 +0200121 SR_CONF_OUTPUT_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
122 SR_CONF_OUTPUT_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200123};
124
125struct channel_spec hp_6632b_ch[] = {
126 { "1", { 0, 20.475, 0.005 }, { 0, 5.1188, 0.00132 } },
127};
128
129struct channel_group_spec hp_6632b_cg[] = {
130 { "1", CH_IDX(0), 0 },
131};
132
133struct scpi_command hp_6632b_cmd[] = {
134 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
Bert Vermeulen53a81802014-10-10 16:00:33 +0200135 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
136 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200137 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
138 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
Bert Vermeulenca95e902014-10-15 12:03:00 +0200139 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
140 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
141 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
142 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200143};
144
145
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200146SR_PRIV const struct scpi_pps pps_profiles[] = {
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200147 /* HP 6632B */
148 { "HP", "6632B", 0,
149 ARRAY_AND_SIZE(hp_6632b_devopts),
Bert Vermeulenbfc86792014-09-09 13:22:24 +0200150 ARRAY_AND_SIZE(devopts_none),
Bert Vermeulenbc4a2a42014-09-08 12:44:16 +0200151 ARRAY_AND_SIZE(hp_6632b_ch),
152 ARRAY_AND_SIZE(hp_6632b_cg),
153 ARRAY_AND_SIZE(hp_6632b_cmd),
154 },
155
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200156 /* Rigol DP800 series */
Bert Vermeulen3222ee12014-09-05 12:52:57 +0200157 { "Rigol", "^DP831A$", PPS_OTP,
158 ARRAY_AND_SIZE(rigol_dp800_devopts),
159 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
160 ARRAY_AND_SIZE(rigol_dp831_ch),
161 ARRAY_AND_SIZE(rigol_dp800_cg),
162 ARRAY_AND_SIZE(rigol_dp800_cmd),
163 },
164 { "Rigol", "^(DP832|DP832A)$", PPS_OTP,
165 ARRAY_AND_SIZE(rigol_dp800_devopts),
166 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
167 ARRAY_AND_SIZE(rigol_dp832_ch),
168 ARRAY_AND_SIZE(rigol_dp800_cg),
169 ARRAY_AND_SIZE(rigol_dp800_cmd),
Bert Vermeulend4eabea2014-09-05 03:23:32 +0200170 },
171};
172SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
173