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stepand4b13752007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Edward O'Callaghanc66827e2020-10-09 12:22:04 +11004 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
stepandbd3af12008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
stepand4b13752007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
stepand4b13752007-10-15 21:45:29 +000015 */
16
17/*
18 * Contains the generic SPI framework
19 */
20
oxygene70aa6502011-03-08 07:17:44 +000021#include <strings.h>
hailfinger132df7b2010-09-15 00:13:02 +000022#include <string.h>
stepand4b13752007-10-15 21:45:29 +000023#include "flash.h"
hailfinger66966da2009-06-15 14:14:48 +000024#include "flashchips.h"
snelson8913d082010-02-26 05:48:29 +000025#include "chipdrivers.h"
hailfinger428f6852010-07-27 22:41:39 +000026#include "programmer.h"
hailfinger78031562008-05-13 14:58:23 +000027#include "spi.h"
stepand4b13752007-10-15 21:45:29 +000028
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110029int spi_send_command(const struct flashctx *flash, unsigned int writecnt,
30 unsigned int readcnt, const unsigned char *writearr,
31 unsigned char *readarr)
hailfinger35cc8162007-10-16 21:09:06 +000032{
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110033 return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
34 readarr);
hailfinger35cc8162007-10-16 21:09:06 +000035}
36
Souvik Ghoshd75cd672016-06-17 14:21:39 -070037int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds)
hailfinger68002c22009-07-10 21:08:55 +000038{
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110039 return flash->mst->spi.multicommand(flash, cmds);
hailfinger948b81f2009-07-22 15:36:50 +000040}
41
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110042int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
43 unsigned int readcnt,
44 const unsigned char *writearr,
45 unsigned char *readarr)
hailfinger948b81f2009-07-22 15:36:50 +000046{
47 struct spi_command cmd[] = {
48 {
49 .writecnt = writecnt,
50 .readcnt = readcnt,
51 .writearr = writearr,
52 .readarr = readarr,
53 }, {
54 .writecnt = 0,
55 .writearr = NULL,
56 .readcnt = 0,
57 .readarr = NULL,
58 }};
59
Souvik Ghoshd75cd672016-06-17 14:21:39 -070060 return spi_send_multicommand(flash, cmd);
hailfinger948b81f2009-07-22 15:36:50 +000061}
62
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110063int default_spi_send_multicommand(const struct flashctx *flash,
64 struct spi_command *cmds)
hailfinger948b81f2009-07-22 15:36:50 +000065{
66 int result = 0;
hailfingerbb092112009-09-18 15:50:56 +000067 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
Souvik Ghoshd75cd672016-06-17 14:21:39 -070068 result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
hailfingerbb092112009-09-18 15:50:56 +000069 cmds->writearr, cmds->readarr);
hailfinger948b81f2009-07-22 15:36:50 +000070 }
71 return result;
hailfinger68002c22009-07-10 21:08:55 +000072}
73
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110074int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
75 unsigned int len)
mkarcher8fb57592011-05-11 17:07:02 +000076{
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110077 unsigned int max_data = flash->mst->spi.max_data_read;
mkarcher8fb57592011-05-11 17:07:02 +000078 if (max_data == MAX_DATA_UNSPECIFIED) {
79 msg_perr("%s called, but SPI read chunk size not defined "
80 "on this hardware. Please report a bug at "
81 "flashrom@flashrom.org\n", __func__);
82 return 1;
83 }
Edward O'Callaghan0a92ce22020-12-09 17:10:37 +110084 return spi_read_chunked(flash, buf, start, len, max_data);
mkarcher8fb57592011-05-11 17:07:02 +000085}
86
Patrick Georgiab8353e2017-02-03 18:32:01 +010087int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
mkarcher8fb57592011-05-11 17:07:02 +000088{
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110089 unsigned int max_data = flash->mst->spi.max_data_write;
mkarcher8fb57592011-05-11 17:07:02 +000090 if (max_data == MAX_DATA_UNSPECIFIED) {
91 msg_perr("%s called, but SPI write chunk size not defined "
92 "on this hardware. Please report a bug at "
93 "flashrom@flashrom.org\n", __func__);
94 return 1;
95 }
Edward O'Callaghan0a92ce22020-12-09 17:10:37 +110096 return spi_write_chunked(flash, buf, start, len, max_data);
mkarcher8fb57592011-05-11 17:07:02 +000097}
98
Edward O'Callaghanc66827e2020-10-09 12:22:04 +110099int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
100 unsigned int len)
hailfingerb8f7e882008-01-19 00:04:46 +0000101{
Nico Huber470a6492019-06-18 23:39:56 +0200102 int ret;
103 size_t to_read;
104 for (; len; len -= to_read, buf += to_read, start += to_read) {
105 /* Do not cross 16MiB boundaries in a single transfer.
106 This helps with
107 o multi-die 4-byte-addressing chips,
108 o dediprog that has a protocol limit of 32MiB-512B. */
109 to_read = min(ALIGN_DOWN(start + 16*MiB, 16*MiB) - start, len);
110 ret = flash->mst->spi.read(flash, buf, start, to_read);
111 if (ret)
112 return ret;
113 }
114 return 0;
hailfingerb8f7e882008-01-19 00:04:46 +0000115}
116
hailfingered063f52009-05-09 02:30:21 +0000117/*
hailfingered063f52009-05-09 02:30:21 +0000118 * Program chip using page (256 bytes) programming.
119 * Some SPI masters can't do this, they use single byte programming instead.
hailfingerc7d06c62010-07-14 16:19:05 +0000120 * The redirect to single byte programming is achieved by setting
121 * .write_256 = spi_chip_write_1
hailfingered063f52009-05-09 02:30:21 +0000122 */
hailfingerc7d06c62010-07-14 16:19:05 +0000123/* real chunksize is up to 256, logical chunksize is 256 */
Patrick Georgiab8353e2017-02-03 18:32:01 +0100124int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
hailfinger2c361e42008-05-13 23:03:12 +0000125{
Edward O'Callaghanc66827e2020-10-09 12:22:04 +1100126 return flash->mst->spi.write_256(flash, buf, start, len);
hailfingerc7d06c62010-07-14 16:19:05 +0000127}
128
Edward O'Callaghaneeaac6b2020-10-12 19:51:56 +1100129int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
130{
131 return flash->mst->spi.write_aai(flash, buf, start, len);
132}
133
Nico Huberf1eeda62021-05-11 17:38:14 +0200134int register_spi_master(const struct spi_master *mst, void *data)
mkarcherd264e9e2011-05-11 17:07:07 +0000135{
Edward O'Callaghan20ba6152019-08-26 23:21:09 +1000136 struct registered_master rmst;
137
Edward O'Callaghanc66827e2020-10-09 12:22:04 +1100138 if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command ||
139 !mst->multicommand ||
140 ((mst->command == default_spi_send_command) &&
141 (mst->multicommand == default_spi_send_multicommand))) {
142 msg_perr("%s called with incomplete master definition. "
143 "Please report a bug at flashrom@flashrom.org\n",
144 __func__);
145 return ERROR_FLASHROM_BUG;
146 }
147
Edward O'Callaghan20ba6152019-08-26 23:21:09 +1000148
149 rmst.buses_supported = BUS_SPI;
150 rmst.spi = *mst;
Nico Huberf1eeda62021-05-11 17:38:14 +0200151 if (data)
152 rmst.spi.data = data;
Edward O'Callaghan20ba6152019-08-26 23:21:09 +1000153 return register_master(&rmst);
David Hendricks91040832011-07-08 20:01:09 -0700154}