blob: fdee462445c52eecf82d6f8b3296f4602db2c345 [file] [log] [blame]
David Hendricks398714f2014-07-03 17:49:41 -07001/*
2 * This file is part of the flashrom project.
3 *
Nikolai Artemiev2d60b332020-12-04 16:43:59 +11004 * Copyright (C) 2014 Google LLC.
David Hendricks398714f2014-07-03 17:49:41 -07005 *
Nikolai Artemiev2d60b332020-12-04 16:43:59 +11006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
David Hendricks398714f2014-07-03 17:49:41 -070010 *
Nikolai Artemiev2d60b332020-12-04 16:43:59 +110011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Nikolai Artemiev144243b2020-11-10 11:57:39 +110015 */
16
17/*
David Hendricks43d9afd2015-03-13 20:54:23 -070018 * s25f.c - Helper functions for Spansion S25FL and S25FS SPI flash chips.
Vadim Bendebury3a501162014-10-21 20:38:13 -070019 * Uses 24 bit addressing for the FS chips and 32 bit addressing for the FL
20 * chips (which is required by the overlayed sector size devices).
21 * TODO: Implement fancy hybrid sector architecture helpers.
David Hendricks398714f2014-07-03 17:49:41 -070022 */
23
Vadim Bendebury3a501162014-10-21 20:38:13 -070024#include <string.h>
25
David Hendricks398714f2014-07-03 17:49:41 -070026#include "chipdrivers.h"
27#include "spi.h"
David Hendricks43d9afd2015-03-13 20:54:23 -070028#include "writeprotect.h"
David Hendricks398714f2014-07-03 17:49:41 -070029
David Hendricks43d9afd2015-03-13 20:54:23 -070030/*
31 * RDAR and WRAR are supported on chips which have more than one set of status
32 * and control registers and take an address of the register to read/write.
33 * WRR, RDSR2, and RDCR are used on chips with a more limited set of control/
34 * status registers.
35 *
36 * WRR is somewhat peculiar. It shares the same opcode as JEDEC_WRSR, and if
37 * given one data byte (following the opcode) it acts the same way. If it's
38 * given two data bytes, the first data byte overwrites status register 1
39 * and the second data byte overwrites config register 1.
40 */
41#define CMD_WRR 0x01
42#define CMD_WRDI 0x04
43#define CMD_RDSR2 0x07 /* note: read SR1 with JEDEC RDSR opcode */
44#define CMD_RDCR 0x35
David Hendricks398714f2014-07-03 17:49:41 -070045#define CMD_RDAR 0x65
46#define CMD_WRAR 0x71
David Hendricks43d9afd2015-03-13 20:54:23 -070047
48/* TODO: For now, commands which use an address assume 24-bit addressing */
49#define CMD_WRR_LEN 3
50#define CMD_WRDI_LEN 1
David Hendricks398714f2014-07-03 17:49:41 -070051#define CMD_RDAR_LEN 4
52#define CMD_WRAR_LEN 5
53
54#define CMD_RSTEN 0x66
55#define CMD_RST 0x99
56
David Hendricksa9884852014-12-11 15:31:12 -080057#define CR1NV_ADDR 0x000002
David Hendricks43d9afd2015-03-13 20:54:23 -070058#define CR1_BPNV_O (1 << 3)
59#define CR1_TBPROT_O (1 << 5)
David Hendricks398714f2014-07-03 17:49:41 -070060#define CR3NV_ADDR 0x000004
61#define CR3NV_20H_NV (1 << 3)
62
David Hendricks43d9afd2015-03-13 20:54:23 -070063/* See "Embedded Algorithm Performance Tables for additional timing specs. */
64#define T_W 145 * 1000 /* NV register write time (145ms) */
65#define T_RPH 35 /* Reset pulse hold time (35us) */
66#define S25FS_T_SE 145 * 1000 /* Sector Erase Time (145ms) */
67#define S25FL_T_SE 130 * 1000 /* Sector Erase Time (130ms) */
68
Souvik Ghoshd75cd672016-06-17 14:21:39 -070069static int s25f_legacy_software_reset(const struct flashctx *flash)
David Hendricks43d9afd2015-03-13 20:54:23 -070070{
David Hendricks43d9afd2015-03-13 20:54:23 -070071 struct spi_command cmds[] = {
72 {
73 .writecnt = 1,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +110074 .writearr = (const uint8_t[]){ CMD_RSTEN },
David Hendricks43d9afd2015-03-13 20:54:23 -070075 .readcnt = 0,
76 .readarr = NULL,
77 }, {
78 .writecnt = 1,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +110079 .writearr = (const uint8_t[]){ 0xf0 },
David Hendricks43d9afd2015-03-13 20:54:23 -070080 .readcnt = 0,
81 .readarr = NULL,
82 }, {
83 .writecnt = 0,
84 .writearr = NULL,
85 .readcnt = 0,
86 .readarr = NULL,
87 }};
88
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +110089 int result = spi_send_multicommand(flash, cmds);
David Hendricks43d9afd2015-03-13 20:54:23 -070090 if (result) {
91 msg_cerr("%s failed during command execution\n", __func__);
92 return result;
93 }
94
95 /* Allow time for reset command to execute. The datasheet specifies
96 * Trph = 35us, double that to be safe. */
97 programmer_delay(T_RPH * 2);
98
99 return 0;
100}
101
102/* "Legacy software reset" is disabled by default on S25FS, use this instead. */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700103static int s25fs_software_reset(struct flashctx *flash)
David Hendricks43d9afd2015-03-13 20:54:23 -0700104{
David Hendricks43d9afd2015-03-13 20:54:23 -0700105 struct spi_command cmds[] = {
106 {
107 .writecnt = 1,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100108 .writearr = (const uint8_t[]){ CMD_RSTEN },
David Hendricks43d9afd2015-03-13 20:54:23 -0700109 .readcnt = 0,
110 .readarr = NULL,
111 }, {
112 .writecnt = 1,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100113 .writearr = (const uint8_t[]){ CMD_RST },
David Hendricks43d9afd2015-03-13 20:54:23 -0700114 .readcnt = 0,
115 .readarr = NULL,
116 }, {
117 .writecnt = 0,
118 .writearr = NULL,
119 .readcnt = 0,
120 .readarr = NULL,
121 }};
122
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100123 int result = spi_send_multicommand(flash, cmds);
David Hendricks43d9afd2015-03-13 20:54:23 -0700124 if (result) {
125 msg_cerr("%s failed during command execution\n", __func__);
126 return result;
127 }
128
129 /* Allow time for reset command to execute. Double tRPH to be safe. */
130 programmer_delay(T_RPH * 2);
131
132 return 0;
133}
134
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700135static int s25f_poll_status(const struct flashctx *flash)
David Hendricks43d9afd2015-03-13 20:54:23 -0700136{
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530137 uint8_t tmp = spi_read_status_register(flash);
David Hendricks43d9afd2015-03-13 20:54:23 -0700138
Edward O'Callaghan8b5e4732019-03-05 15:27:53 +1100139 while (tmp & SPI_SR_WIP) {
David Hendricks43d9afd2015-03-13 20:54:23 -0700140 /*
141 * The WIP bit on S25F chips remains set to 1 if erase or
142 * programming errors occur, so we must check for those
143 * errors here. If an error is encountered, do a software
144 * reset to clear WIP and other volatile bits, otherwise
145 * the chip will be unresponsive to further commands.
146 */
Edward O'Callaghan1945f1e2019-03-18 13:12:51 +1100147 if (tmp & SPI_SR_ERA_ERR) {
David Hendricks43d9afd2015-03-13 20:54:23 -0700148 msg_cerr("Erase error occurred\n");
149 s25f_legacy_software_reset(flash);
150 return -1;
151 }
152
153 if (tmp & (1 << 6)) {
154 msg_cerr("Programming error occurred\n");
155 s25f_legacy_software_reset(flash);
156 return -1;
157 }
158
159 programmer_delay(1000 * 10);
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530160 tmp = spi_read_status_register(flash);
David Hendricks43d9afd2015-03-13 20:54:23 -0700161 }
162
163 return 0;
164}
165
166/* "Read Any Register" instruction only supported on S25FS */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700167static int s25fs_read_cr(const struct flashctx *flash, uint32_t addr)
David Hendricks398714f2014-07-03 17:49:41 -0700168{
David Hendricks398714f2014-07-03 17:49:41 -0700169 uint8_t cfg;
170 /* By default, 8 dummy cycles are necessary for variable-latency
171 commands such as RDAR (see CR2NV[3:0]). */
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100172 uint8_t read_cr_cmd[] = {
Nikolai Artemiev144243b2020-11-10 11:57:39 +1100173 CMD_RDAR,
174 (addr >> 16) & 0xff,
175 (addr >> 8) & 0xff,
176 (addr & 0xff),
177 0x00, 0x00, 0x00, 0x00,
178 0x00, 0x00, 0x00, 0x00,
David Hendricks398714f2014-07-03 17:49:41 -0700179 };
180
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100181 int result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg);
David Hendricks398714f2014-07-03 17:49:41 -0700182 if (result) {
183 msg_cerr("%s failed during command execution at address 0x%x\n",
184 __func__, addr);
David Hendricks688b5e22014-12-12 11:15:44 -0800185 return -1;
David Hendricks398714f2014-07-03 17:49:41 -0700186 }
187
188 return cfg;
189}
190
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700191static int s25f_read_cr1(const struct flashctx *flash)
David Hendricks43d9afd2015-03-13 20:54:23 -0700192{
193 int result;
194 uint8_t cfg;
195 unsigned char read_cr_cmd[] = { CMD_RDCR };
196
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700197 result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg);
David Hendricks43d9afd2015-03-13 20:54:23 -0700198 if (result) {
199 msg_cerr("%s failed during command execution\n", __func__);
200 return -1;
201 }
202
203 return cfg;
204}
205
206/* "Write Any Register" instruction only supported on S25FS */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700207static int s25fs_write_cr(const struct flashctx *flash,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100208 uint32_t addr, uint8_t data)
David Hendricks398714f2014-07-03 17:49:41 -0700209{
David Hendricks398714f2014-07-03 17:49:41 -0700210 struct spi_command cmds[] = {
211 {
212 .writecnt = JEDEC_WREN_OUTSIZE,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100213 .writearr = (const uint8_t[]){ JEDEC_WREN },
David Hendricks398714f2014-07-03 17:49:41 -0700214 .readcnt = 0,
215 .readarr = NULL,
216 }, {
217 .writecnt = CMD_WRAR_LEN,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100218 .writearr = (const uint8_t[]){
David Hendricks398714f2014-07-03 17:49:41 -0700219 CMD_WRAR,
220 (addr >> 16) & 0xff,
221 (addr >> 8) & 0xff,
222 (addr & 0xff),
223 data
224 },
225 .readcnt = 0,
226 .readarr = NULL,
227 }, {
228 .writecnt = 0,
229 .writearr = NULL,
230 .readcnt = 0,
231 .readarr = NULL,
232 }};
233
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100234 int result = spi_send_multicommand(flash, cmds);
David Hendricks398714f2014-07-03 17:49:41 -0700235 if (result) {
236 msg_cerr("%s failed during command execution at address 0x%x\n",
237 __func__, addr);
David Hendricks688b5e22014-12-12 11:15:44 -0800238 return -1;
David Hendricks398714f2014-07-03 17:49:41 -0700239 }
240
David Hendricks43d9afd2015-03-13 20:54:23 -0700241 programmer_delay(T_W);
242 return s25f_poll_status(flash);
David Hendricks398714f2014-07-03 17:49:41 -0700243}
244
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700245static int s25f_write_cr1(const struct flashctx *flash, uint8_t data)
David Hendricks398714f2014-07-03 17:49:41 -0700246{
247 int result;
248 struct spi_command cmds[] = {
249 {
David Hendricks43d9afd2015-03-13 20:54:23 -0700250 .writecnt = JEDEC_WREN_OUTSIZE,
251 .writearr = (const unsigned char[]){ JEDEC_WREN },
David Hendricks398714f2014-07-03 17:49:41 -0700252 .readcnt = 0,
253 .readarr = NULL,
254 }, {
David Hendricks43d9afd2015-03-13 20:54:23 -0700255 .writecnt = CMD_WRR_LEN,
256 .writearr = (const unsigned char[]){
257 CMD_WRR,
Ramya Vijaykumar4af3f822016-01-27 11:51:27 +0530258 spi_read_status_register(flash),
David Hendricks43d9afd2015-03-13 20:54:23 -0700259 data,
260 },
David Hendricks398714f2014-07-03 17:49:41 -0700261 .readcnt = 0,
262 .readarr = NULL,
263 }, {
264 .writecnt = 0,
265 .writearr = NULL,
266 .readcnt = 0,
267 .readarr = NULL,
268 }};
269
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700270 result = spi_send_multicommand(flash, cmds);
David Hendricks398714f2014-07-03 17:49:41 -0700271 if (result) {
272 msg_cerr("%s failed during command execution\n", __func__);
David Hendricks43d9afd2015-03-13 20:54:23 -0700273 return -1;
David Hendricks398714f2014-07-03 17:49:41 -0700274 }
275
David Hendricks43d9afd2015-03-13 20:54:23 -0700276 programmer_delay(T_W);
277 return s25f_poll_status(flash);
David Hendricks398714f2014-07-03 17:49:41 -0700278}
279
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700280static int s25fs_restore_cr3nv(struct flashctx *flash, uint8_t cfg)
David Hendricks398714f2014-07-03 17:49:41 -0700281{
282 int ret = 0;
283
284 msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg);
David Hendricks636c74a2014-12-12 11:30:00 -0800285 ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg);
David Hendricks398714f2014-07-03 17:49:41 -0700286 ret |= s25fs_software_reset(flash);
287 return ret;
288}
289
David Hendricksa9884852014-12-11 15:31:12 -0800290/* returns state of top/bottom block protection, or <0 to indicate error */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700291static int s25f_get_tbprot_o(const struct flashctx *flash)
David Hendricksa9884852014-12-11 15:31:12 -0800292{
David Hendricks43d9afd2015-03-13 20:54:23 -0700293 int cr1 = s25f_read_cr1(flash);
David Hendricksa9884852014-12-11 15:31:12 -0800294
David Hendricks43d9afd2015-03-13 20:54:23 -0700295 if (cr1 < 0)
David Hendricksa9884852014-12-11 15:31:12 -0800296 return -1;
297
298 /*
299 * 1 = BP starts at bottom (low address)
300 * 0 = BP start at top (high address)
301 */
David Hendricks43d9afd2015-03-13 20:54:23 -0700302 return cr1 & CR1_TBPROT_O ? 1 : 0;
David Hendricksa9884852014-12-11 15:31:12 -0800303}
304
David Hendricks148a4bf2015-03-13 21:02:42 -0700305/* fills modifier_bits struct, returns 0 to indicate success */
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700306int s25f_get_modifier_bits(const struct flashctx *flash,
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +1100307 struct modifier_bits *m)
David Hendricks148a4bf2015-03-13 21:02:42 -0700308{
309 int tmp;
310
311 memset(m, 0, sizeof(*m));
312
313 tmp = s25f_get_tbprot_o(flash);
314 if (tmp < 0)
315 return -1;
316 m->tb = tmp;
317
318 return 0;
319}
320
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700321int s25f_set_modifier_bits(const struct flashctx *flash,
Edward O'Callaghan9c4c9a52019-12-04 18:18:01 +1100322 struct modifier_bits *m)
David Hendricks148a4bf2015-03-13 21:02:42 -0700323{
324 int cr1, cr1_orig;
325
326 cr1 = cr1_orig = s25f_read_cr1(flash);
327 if (cr1 < 0)
328 return -1;
329
330 /*
331 * Clear BPNV so that setting BP2-0 in status register gets
332 * written to non-volatile memory.
333 *
334 * For TBPROT:
335 * 1 = BP starts at bottom (low address)
336 * 0 = BP start at top (high address)
337 */
338 cr1 &= ~(CR1_BPNV_O | CR1_TBPROT_O);
339 cr1 |= m->tb ? CR1_TBPROT_O : 0;
340
341 if (cr1 != cr1_orig) {
342 msg_cdbg("%s: setting cr1 bits to 0x%02x\n", __func__, cr1);
343 if (s25f_write_cr1(flash, cr1) < 0)
344 return -1;
345 if (s25f_read_cr1(flash) != cr1) {
346 msg_cerr("%s: failed to set CR1 value\n", __func__);
347 return -1;
348 }
349 } else {
350 msg_cdbg("%s: cr1 bits already match desired value: "
351 "0x%02x\n", __func__, cr1);
352 }
353
354 return 0;
355}
356
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700357int s25fs_block_erase_d8(struct flashctx *flash,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100358 uint32_t addr, uint32_t blocklen)
David Hendricks398714f2014-07-03 17:49:41 -0700359{
David Hendricks398714f2014-07-03 17:49:41 -0700360 static int cr3nv_checked = 0;
361
362 struct spi_command erase_cmds[] = {
363 {
364 .writecnt = JEDEC_WREN_OUTSIZE,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100365 .writearr = (const uint8_t[]){ JEDEC_WREN },
David Hendricks398714f2014-07-03 17:49:41 -0700366 .readcnt = 0,
367 .readarr = NULL,
368 }, {
369 .writecnt = JEDEC_BE_D8_OUTSIZE,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100370 .writearr = (const uint8_t[]){
David Hendricks398714f2014-07-03 17:49:41 -0700371 JEDEC_BE_D8,
372 (addr >> 16) & 0xff,
373 (addr >> 8) & 0xff,
374 (addr & 0xff)
375 },
376 .readcnt = 0,
377 .readarr = NULL,
378 }, {
379 .writecnt = 0,
380 .writearr = NULL,
381 .readcnt = 0,
382 .readarr = NULL,
383 }};
384
385 /* Check if hybrid sector architecture is in use and, if so,
386 * switch to uniform sectors. */
387 if (!cr3nv_checked) {
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100388 uint8_t cfg = s25fs_read_cr(flash, CR3NV_ADDR);
David Hendricks398714f2014-07-03 17:49:41 -0700389 if (!(cfg & CR3NV_20H_NV)) {
David Hendricks636c74a2014-12-12 11:30:00 -0800390 s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV);
David Hendricks398714f2014-07-03 17:49:41 -0700391 s25fs_software_reset(flash);
392
David Hendricks636c74a2014-12-12 11:30:00 -0800393 cfg = s25fs_read_cr(flash, CR3NV_ADDR);
David Hendricks398714f2014-07-03 17:49:41 -0700394 if (!(cfg & CR3NV_20H_NV)) {
395 msg_cerr("%s: Unable to enable uniform "
396 "block sizes.\n", __func__);
397 return 1;
398 }
399
400 msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n",
401 __func__, cfg,
David Hendricks636c74a2014-12-12 11:30:00 -0800402 s25fs_read_cr(flash, CR3NV_ADDR));
David Hendricks398714f2014-07-03 17:49:41 -0700403 /* Restore CR3V when flashrom exits */
404 register_chip_restore(s25fs_restore_cr3nv, flash, cfg);
405 }
406
407 cr3nv_checked = 1;
408 }
409
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100410 int result = spi_send_multicommand(flash, erase_cmds);
David Hendricks398714f2014-07-03 17:49:41 -0700411 if (result) {
412 msg_cerr("%s failed during command execution at address 0x%x\n",
413 __func__, addr);
414 return result;
415 }
416
David Hendricks43d9afd2015-03-13 20:54:23 -0700417 programmer_delay(S25FS_T_SE);
418 return s25f_poll_status(flash);
David Hendricks398714f2014-07-03 17:49:41 -0700419}
Vadim Bendebury3a501162014-10-21 20:38:13 -0700420
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700421int s25fl_block_erase(struct flashctx *flash,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100422 uint32_t addr, uint32_t blocklen)
Vadim Bendebury3a501162014-10-21 20:38:13 -0700423{
Vadim Bendebury3a501162014-10-21 20:38:13 -0700424 struct spi_command erase_cmds[] = {
425 {
426 .writecnt = JEDEC_WREN_OUTSIZE,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100427 .writearr = (const uint8_t[]){
Vadim Bendebury3a501162014-10-21 20:38:13 -0700428 JEDEC_WREN
429 },
430 .readcnt = 0,
431 .readarr = NULL,
432 }, {
433 .writecnt = JEDEC_BE_DC_OUTSIZE,
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100434 .writearr = (const uint8_t[]){
Vadim Bendebury3a501162014-10-21 20:38:13 -0700435 JEDEC_BE_DC,
436 (addr >> 24) & 0xff,
437 (addr >> 16) & 0xff,
438 (addr >> 8) & 0xff,
439 (addr & 0xff)
440 },
441 .readcnt = 0,
442 .readarr = NULL,
443 }, {
444 .writecnt = 0,
445 .readcnt = 0,
446 }
447 };
448
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100449 int result = spi_send_multicommand(flash, erase_cmds);
Vadim Bendebury3a501162014-10-21 20:38:13 -0700450 if (result) {
451 msg_cerr("%s failed during command execution at address 0x%x\n",
452 __func__, addr);
453 return result;
454 }
455
David Hendricks43d9afd2015-03-13 20:54:23 -0700456 programmer_delay(S25FL_T_SE);
457 return s25f_poll_status(flash);
Vadim Bendebury3a501162014-10-21 20:38:13 -0700458}
459
460
Souvik Ghoshd75cd672016-06-17 14:21:39 -0700461int probe_spi_big_spansion(struct flashctx *flash)
Vadim Bendebury3a501162014-10-21 20:38:13 -0700462{
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100463 uint8_t cmd = JEDEC_RDID;
464 uint8_t dev_id[6]; /* We care only about 6 first bytes */
Vadim Bendebury3a501162014-10-21 20:38:13 -0700465
Nikolai Artemiev077b66c2020-11-10 13:38:38 +1100466 if (spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id))
467 return 0;
Vadim Bendebury3a501162014-10-21 20:38:13 -0700468
Nikolai Artemiev7f23bbf2020-12-04 16:51:06 +1100469 msg_gdbg("Read id bytes: ");
Nikolai Artemiev077b66c2020-11-10 13:38:38 +1100470 for (size_t i = 0; i < sizeof(dev_id); i++)
471 msg_gdbg(" 0x%02x", dev_id[i]);
472 msg_gdbg(".\n");
Vadim Bendebury3a501162014-10-21 20:38:13 -0700473
Vadim Bendebury3a501162014-10-21 20:38:13 -0700474 /*
475 * The structure of the RDID output is as follows:
476 *
477 * offset value meaning
478 * 00h 01h Manufacturer ID for Spansion
479 * 01h 20h 128 Mb capacity
480 * 01h 02h 256 Mb capacity
481 * 02h 18h 128 Mb capacity
482 * 02h 19h 256 Mb capacity
483 * 03h 4Dh Full size of the RDID output (ignored)
484 * 04h 00h FS: 256-kB physical sectors
485 * 04h 01h FS: 64-kB physical sectors
486 * 04h 00h FL: 256-kB physical sectors
487 * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors
488 * 05h 80h FL family
489 * 05h 81h FS family
490 *
491 * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight
492 * possible chips:
493 *
494 * 2 types * 2 possible sizes * 2 possible sector layouts
495 *
496 */
Nikolai Artemiev4ce3bd22020-11-10 13:41:12 +1100497
498 uint32_t model_id =
499 dev_id[1] << 24 |
500 dev_id[2] << 16 |
501 dev_id[4] << 8 |
502 dev_id[5] << 0;
503
504 if (dev_id[0] == flash->chip->manufacture_id && model_id == flash->chip->model_id)
505 return 1;
506
Vadim Bendebury3a501162014-10-21 20:38:13 -0700507 return 0;
508}