Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2020 The Chromium OS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdlib.h> |
| 18 | #include <stdint.h> |
| 19 | #include <stdio.h> |
| 20 | #include <string.h> |
| 21 | #include <time.h> |
| 22 | #include <errno.h> |
| 23 | |
| 24 | #include "programmer.h" |
| 25 | #include "spi.h" |
| 26 | #include "i2c_helper.h" |
| 27 | |
| 28 | |
| 29 | #define MCU_I2C_SLAVE_ADDR 0x94 |
| 30 | #define REGISTER_ADDRESS (0x94 >> 1) |
| 31 | #define PAGE_SIZE 256 |
| 32 | #define MAX_SPI_WAIT_RETRIES 1000 |
| 33 | |
Edward O'Callaghan | 33653fd | 2020-05-04 13:01:54 +1000 | [diff] [blame] | 34 | #define MCU_MODE 0x6F |
| 35 | #define ENTER_ISP_MODE 0x80 |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 36 | #define START_WRITE_XFER 0xA0 |
| 37 | #define WRITE_XFER_STATUS_MASK 0x20 |
Edward O'Callaghan | 33653fd | 2020-05-04 13:01:54 +1000 | [diff] [blame] | 38 | |
| 39 | #define MCU_DATA_PORT 0x70 |
| 40 | |
| 41 | #define MAP_PAGE_BYTE2 0x64 |
| 42 | #define MAP_PAGE_BYTE1 0x65 |
| 43 | #define MAP_PAGE_BYTE0 0x66 |
| 44 | |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 45 | //opcodes |
| 46 | #define OPCODE_READ 3 |
| 47 | #define OPCODE_WRITE 2 |
| 48 | |
| 49 | |
| 50 | struct realtek_mst_i2c_spi_data { |
| 51 | int fd; |
| 52 | }; |
| 53 | |
| 54 | static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) |
| 55 | { |
| 56 | i2c_buffer_t data; |
| 57 | if (i2c_buffer_t_fill(&data, buf, len)) |
| 58 | return SPI_GENERIC_ERROR; |
| 59 | |
| 60 | return i2c_write(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR; |
| 61 | } |
| 62 | |
| 63 | static int realtek_mst_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len) |
| 64 | { |
| 65 | i2c_buffer_t data; |
| 66 | if (i2c_buffer_t_fill(&data, buf, len)) |
| 67 | return SPI_GENERIC_ERROR; |
| 68 | |
| 69 | return i2c_read(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR; |
| 70 | } |
| 71 | |
| 72 | static int get_fd_from_context(const struct flashctx *flash) |
| 73 | { |
| 74 | if (!flash || !flash->mst || !flash->mst->spi.data) { |
| 75 | msg_perr("Unable to extract fd from flash context.\n"); |
| 76 | return SPI_GENERIC_ERROR; |
| 77 | } |
| 78 | const struct realtek_mst_i2c_spi_data *data = |
| 79 | (const struct realtek_mst_i2c_spi_data *)flash->mst->spi.data; |
| 80 | |
| 81 | return data->fd; |
| 82 | } |
| 83 | |
| 84 | static int realtek_mst_i2c_spi_write_register(int fd, uint8_t reg, uint8_t value) |
| 85 | { |
| 86 | uint8_t command[] = { reg, value }; |
| 87 | return realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2); |
| 88 | } |
| 89 | |
| 90 | static int realtek_mst_i2c_spi_read_register(int fd, uint8_t reg, uint8_t *value) |
| 91 | { |
| 92 | uint8_t command[] = { reg }; |
| 93 | int ret = realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1); |
| 94 | ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1); |
| 95 | |
| 96 | return ret ? SPI_GENERIC_ERROR : 0; |
| 97 | } |
| 98 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 99 | static int realtek_mst_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask, int target) |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 100 | { |
| 101 | uint8_t val; |
| 102 | int tried = 0; |
| 103 | int ret = 0; |
| 104 | do { |
| 105 | ret |= realtek_mst_i2c_spi_read_register(fd, offset, &val); |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 106 | } while (!ret && ((val & mask) != target) && ++tried < MAX_SPI_WAIT_RETRIES); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 107 | |
| 108 | if (tried == MAX_SPI_WAIT_RETRIES) { |
| 109 | msg_perr("%s: Time out on sending command.\n", __func__); |
| 110 | return -MAX_SPI_WAIT_RETRIES; |
| 111 | } |
| 112 | |
| 113 | return (val & mask) ? SPI_GENERIC_ERROR : ret; |
| 114 | } |
| 115 | |
| 116 | static int realtek_mst_i2c_spi_enter_isp_mode(int fd) |
| 117 | { |
Edward O'Callaghan | 33653fd | 2020-05-04 13:01:54 +1000 | [diff] [blame] | 118 | int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, ENTER_ISP_MODE); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 119 | |
| 120 | // set internal osc divider register to default to speed up MCU |
| 121 | // 0x06A0 = 0x74 |
| 122 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); |
| 123 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x06); |
| 124 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xA0); |
| 125 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x74); |
| 126 | |
| 127 | return ret; |
| 128 | } |
| 129 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 130 | static int realtek_mst_i2c_execute_write(int fd) |
| 131 | { |
| 132 | int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, START_WRITE_XFER); |
| 133 | ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, WRITE_XFER_STATUS_MASK, 0); |
| 134 | return ret; |
| 135 | } |
| 136 | |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 137 | static int realtek_mst_i2c_spi_reset_mpu(int fd) |
| 138 | { |
| 139 | int ret = 0; |
| 140 | // 0xFFEE[1] = 1; |
| 141 | uint8_t val = 0; |
| 142 | ret |= realtek_mst_i2c_spi_read_register(fd, 0xEE, &val); |
| 143 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xEE, (val & 0xFD) | 0x02); |
| 144 | return ret; |
| 145 | } |
| 146 | |
| 147 | #if 0 |
| 148 | static int realtek_mst_i2c_spi_set_defaults(int fd) |
| 149 | { |
| 150 | // 0xFF1B = 0x02; |
| 151 | int ret = realtek_mst_i2c_spi_write_register(fd, 0x1B, 0x02); |
| 152 | ret = realtek_mst_i2c_spi_write_register(fd, 0x1C, 0x30); |
| 153 | ret = realtek_mst_i2c_spi_write_register(fd, 0x1D, 0x1C); |
| 154 | ret = realtek_mst_i2c_spi_write_register(fd, 0x1E, 0x02); |
| 155 | ret = realtek_mst_i2c_spi_write_register(fd, 0x1F, 0x00); |
| 156 | |
| 157 | ret = realtek_mst_i2c_spi_write_register(fd, 0x20, 0x1C); |
| 158 | ret = realtek_mst_i2c_spi_write_register(fd, 0x2C, 0x02); |
| 159 | ret = realtek_mst_i2c_spi_write_register(fd, 0x2D, 0x00); |
| 160 | ret = realtek_mst_i2c_spi_write_register(fd, 0x2E, 0x1C); |
| 161 | |
| 162 | ret = realtek_mst_i2c_spi_write_register(fd, 0x62, 0x06); |
| 163 | ret = realtek_mst_i2c_spi_write_register(fd, 0x6A, 0x03); |
| 164 | ret = realtek_mst_i2c_spi_write_register(fd, 0x6B, 0x0B); |
| 165 | ret = realtek_mst_i2c_spi_write_register(fd, 0x6C, 0x00); |
| 166 | |
| 167 | ret = realtek_mst_i2c_spi_write_register(fd, 0xED, 0x88); |
| 168 | ret = realtek_mst_i2c_spi_write_register(fd, 0xEE, 0x04); |
| 169 | |
| 170 | return ret; |
| 171 | } |
| 172 | #endif |
| 173 | |
| 174 | static int realtek_mst_i2c_spi_disable_protection(int fd) |
| 175 | { |
| 176 | int ret = 0; |
| 177 | uint8_t val = 0; |
| 178 | // 0xAB[2:0] = b001 |
| 179 | |
| 180 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); |
| 181 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x10); |
| 182 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xAB); |
| 183 | |
| 184 | ret |= realtek_mst_i2c_spi_read_register(fd, 0xF5, &val); |
| 185 | |
| 186 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); |
| 187 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x10); |
| 188 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xAB); |
| 189 | |
| 190 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, (val & 0xF8) | 0x01); |
| 191 | |
| 192 | /* Set pin value to high, 0xFFD7[0] = 1. */ |
| 193 | ret |= realtek_mst_i2c_spi_read_register(fd, 0xD7, &val); |
| 194 | ret |= realtek_mst_i2c_spi_write_register(fd, 0xD7, (val & 0xFE) | 0x01); |
| 195 | |
| 196 | return ret; |
| 197 | } |
| 198 | |
| 199 | static int realtek_mst_i2c_spi_send_command(const struct flashctx *flash, |
| 200 | unsigned int writecnt, unsigned int readcnt, |
| 201 | const unsigned char *writearr, |
| 202 | unsigned char *readarr) |
| 203 | { |
| 204 | unsigned i; |
| 205 | int ret = 0; |
| 206 | |
| 207 | if (writecnt > 4 || readcnt > 3 || writecnt == 0) { |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 208 | return SPI_GENERIC_ERROR; |
| 209 | } |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 210 | |
| 211 | int fd = get_fd_from_context(flash); |
| 212 | if (fd < 0) |
| 213 | return SPI_GENERIC_ERROR; |
| 214 | |
Edward O'Callaghan | 562ed8e | 2020-05-06 15:24:25 +1000 | [diff] [blame] | 215 | /* First byte of writearr should be the spi opcode value, followed by the value to write. */ |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 216 | writecnt--; |
Edward O'Callaghan | 562ed8e | 2020-05-06 15:24:25 +1000 | [diff] [blame] | 217 | |
| 218 | /** |
| 219 | * Before dispatching a SPI opcode the MCU register 0x60 requires |
| 220 | * the following configuration byte set: |
| 221 | * |
| 222 | * BIT0 - start [0] , end [1]. |
| 223 | * BITS[1-4] - counts. |
| 224 | * BITS[5-7] - opcode type. |
| 225 | * |
| 226 | * | bit7 | bit6 | bit5 | |
| 227 | * +------+------+------+ |
| 228 | * | 0 | 1 | 0 | ~ JEDEC_RDID,REMS,READ |
| 229 | * | 0 | 1 | 1 | ~ JEDEC_WRSR |
| 230 | * | 1 | 0 | 1 | ~ JEDEC_.. erasures. |
| 231 | */ |
| 232 | uint8_t ctrl_reg_val = (writecnt << 3) | (readcnt << 1); |
| 233 | switch (writearr[0]) { |
| 234 | /* WREN isn't a supported somehow? ignore it. */ |
| 235 | case JEDEC_WREN: return 0; |
| 236 | /* WRSR requires BIT6 && BIT5 set. */ |
| 237 | case JEDEC_WRSR: |
| 238 | ctrl_reg_val |= (1 << 5); |
| 239 | ctrl_reg_val |= (2 << 5); |
| 240 | break; |
| 241 | /* Erasures require BIT7 && BIT5 set. */ |
| 242 | case JEDEC_CE_60: |
| 243 | case JEDEC_CE_C7: |
| 244 | case JEDEC_BE_52: |
| 245 | case JEDEC_BE_D8: |
| 246 | case JEDEC_BE_D7: |
| 247 | case JEDEC_SE: |
| 248 | ctrl_reg_val |= (1 << 5); |
| 249 | ctrl_reg_val |= (4 << 5); |
| 250 | break; |
| 251 | default: |
| 252 | /* Otherwise things like RDID,REMS,READ require BIT6 */ |
| 253 | ctrl_reg_val |= (2 << 5); |
| 254 | } |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 255 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); |
Edward O'Callaghan | 562ed8e | 2020-05-06 15:24:25 +1000 | [diff] [blame] | 256 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 257 | |
| 258 | for (i = 0; i < writecnt; ++i) |
| 259 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); |
| 260 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); |
| 261 | if (ret) |
| 262 | return ret; |
| 263 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 264 | ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01, 0); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 265 | if (ret) |
| 266 | return ret; |
| 267 | |
| 268 | for (i = 0; i < readcnt; ++i) |
| 269 | ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); |
| 270 | |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 271 | return ret; |
| 272 | } |
| 273 | |
| 274 | static int realtek_mst_i2c_spi_map_page(int fd, uint8_t block_idx, uint8_t page_idx, uint8_t byte_idx) |
| 275 | { |
| 276 | int ret = 0; |
Edward O'Callaghan | 33653fd | 2020-05-04 13:01:54 +1000 | [diff] [blame] | 277 | ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE2, block_idx); |
| 278 | ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE1, page_idx); |
| 279 | ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE0, byte_idx); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 280 | |
| 281 | return ret ? SPI_GENERIC_ERROR : 0; |
| 282 | } |
| 283 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 284 | static int realtek_mst_i2c_spi_write_page(int fd, uint8_t reg, const uint8_t *buf, unsigned int len) |
| 285 | { |
| 286 | /** |
| 287 | * Using static buffer with maximum possible size, |
| 288 | * extra byte is needed for prefixing the data port register at index 0. |
| 289 | */ |
| 290 | uint8_t wbuf[PAGE_SIZE + 1] = { MCU_DATA_PORT }; |
| 291 | if (len > PAGE_SIZE) |
| 292 | return SPI_GENERIC_ERROR; |
| 293 | |
| 294 | memcpy(&wbuf[1], buf, len); |
| 295 | |
| 296 | return realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, wbuf, len + 1); |
| 297 | } |
| 298 | |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 299 | static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, |
| 300 | unsigned int start, unsigned int len) |
| 301 | { |
| 302 | unsigned i; |
| 303 | int ret = 0; |
| 304 | |
| 305 | if (start & 0xff) |
| 306 | return default_spi_read(flash, buf, start, len); |
| 307 | |
| 308 | int fd = get_fd_from_context(flash); |
| 309 | if (fd < 0) |
| 310 | return SPI_GENERIC_ERROR; |
| 311 | |
| 312 | start--; |
| 313 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** |
| 314 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ); |
| 315 | uint8_t block_idx = start >> 16; |
| 316 | uint8_t page_idx = start >> 8; |
| 317 | uint8_t byte_idx = start; |
| 318 | ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); |
| 319 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); |
| 320 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** |
| 321 | if (ret) |
| 322 | return ret; |
| 323 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 324 | ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01, 0); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 325 | if (ret) |
| 326 | return ret; |
| 327 | |
| 328 | /** |
| 329 | * The first byte is just a null, probably a status code? |
| 330 | * Advance the read by a offset of one byte and continue. |
| 331 | */ |
| 332 | uint8_t dummy; |
Edward O'Callaghan | 33653fd | 2020-05-04 13:01:54 +1000 | [diff] [blame] | 333 | realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 334 | |
| 335 | for (i = 0; i < len; i += PAGE_SIZE) { |
| 336 | ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, |
| 337 | buf + i, min(len - i, PAGE_SIZE)); |
| 338 | if (ret) |
| 339 | return ret; |
| 340 | } |
| 341 | |
| 342 | return ret; |
| 343 | } |
| 344 | |
| 345 | static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, |
| 346 | unsigned int start, unsigned int len) |
| 347 | { |
| 348 | unsigned i; |
| 349 | int ret = 0; |
| 350 | |
| 351 | if (start & 0xff) |
| 352 | return default_spi_write_256(flash, buf, start, len); |
| 353 | |
| 354 | int fd = get_fd_from_context(flash); |
| 355 | if (fd < 0) |
| 356 | return SPI_GENERIC_ERROR; |
| 357 | |
| 358 | ret = realtek_mst_i2c_spi_disable_protection(fd); |
| 359 | if (ret) |
| 360 | return ret; |
| 361 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 362 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */ |
| 363 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (PAGE_SIZE - 1)); /* fit len=256 */ |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 364 | |
| 365 | for (i = 0; i < len; i += PAGE_SIZE) { |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 366 | uint16_t page_len = min(len - i, PAGE_SIZE); |
| 367 | if (len - i < PAGE_SIZE) |
| 368 | ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); |
| 369 | uint8_t block_idx = (start + i) >> 16; |
| 370 | uint8_t page_idx = (start + i) >> 8; |
| 371 | ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, 0); |
| 372 | if (ret) |
| 373 | break; |
| 374 | |
| 375 | /* Wait for empty buffer. */ |
| 376 | ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, 0x10, 0x10); |
| 377 | if (ret) |
| 378 | break; |
| 379 | |
| 380 | ret |= realtek_mst_i2c_spi_write_page(fd, MCU_DATA_PORT, |
| 381 | buf + i, page_len); |
| 382 | if (ret) |
| 383 | break; |
| 384 | ret |= realtek_mst_i2c_execute_write(fd); |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 385 | if (ret) |
| 386 | break; |
| 387 | } |
| 388 | |
Edward O'Callaghan | 387632a | 2020-05-06 16:16:47 +1000 | [diff] [blame^] | 389 | |
Edward O'Callaghan | 97dd926 | 2020-03-26 00:00:41 +1100 | [diff] [blame] | 390 | /* TODO: re-enable the write protection? */ |
| 391 | |
| 392 | return ret; |
| 393 | } |
| 394 | |
| 395 | static int realtek_mst_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, |
| 396 | unsigned int start, unsigned int len) |
| 397 | { |
| 398 | msg_perr("%s: AAI write function is not supported.\n", __func__); |
| 399 | return SPI_GENERIC_ERROR; |
| 400 | } |
| 401 | |
| 402 | static struct spi_master spi_master_i2c_realtek_mst = { |
| 403 | .max_data_read = 16, |
| 404 | .max_data_write = 8, |
| 405 | .command = realtek_mst_i2c_spi_send_command, |
| 406 | .multicommand = default_spi_send_multicommand, |
| 407 | .read = realtek_mst_i2c_spi_read, |
| 408 | .write_256 = realtek_mst_i2c_spi_write_256, |
| 409 | .write_aai = realtek_mst_i2c_spi_write_aai, |
| 410 | }; |
| 411 | |
| 412 | static int realtek_mst_i2c_spi_shutdown(void *data) |
| 413 | { |
| 414 | int ret = 0; |
| 415 | struct realtek_mst_i2c_spi_data *realtek_mst_data = |
| 416 | (struct realtek_mst_i2c_spi_data *)data; |
| 417 | int fd = realtek_mst_data->fd; |
| 418 | ret |= realtek_mst_i2c_spi_reset_mpu(fd); |
| 419 | i2c_close(fd); |
| 420 | free(data); |
| 421 | |
| 422 | return ret; |
| 423 | } |
| 424 | |
| 425 | static int get_params(int *i2c_bus) |
| 426 | { |
| 427 | char *bus_str = NULL; |
| 428 | int ret = SPI_GENERIC_ERROR; |
| 429 | |
| 430 | bus_str = extract_programmer_param("bus"); |
| 431 | if (bus_str) { |
| 432 | char *bus_suffix; |
| 433 | errno = 0; |
| 434 | int bus = (int)strtol(bus_str, &bus_suffix, 10); |
| 435 | if (errno != 0 || bus_str == bus_suffix) { |
| 436 | msg_perr("%s: Could not convert 'bus'.\n", __func__); |
| 437 | goto get_params_done; |
| 438 | } |
| 439 | |
| 440 | if (bus < 0 || bus > 255) { |
| 441 | msg_perr("%s: Value for 'bus' is out of range(0-255).\n", __func__); |
| 442 | goto get_params_done; |
| 443 | } |
| 444 | |
| 445 | if (strlen(bus_suffix) > 0) { |
| 446 | msg_perr("%s: Garbage following 'bus' value.\n", __func__); |
| 447 | goto get_params_done; |
| 448 | } |
| 449 | |
| 450 | msg_pinfo("Using i2c bus %i.\n", bus); |
| 451 | *i2c_bus = bus; |
| 452 | ret = 0; |
| 453 | goto get_params_done; |
| 454 | } else { |
| 455 | msg_perr("%s: Bus number not specified.\n", __func__); |
| 456 | } |
| 457 | get_params_done: |
| 458 | if (bus_str) |
| 459 | free(bus_str); |
| 460 | |
| 461 | return ret; |
| 462 | } |
| 463 | |
| 464 | int realtek_mst_i2c_spi_init(void) |
| 465 | { |
| 466 | int ret = 0; |
| 467 | int i2c_bus = 0; |
| 468 | |
| 469 | if (get_params(&i2c_bus)) |
| 470 | return SPI_GENERIC_ERROR; |
| 471 | |
| 472 | int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); |
| 473 | if (fd < 0) |
| 474 | return fd; |
| 475 | |
| 476 | /* Ensure we are in a known state before entering ISP mode */ |
| 477 | ret |= realtek_mst_i2c_spi_reset_mpu(fd); |
| 478 | if (ret) |
| 479 | return ret; |
| 480 | |
| 481 | ret |= realtek_mst_i2c_spi_enter_isp_mode(fd); |
| 482 | if (ret) |
| 483 | return ret; |
| 484 | // XXX: maybe make into a mode:defaults cli param? |
| 485 | #if 0 |
| 486 | ret |= realtek_mst_i2c_spi_set_defaults(fd); |
| 487 | if (ret) |
| 488 | return ret; |
| 489 | #endif |
| 490 | |
| 491 | struct realtek_mst_i2c_spi_data *data = calloc(1, sizeof(struct realtek_mst_i2c_spi_data)); |
| 492 | if (!data) { |
| 493 | msg_perr("Unable to allocate space for extra SPI master data.\n"); |
| 494 | return SPI_GENERIC_ERROR; |
| 495 | } |
| 496 | |
| 497 | data->fd = fd; |
| 498 | ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); |
| 499 | |
| 500 | spi_master_i2c_realtek_mst.data = data; |
| 501 | ret |= register_spi_master(&spi_master_i2c_realtek_mst); |
| 502 | |
| 503 | return ret; |
| 504 | } |