Add Tegra2 SPI controller.
Co-worked with David Hendrix (dhendrix@) to finalize this difficult tasks. The credits of porting to ARM platform go to Stefan (reinauer@).
Original code comes from u-boot, and is adapted to flashrom call model. The main change is fixing the endian issue (refer to next4Bytes(), for multiple bytes write/read in one GO). Another is we move UART disable in spi_init() so that there is no delay between every CS activate. We get quite good results (see TEST field below).
Change-Id: Ica523803491c270059584695b3cff0cb68234425
R=dhendrix@chromium.org
BUG=chrome-os-partner:2825
TEST=Tested the following cases on Tegra2 Seaboard. Compiled successfully and tested on x86.
% flashrom -V | grep Found
W25Q16 ...
% flashrom --wp-status
% flashrom --wp-range 0x100000 0x100000
% flashrom --wp-range 0 0
% flashrom --wp-enable
% flashrom --wp-disable
% flashrom -r /tmp/flash
(it takes 5.6 secs, w/o fmap search)
% flashrom -w /tmp/diff_content
(it takes 32.6 secs, w/o fmap search)
% flashrom -E
(it takes 20.8 secs, w/o fmap search)
Review URL: http://codereview.chromium.org/6731011
diff --git a/programmer.h b/programmer.h
index d6ba8a0..373a63d 100644
--- a/programmer.h
+++ b/programmer.h
@@ -523,6 +523,9 @@
SPI_CONTROLLER_MCP6X_BITBANG,
SPI_CONTROLLER_WPCE775X,
#endif
+#if defined(__arm__)
+ SPI_CONTROLLER_TEGRA2,
+#endif
#endif
#if CONFIG_FT2232_SPI == 1
SPI_CONTROLLER_FT2232,
@@ -660,4 +663,15 @@
int serialport_write(unsigned char *buf, unsigned int writecnt);
int serialport_read(unsigned char *buf, unsigned int readcnt);
+
+/* tegra2_spi.c */
+#if CONFIG_INTERNAL == 1
+int tegra2_spi_init(void);
+void tegra2_spi_shutdown(void*);
+int tegra2_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
+int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
+int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len);
+#endif
+
#endif /* !__PROGRAMMER_H__ */