blob: aee3055a7849164297a124a5d163d00d419cdf6d [file] [log] [blame]
Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
Daniele Castagna7a755de2016-12-16 17:32:30 -05002 * Copyright 2014 The Chromium OS Authors. All rights reserved.
Stéphane Marchesin25a26062014-09-12 16:18:59 -07003 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_I915
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
9#include <errno.h>
Gurchetan Singh82a8eed2017-01-03 13:01:37 -080010#include <i915_drm.h>
Gurchetan Singhcc015e82017-01-17 16:15:25 -080011#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070012#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070013#include <sys/mman.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070014#include <xf86drm.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070015
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070016#include "drv_priv.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070017#include "helpers.h"
18#include "util.h"
19
Gurchetan Singh68af9c22017-01-18 13:48:11 -080020#define I915_CACHELINE_SIZE 64
21#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
22
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070023static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
24 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
25 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
26 DRM_FORMAT_XRGB8888 };
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080027
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070028static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
29 DRM_FORMAT_UYVY, DRM_FORMAT_YUYV };
30
31static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Gurchetan Singh179687e2016-10-28 10:07:35 -070032
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080033struct i915_device {
Gurchetan Singh68af9c22017-01-18 13:48:11 -080034 uint32_t gen;
35 int32_t has_llc;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070036};
37
Gurchetan Singh68af9c22017-01-18 13:48:11 -080038static uint32_t i915_get_gen(int device_id)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070039{
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080040 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
41 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
Stéphane Marchesina39dfde2014-09-15 15:38:25 -070042 unsigned i;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080043 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070044 if (gen3_ids[i] == device_id)
45 return 3;
46
47 return 4;
48}
49
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080050static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
51{
52 uint32_t i;
53 struct combination *combo;
54
55 /*
56 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
57 * report this functionality via format modifiers.
58 */
59 for (i = 0; i < drv->backend->combos.size; i++) {
60 combo = &drv->backend->combos.data[i];
61 if (combo->format == item->format) {
62 if ((combo->metadata.tiling == I915_TILING_Y &&
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080063 item->modifier == I915_FORMAT_MOD_Y_TILED) ||
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080064 (combo->metadata.tiling == I915_TILING_X &&
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080065 item->modifier == I915_FORMAT_MOD_X_TILED)) {
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080066 combo->metadata.modifier = item->modifier;
67 combo->usage |= item->usage;
68 } else if (combo->metadata.tiling != I915_TILING_Y) {
69 combo->usage |= item->usage;
70 }
71 }
72 }
73
74 return 0;
75}
76
77static int i915_add_combinations(struct driver *drv)
78{
79 int ret;
80 uint32_t i, num_items;
81 struct kms_item *items;
82 struct format_metadata metadata;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070083 uint64_t render_flags, texture_flags;
84
85 render_flags = BO_USE_RENDER_MASK;
86 texture_flags = BO_USE_TEXTURE_MASK;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080087
88 metadata.tiling = I915_TILING_NONE;
89 metadata.priority = 1;
90 metadata.modifier = DRM_FORMAT_MOD_NONE;
91
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070092 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
93 &metadata, render_flags);
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080094 if (ret)
95 return ret;
96
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070097 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
98 &metadata, texture_flags);
99 if (ret)
100 return ret;
101
102 ret = drv_add_combinations(drv, tileable_texture_source_formats,
103 ARRAY_SIZE(texture_source_formats), &metadata, texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800104 if (ret)
105 return ret;
106
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800107 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
108 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800109
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700110 render_flags &= ~BO_USE_SW_WRITE_OFTEN;
111 render_flags &= ~BO_USE_SW_READ_OFTEN;
112 render_flags &= ~BO_USE_LINEAR;
113
114 texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
115 texture_flags &= ~BO_USE_SW_READ_OFTEN;
116 texture_flags &= ~BO_USE_LINEAR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800117
118 metadata.tiling = I915_TILING_X;
119 metadata.priority = 2;
120
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700121 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
122 &metadata, render_flags);
123 if (ret)
124 return ret;
125
126 ret = drv_add_combinations(drv, tileable_texture_source_formats,
127 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
128 texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800129 if (ret)
130 return ret;
131
132 metadata.tiling = I915_TILING_Y;
133 metadata.priority = 3;
134
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700135 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
136 &metadata, render_flags);
137 if (ret)
138 return ret;
139
140 ret = drv_add_combinations(drv, tileable_texture_source_formats,
141 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
142 texture_flags);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800143 if (ret)
144 return ret;
145
146 items = drv_query_kms(drv, &num_items);
147 if (!items || !num_items)
148 return 0;
149
150 for (i = 0; i < num_items; i++) {
151 ret = i915_add_kms_item(drv, &items[i]);
152 if (ret) {
153 free(items);
154 return ret;
155 }
156 }
157
158 free(items);
159 return 0;
160}
161
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800162static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
163 uint32_t *aligned_height)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700164{
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700165 struct i915_device *i915 = bo->drv->priv;
166 uint32_t horizontal_alignment = 4;
167 uint32_t vertical_alignment = 4;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700168
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700169 switch (tiling) {
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700170 default:
171 case I915_TILING_NONE:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700172 horizontal_alignment = 64;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700173 break;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800174
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700175 case I915_TILING_X:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700176 horizontal_alignment = 512;
177 vertical_alignment = 8;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700178 break;
179
180 case I915_TILING_Y:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700181 if (i915->gen == 3) {
182 horizontal_alignment = 512;
183 vertical_alignment = 8;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800184 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700185 horizontal_alignment = 128;
186 vertical_alignment = 32;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700187 }
188 break;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700189 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800190
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700191 *aligned_height = ALIGN(bo->height, vertical_alignment);
192 if (i915->gen > 3) {
193 *stride = ALIGN(*stride, horizontal_alignment);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800194 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700195 while (*stride > horizontal_alignment)
196 horizontal_alignment <<= 1;
197
198 *stride = horizontal_alignment;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800199 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800200
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700201 if (i915->gen <= 3 && *stride > 8192)
202 return -EINVAL;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800203
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700204 return 0;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700205}
206
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800207static void i915_clflush(void *start, size_t size)
208{
209 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
210 void *end = (void *)((uintptr_t)start + size);
211
212 __builtin_ia32_mfence();
213 while (p < end) {
214 __builtin_ia32_clflush(p);
215 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
216 }
217}
218
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800219static int i915_init(struct driver *drv)
220{
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800221 int ret;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800222 int device_id;
223 struct i915_device *i915;
224 drm_i915_getparam_t get_param;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800225
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800226 i915 = calloc(1, sizeof(*i915));
227 if (!i915)
228 return -ENOMEM;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800229
230 memset(&get_param, 0, sizeof(get_param));
231 get_param.param = I915_PARAM_CHIPSET_ID;
232 get_param.value = &device_id;
233 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
234 if (ret) {
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800235 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800236 free(i915);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800237 return -EINVAL;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800238 }
239
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800240 i915->gen = i915_get_gen(device_id);
241
242 memset(&get_param, 0, sizeof(get_param));
243 get_param.param = I915_PARAM_HAS_LLC;
244 get_param.value = &i915->has_llc;
245 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
246 if (ret) {
247 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
248 free(i915);
249 return -EINVAL;
250 }
251
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800252 drv->priv = i915;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800253
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800254 return i915_add_combinations(drv);
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800255}
256
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800257static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
258 uint32_t flags)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700259{
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700260 int ret;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800261 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700262 uint32_t stride;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800263 struct drm_i915_gem_create gem_create;
264 struct drm_i915_gem_set_tiling gem_set_tiling;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700265
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800266 if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800267 bo->tiling = I915_TILING_NONE;
Gurchetan Singh458976f2016-11-23 17:32:33 -0800268 else if (flags & BO_USE_SCANOUT)
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800269 bo->tiling = I915_TILING_X;
Gurchetan Singh6bab0c12016-10-13 19:08:48 -0700270 else
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800271 bo->tiling = I915_TILING_Y;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700272
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800273 stride = drv_stride_from_format(format, width, 0);
Gurchetan Singh507f5dd2017-03-16 13:14:30 -0700274 /*
275 * Align the Y plane to 128 bytes so the chroma planes would be aligned
276 * to 64 byte boundaries. This is an Intel HW requirement.
277 */
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800278 if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID) {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700279 stride = ALIGN(stride, 128);
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800280 bo->tiling = I915_TILING_NONE;
Gurchetan Singh507f5dd2017-03-16 13:14:30 -0700281 }
282
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800283 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700284 if (ret)
285 return ret;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800286
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700287 drv_bo_from_format(bo, stride, height, format);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800288
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800289 memset(&gem_create, 0, sizeof(gem_create));
290 gem_create.size = bo->total_size;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800291
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800292 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
293 if (ret) {
294 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
295 gem_create.size);
296 return ret;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700297 }
Gurchetan Singh83dc4fb2016-07-19 15:52:33 -0700298
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800299 for (plane = 0; plane < bo->num_planes; plane++)
300 bo->handles[plane].u32 = gem_create.handle;
Daniel Nicoara1de26dc2014-09-25 18:53:19 -0400301
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800302 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
303 gem_set_tiling.handle = bo->handles[0].u32;
304 gem_set_tiling.tiling_mode = bo->tiling;
305 gem_set_tiling.stride = bo->strides[0];
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700306
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800307 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
308 if (ret) {
309 struct drm_gem_close gem_close;
310 memset(&gem_close, 0, sizeof(gem_close));
311 gem_close.handle = bo->handles[0].u32;
312 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800313
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800314 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700315 return -errno;
316 }
317
318 return 0;
319}
320
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800321static void i915_close(struct driver *drv)
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800322{
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800323 free(drv->priv);
324 drv->priv = NULL;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800325}
326
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800327static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
328{
329 int ret;
330 struct drm_i915_gem_get_tiling gem_get_tiling;
331
332 ret = drv_prime_bo_import(bo, data);
333 if (ret)
334 return ret;
335
336 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
337 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
338 gem_get_tiling.handle = bo->handles[0].u32;
339
340 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
341 if (ret) {
342 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
343 return ret;
344 }
345
346 bo->tiling = gem_get_tiling.tiling_mode;
347 return 0;
348}
349
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700350static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
Gurchetan Singhef920532016-08-12 16:38:25 -0700351{
352 int ret;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800353 void *addr;
354 struct drm_i915_gem_set_domain set_domain;
Gurchetan Singhef920532016-08-12 16:38:25 -0700355
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800356 memset(&set_domain, 0, sizeof(set_domain));
357 set_domain.handle = bo->handles[0].u32;
358 if (bo->tiling == I915_TILING_NONE) {
359 struct drm_i915_gem_mmap gem_map;
360 memset(&gem_map, 0, sizeof(gem_map));
Gurchetan Singhef920532016-08-12 16:38:25 -0700361
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800362 gem_map.handle = bo->handles[0].u32;
363 gem_map.offset = 0;
364 gem_map.size = bo->total_size;
365
366 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
367 if (ret) {
368 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
369 return MAP_FAILED;
370 }
371
372 addr = (void *)(uintptr_t)gem_map.addr_ptr;
373 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
374 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
375
376 } else {
377 struct drm_i915_gem_mmap_gtt gem_map;
378 memset(&gem_map, 0, sizeof(gem_map));
379
380 gem_map.handle = bo->handles[0].u32;
381
382 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
383 if (ret) {
384 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
385 return MAP_FAILED;
386 }
387
388 addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
389 gem_map.offset);
390
391 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
392 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
393 }
394
395 if (addr == MAP_FAILED) {
396 fprintf(stderr, "drv: i915 GEM mmap failed\n");
397 return addr;
398 }
399
400 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
Gurchetan Singhef920532016-08-12 16:38:25 -0700401 if (ret) {
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800402 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
Gurchetan Singhef920532016-08-12 16:38:25 -0700403 return MAP_FAILED;
404 }
405
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800406 data->length = bo->total_size;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800407 return addr;
408}
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700409
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800410static int i915_bo_unmap(struct bo *bo, struct map_info *data)
411{
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800412 struct i915_device *i915 = bo->drv->priv;
413 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
414 i915_clflush(data->addr, data->length);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800415
416 return munmap(data->addr, data->length);
Gurchetan Singhef920532016-08-12 16:38:25 -0700417}
418
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800419static uint32_t i915_resolve_format(uint32_t format)
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700420{
421 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800422 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700423 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800424 return DRM_FORMAT_XBGR8888;
425 case DRM_FORMAT_FLEX_YCbCr_420_888:
Gurchetan Singh03f13562017-02-08 15:21:14 -0800426 return DRM_FORMAT_YVU420_ANDROID;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700427 default:
428 return format;
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700429 }
430}
431
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800432struct backend backend_i915 = {
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700433 .name = "i915",
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700434 .init = i915_init,
435 .close = i915_close,
436 .bo_create = i915_bo_create,
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800437 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800438 .bo_import = i915_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700439 .bo_map = i915_bo_map,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800440 .bo_unmap = i915_bo_unmap,
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700441 .resolve_format = i915_resolve_format,
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700442};
443
444#endif