blob: 1195a24ee4bfa0e31a326fb25c6ec57001e271fb [file] [log] [blame]
Rajesh Yadav7f79cb52018-01-22 18:29:06 +05301/*
2 * Copyright 2018 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7#ifdef DRV_MSM
8
Tanmay Shah067594b2018-11-26 10:05:18 -08009#include <assert.h>
10#include <drm_fourcc.h>
Tanmay Shah617ee712018-07-11 16:41:05 -070011#include <errno.h>
12#include <msm_drm.h>
Tanmay Shah067594b2018-11-26 10:05:18 -080013#include <stdbool.h>
Tanmay Shah617ee712018-07-11 16:41:05 -070014#include <stdio.h>
15#include <string.h>
16#include <sys/mman.h>
17#include <xf86drm.h>
18
Rajesh Yadav7f79cb52018-01-22 18:29:06 +053019#include "drv_priv.h"
20#include "helpers.h"
21#include "util.h"
22
Tanmay Shah067594b2018-11-26 10:05:18 -080023/* Alignment values are based on SDM845 Gfx IP */
Tanmay Shah617ee712018-07-11 16:41:05 -070024#define DEFAULT_ALIGNMENT 64
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080025#define BUFFER_SIZE_ALIGN 4096
26
27#define VENUS_STRIDE_ALIGN 128
28#define VENUS_SCANLINE_ALIGN 16
29#define NV12_LINEAR_PADDING (12 * 1024)
Tanmay Shah067594b2018-11-26 10:05:18 -080030#define NV12_UBWC_PADDING(y_stride) (MAX(16 * 1024, y_stride * 48))
31#define MACROTILE_WIDTH_ALIGN 64
32#define MACROTILE_HEIGHT_ALIGN 16
33#define PLANE_SIZE_ALIGN 4096
34
35#define MSM_UBWC_TILING 1
Stéphane Marchesin23e006a2018-02-28 16:37:46 -080036
Gurchetan Singhb131c9d2018-08-28 14:17:05 -070037static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
Gurchetan Singh71bc6652018-09-17 17:42:05 -070038 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
39 DRM_FORMAT_XRGB8888 };
Rajesh Yadav7f79cb52018-01-22 18:29:06 +053040
Tanmay Shah617ee712018-07-11 16:41:05 -070041static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_R8,
42 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Alexandre Courbot1805a9b2018-05-21 19:05:10 +090043
Tanmay Shah067594b2018-11-26 10:05:18 -080044/*
45 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
46 * Pixel data pitch/stride is aligned with macrotile width.
47 * Pixel data height is aligned with macrotile height.
48 * Entire pixel data buffer is aligned with 4k(bytes).
49 */
50static uint32_t get_ubwc_meta_size(uint32_t width, uint32_t height, uint32_t tile_width,
51 uint32_t tile_height)
52{
53 uint32_t macrotile_width, macrotile_height;
54
55 macrotile_width = DIV_ROUND_UP(width, tile_width);
56 macrotile_height = DIV_ROUND_UP(height, tile_height);
57
58 // Align meta buffer width to 64 blocks
59 macrotile_width = ALIGN(macrotile_width, MACROTILE_WIDTH_ALIGN);
60
61 // Align meta buffer height to 16 blocks
62 macrotile_height = ALIGN(macrotile_height, MACROTILE_HEIGHT_ALIGN);
63
64 return ALIGN(macrotile_width * macrotile_height, PLANE_SIZE_ALIGN);
65}
66
67static void msm_calculate_layout(struct bo *bo)
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080068{
69 uint32_t width, height;
70
71 width = bo->width;
72 height = bo->height;
73
74 /* NV12 format requires extra padding with platform
75 * specific alignments for venus driver
76 */
77 if (bo->format == DRM_FORMAT_NV12) {
Tanmay Shah067594b2018-11-26 10:05:18 -080078 uint32_t y_stride, uv_stride, y_scanline, uv_scanline, y_plane, uv_plane, size,
79 extra_padding;
80
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080081 y_stride = ALIGN(width, VENUS_STRIDE_ALIGN);
82 uv_stride = ALIGN(width, VENUS_STRIDE_ALIGN);
83 y_scanline = ALIGN(height, VENUS_SCANLINE_ALIGN * 2);
84 uv_scanline = ALIGN(DIV_ROUND_UP(height, 2), VENUS_SCANLINE_ALIGN);
85 y_plane = y_stride * y_scanline;
86 uv_plane = uv_stride * uv_scanline;
87
Tanmay Shah067594b2018-11-26 10:05:18 -080088 if (bo->tiling == MSM_UBWC_TILING) {
89 y_plane += get_ubwc_meta_size(width, height, 32, 8);
90 uv_plane += get_ubwc_meta_size(width >> 1, height >> 1, 16, 8);
91 extra_padding = NV12_UBWC_PADDING(y_stride);
92 } else {
93 extra_padding = NV12_LINEAR_PADDING;
94 }
95
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080096 bo->strides[0] = y_stride;
97 bo->sizes[0] = y_plane;
98 bo->offsets[1] = y_plane;
99 bo->strides[1] = uv_stride;
Tanmay Shah067594b2018-11-26 10:05:18 -0800100 size = y_plane + uv_plane + extra_padding;
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800101 bo->total_size = ALIGN(size, BUFFER_SIZE_ALIGN);
102 bo->sizes[1] = bo->total_size - bo->sizes[0];
103 } else {
104 uint32_t stride, alignw, alignh;
105
106 alignw = ALIGN(width, DEFAULT_ALIGNMENT);
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800107 /* HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned. */
108 if (bo->format == DRM_FORMAT_YVU420_ANDROID) {
109 alignh = height;
110 } else {
111 alignh = ALIGN(height, DEFAULT_ALIGNMENT);
112 }
113
114 stride = drv_stride_from_format(bo->format, alignw, 0);
115
116 /* Calculate size and assign stride, size, offset to each plane based on format */
117 drv_bo_from_format(bo, stride, alignh, bo->format);
Tanmay Shah067594b2018-11-26 10:05:18 -0800118
119 /* For all RGB UBWC formats */
120 if (bo->tiling == MSM_UBWC_TILING) {
121 bo->sizes[0] += get_ubwc_meta_size(width, height, 16, 4);
122 bo->total_size = bo->sizes[0];
123 assert(IS_ALIGNED(bo->total_size, BUFFER_SIZE_ALIGN));
124 }
125 }
126}
127
128static bool is_ubwc_fmt(uint32_t format)
129{
130 switch (format) {
131 case DRM_FORMAT_XBGR8888:
132 case DRM_FORMAT_ABGR8888:
133 case DRM_FORMAT_NV12:
134 return 1;
135 default:
136 return 0;
137 }
138}
139
140static void msm_add_ubwc_combinations(struct driver *drv, const uint32_t *formats,
141 uint32_t num_formats, struct format_metadata *metadata,
142 uint64_t use_flags)
143{
144 for (uint32_t i = 0; i < num_formats; i++) {
145 if (is_ubwc_fmt(formats[i])) {
146 struct combination combo = { .format = formats[i],
147 .metadata = *metadata,
148 .use_flags = use_flags };
149 drv_array_append(drv->combos, &combo);
150 }
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800151 }
152}
153
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530154static int msm_init(struct driver *drv)
155{
Tanmay Shah067594b2018-11-26 10:05:18 -0800156 struct format_metadata metadata;
157 uint64_t render_use_flags = BO_USE_RENDER_MASK;
158 uint64_t texture_use_flags = BO_USE_TEXTURE_MASK | BO_USE_HW_VIDEO_DECODER;
159 uint64_t sw_flags = (BO_USE_RENDERSCRIPT | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_OFTEN |
160 BO_USE_LINEAR | BO_USE_PROTECTED);
161
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530162 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Tanmay Shah067594b2018-11-26 10:05:18 -0800163 &LINEAR_METADATA, render_use_flags);
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530164
Tanmay Shah617ee712018-07-11 16:41:05 -0700165 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
Tanmay Shah067594b2018-11-26 10:05:18 -0800166 &LINEAR_METADATA, texture_use_flags);
Alexandre Courbot1805a9b2018-05-21 19:05:10 +0900167
Gurchetan Singh71bc6652018-09-17 17:42:05 -0700168 /* Android CTS tests require this. */
169 drv_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
170
Tanmay Shah067594b2018-11-26 10:05:18 -0800171 drv_modify_linear_combinations(drv);
172
173 metadata.tiling = MSM_UBWC_TILING;
174 metadata.priority = 2;
175 metadata.modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
176
177 render_use_flags &= ~sw_flags;
178 texture_use_flags &= ~sw_flags;
179
180 msm_add_ubwc_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
181 &metadata, render_use_flags);
182
183 msm_add_ubwc_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
184 &metadata, texture_use_flags);
185
186 return 0;
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530187}
188
Tanmay Shah067594b2018-11-26 10:05:18 -0800189static int msm_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
190 uint32_t format, const uint64_t modifier)
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800191{
Tanmay Shah617ee712018-07-11 16:41:05 -0700192 struct drm_msm_gem_new req;
Tanmay Shah617ee712018-07-11 16:41:05 -0700193 int ret;
194 size_t i;
195
Tanmay Shah067594b2018-11-26 10:05:18 -0800196 bo->tiling = (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) ? MSM_UBWC_TILING : 0;
197
198 msm_calculate_layout(bo);
Tanmay Shah617ee712018-07-11 16:41:05 -0700199
200 memset(&req, 0, sizeof(req));
201 req.flags = MSM_BO_WC | MSM_BO_SCANOUT;
202 req.size = bo->total_size;
203
204 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MSM_GEM_NEW, &req);
205 if (ret) {
206 drv_log("DRM_IOCTL_MSM_GEM_NEW failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700207 return -errno;
Tanmay Shah617ee712018-07-11 16:41:05 -0700208 }
209
210 /*
211 * Though we use only one plane, we need to set handle for
212 * all planes to pass kernel checks
213 */
214 for (i = 0; i < bo->num_planes; i++) {
215 bo->handles[i].u32 = req.handle;
Tanmay Shah067594b2018-11-26 10:05:18 -0800216 bo->format_modifiers[i] = modifier;
Tanmay Shah617ee712018-07-11 16:41:05 -0700217 }
218
219 return 0;
220}
221
Tanmay Shah067594b2018-11-26 10:05:18 -0800222static int msm_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
223 uint32_t format, const uint64_t *modifiers, uint32_t count)
224{
225 static const uint64_t modifier_order[] = {
226 DRM_FORMAT_MOD_QCOM_COMPRESSED,
227 DRM_FORMAT_MOD_LINEAR,
228 };
229
230 uint64_t modifier =
231 drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
232
233 return msm_bo_create_for_modifier(bo, width, height, format, modifier);
234}
235
236/* msm_bo_create will create linear buffers for now */
237static int msm_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
238 uint64_t flags)
239{
240 struct combination *combo = drv_get_combination(bo->drv, format, flags);
241
242 if (!combo) {
243 drv_log("invalid format = %d, flags = %llx combination\n", format, flags);
244 return -EINVAL;
245 }
246
247 return msm_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
248}
249
Tanmay Shah617ee712018-07-11 16:41:05 -0700250static void *msm_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
251{
252 int ret;
253 struct drm_msm_gem_info req;
254
255 memset(&req, 0, sizeof(req));
256 req.handle = bo->handles[0].u32;
257
258 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MSM_GEM_INFO, &req);
259 if (ret) {
260 drv_log("DRM_IOCLT_MSM_GEM_INFO failed with %s\n", strerror(errno));
261 return MAP_FAILED;
262 }
263 vma->length = bo->total_size;
264
265 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
266 req.offset);
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800267}
268
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530269const struct backend backend_msm = {
270 .name = "msm",
271 .init = msm_init,
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800272 .bo_create = msm_bo_create,
Tanmay Shah067594b2018-11-26 10:05:18 -0800273 .bo_create_with_modifiers = msm_bo_create_with_modifiers,
Tanmay Shah617ee712018-07-11 16:41:05 -0700274 .bo_destroy = drv_gem_bo_destroy,
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530275 .bo_import = drv_prime_bo_import,
Tanmay Shah617ee712018-07-11 16:41:05 -0700276 .bo_map = msm_bo_map,
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530277 .bo_unmap = drv_bo_munmap,
278};
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530279#endif /* DRV_MSM */