Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 1 | /* |
Daniele Castagna | 7a755de | 2016-12-16 17:32:30 -0500 | [diff] [blame] | 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | */ |
| 6 | #ifdef DRV_AMDGPU |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 7 | #include <amdgpu.h> |
| 8 | #include <amdgpu_drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 9 | #include <errno.h> |
| 10 | #include <stdio.h> |
| 11 | #include <stdlib.h> |
| 12 | #include <string.h> |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 13 | #include <sys/mman.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 14 | #include <xf86drm.h> |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 15 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 16 | #include "dri.h" |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 17 | #include "drv_priv.h" |
| 18 | #include "helpers.h" |
| 19 | #include "util.h" |
| 20 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 21 | #ifdef __ANDROID__ |
| 22 | #define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so" |
| 23 | #else |
| 24 | #define DRI_PATH "/usr/lib64/dri/radeonsi_dri.so" |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 25 | #endif |
| 26 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 27 | #define TILE_TYPE_LINEAR 0 |
| 28 | /* DRI backend decides tiling in this case. */ |
| 29 | #define TILE_TYPE_DRI 1 |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 30 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 31 | struct amdgpu_priv { |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 32 | struct dri_driver dri; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 33 | int drm_version; |
| 34 | }; |
| 35 | |
Gurchetan Singh | 767c538 | 2018-05-05 00:42:12 +0000 | [diff] [blame^] | 36 | const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, |
| 37 | DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888, |
| 38 | DRM_FORMAT_XRGB8888 }; |
Gurchetan Singh | 179687e | 2016-10-28 10:07:35 -0700 | [diff] [blame] | 39 | |
Shirish S | 8317bc0 | 2017-10-13 09:54:03 +0530 | [diff] [blame] | 40 | const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21, |
Deepak Sharma | adc70fa | 2018-02-20 14:58:26 -0800 | [diff] [blame] | 41 | DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID }; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 42 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 43 | static int amdgpu_init(struct driver *drv) |
| 44 | { |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 45 | struct amdgpu_priv *priv; |
| 46 | drmVersionPtr drm_version; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 47 | struct format_metadata metadata; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 48 | uint64_t use_flags = BO_USE_RENDER_MASK; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 49 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 50 | priv = calloc(1, sizeof(struct amdgpu_priv)); |
| 51 | if (!priv) |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 52 | return -ENOMEM; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 53 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 54 | drm_version = drmGetVersion(drv_get_fd(drv)); |
| 55 | if (!drm_version) { |
| 56 | free(priv); |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 57 | return -ENODEV; |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | priv->drm_version = drm_version->version_minor; |
| 61 | drmFreeVersion(drm_version); |
| 62 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 63 | drv->priv = priv; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 64 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 65 | if (dri_init(drv, DRI_PATH, "radeonsi")) { |
| 66 | free(priv); |
| 67 | drv->priv = NULL; |
| 68 | return -ENODEV; |
| 69 | } |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 70 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 71 | metadata.tiling = TILE_TYPE_LINEAR; |
| 72 | metadata.priority = 1; |
Kristian H. Kristensen | bc8c593 | 2017-10-24 18:36:32 -0700 | [diff] [blame] | 73 | metadata.modifier = DRM_FORMAT_MOD_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 74 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 75 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 76 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 77 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 78 | drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats), |
| 79 | &metadata, BO_USE_TEXTURE_MASK); |
| 80 | |
| 81 | /* Linear formats supported by display. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 82 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 83 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 84 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 85 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 86 | /* YUV formats for camera and display. */ |
| 87 | drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, |
| 88 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 89 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 90 | drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 91 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 92 | /* |
| 93 | * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots |
| 94 | * from camera. |
| 95 | */ |
| 96 | drv_modify_combination(drv, DRM_FORMAT_R8, &metadata, |
| 97 | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE); |
| 98 | |
| 99 | /* |
| 100 | * The following formats will be allocated by the DRI backend and may be potentially tiled. |
| 101 | * Since format modifier support hasn't been implemented fully yet, it's not |
| 102 | * possible to enumerate the different types of buffers (like i915 can). |
| 103 | */ |
| 104 | use_flags &= ~BO_USE_RENDERSCRIPT; |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 105 | use_flags &= ~BO_USE_SW_WRITE_OFTEN; |
| 106 | use_flags &= ~BO_USE_SW_READ_OFTEN; |
| 107 | use_flags &= ~BO_USE_LINEAR; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 108 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 109 | metadata.tiling = TILE_TYPE_DRI; |
| 110 | metadata.priority = 2; |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 111 | |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 112 | drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats), |
| 113 | &metadata, use_flags); |
Gurchetan Singh | 6b41fb5 | 2017-03-01 20:14:39 -0800 | [diff] [blame] | 114 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 115 | /* Potentially tiled formats supported by display. */ |
| 116 | drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
| 117 | drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT); |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 118 | drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT); |
Gurchetan Singh | d300145 | 2017-11-03 17:18:36 -0700 | [diff] [blame] | 119 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static void amdgpu_close(struct driver *drv) |
| 123 | { |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 124 | dri_close(drv); |
| 125 | free(drv->priv); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 126 | drv->priv = NULL; |
| 127 | } |
| 128 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 129 | static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format, |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 130 | uint64_t use_flags) |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 131 | { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 132 | int ret; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 133 | uint32_t plane, stride; |
| 134 | struct combination *combo; |
| 135 | union drm_amdgpu_gem_create gem_create; |
| 136 | struct amdgpu_priv *priv = bo->drv->priv; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 137 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 138 | combo = drv_get_combination(bo->drv, format, use_flags); |
| 139 | if (!combo) |
| 140 | return -EINVAL; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 141 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 142 | if (combo->metadata.tiling == TILE_TYPE_DRI) |
| 143 | return dri_bo_create(bo, width, height, format, use_flags); |
| 144 | |
| 145 | stride = drv_stride_from_format(format, width, 0); |
| 146 | if (format == DRM_FORMAT_YVU420_ANDROID) |
| 147 | stride = ALIGN(stride, 128); |
| 148 | else |
| 149 | stride = ALIGN(stride, 64); |
| 150 | |
| 151 | drv_bo_from_format(bo, stride, height, format); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 152 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 153 | memset(&gem_create, 0, sizeof(gem_create)); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 154 | gem_create.in.bo_size = bo->total_size; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 155 | gem_create.in.alignment = 256; |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 156 | gem_create.in.domain_flags = 0; |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 157 | |
Dominik Behr | fa17cdd | 2017-11-30 12:23:06 -0800 | [diff] [blame] | 158 | if (use_flags & (BO_USE_LINEAR | BO_USE_SW)) |
| 159 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; |
| 160 | |
| 161 | if (use_flags & (BO_USE_SCANOUT | BO_USE_CURSOR)) { |
| 162 | /* TODO(dbehr) do not use VRAM after we enable display VM */ |
| 163 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM; |
| 164 | } else { |
| 165 | gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT; |
| 166 | if (!(use_flags & BO_USE_SW_READ_OFTEN)) |
| 167 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; |
| 168 | } |
| 169 | |
Bas Nieuwenhuizen | 3cf8c92 | 2018-03-23 17:21:37 +0100 | [diff] [blame] | 170 | /* If drm_version >= 21 everything exposes explicit synchronization primitives |
| 171 | and chromeos/arc++ will use them. Disable implicit synchronization. */ |
| 172 | if (priv->drm_version >= 21) { |
| 173 | gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC; |
| 174 | } |
| 175 | |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 176 | /* Allocate the buffer with the preferred heap. */ |
Gurchetan Singh | 1b1d56a | 2017-03-10 16:25:23 -0800 | [diff] [blame] | 177 | ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create, |
| 178 | sizeof(gem_create)); |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 179 | if (ret < 0) |
| 180 | return ret; |
| 181 | |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 182 | for (plane = 0; plane < bo->num_planes; plane++) |
| 183 | bo->handles[plane].u32 = gem_create.out.handle; |
| 184 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 185 | return 0; |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 186 | } |
| 187 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 188 | static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data) |
| 189 | { |
| 190 | struct combination *combo; |
| 191 | combo = drv_get_combination(bo->drv, data->format, data->use_flags); |
| 192 | if (!combo) |
| 193 | return -EINVAL; |
| 194 | |
| 195 | if (combo->metadata.tiling == TILE_TYPE_DRI) |
| 196 | return dri_bo_import(bo, data); |
| 197 | else |
| 198 | return drv_prime_bo_import(bo, data); |
| 199 | } |
| 200 | |
| 201 | static int amdgpu_destroy_bo(struct bo *bo) |
| 202 | { |
| 203 | if (bo->priv) |
| 204 | return dri_bo_destroy(bo); |
| 205 | else |
| 206 | return drv_gem_bo_destroy(bo); |
| 207 | } |
| 208 | |
| 209 | static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags) |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 210 | { |
| 211 | int ret; |
| 212 | union drm_amdgpu_gem_mmap gem_map; |
| 213 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 214 | if (bo->priv) |
| 215 | return dri_bo_map(bo, vma, plane, map_flags); |
| 216 | |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 217 | memset(&gem_map, 0, sizeof(gem_map)); |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 218 | gem_map.in.handle = bo->handles[plane].u32; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 219 | |
| 220 | ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map); |
| 221 | if (ret) { |
Alistair Strachan | 0cfaaa5 | 2018-03-19 14:03:23 -0700 | [diff] [blame] | 222 | drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n"); |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 223 | return MAP_FAILED; |
| 224 | } |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 225 | |
Gurchetan Singh | ee43c30 | 2017-11-14 18:20:27 -0800 | [diff] [blame] | 226 | vma->length = bo->total_size; |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 227 | |
Gurchetan Singh | cfb8876 | 2017-09-28 17:14:50 -0700 | [diff] [blame] | 228 | return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd, |
| 229 | gem_map.out.addr_ptr); |
Pratik Vishwakarma | bc1b535 | 2016-12-12 14:22:10 +0530 | [diff] [blame] | 230 | } |
| 231 | |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 232 | static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma) |
| 233 | { |
| 234 | if (bo->priv) |
| 235 | return dri_bo_unmap(bo, vma); |
| 236 | else |
| 237 | return munmap(vma->addr, vma->length); |
| 238 | } |
| 239 | |
Gurchetan Singh | a1892b2 | 2017-09-28 16:40:52 -0700 | [diff] [blame] | 240 | static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags) |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 241 | { |
| 242 | switch (format) { |
Ricky Liang | 0b78e07 | 2017-11-10 09:17:17 +0800 | [diff] [blame] | 243 | case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED: |
| 244 | /* Camera subsystem requires NV12. */ |
| 245 | if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)) |
| 246 | return DRM_FORMAT_NV12; |
| 247 | /*HACK: See b/28671744 */ |
| 248 | return DRM_FORMAT_XBGR8888; |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 249 | case DRM_FORMAT_FLEX_YCbCr_420_888: |
| 250 | return DRM_FORMAT_NV12; |
| 251 | default: |
| 252 | return format; |
| 253 | } |
| 254 | } |
| 255 | |
Gurchetan Singh | 3e9d383 | 2017-10-31 10:36:25 -0700 | [diff] [blame] | 256 | const struct backend backend_amdgpu = { |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 257 | .name = "amdgpu", |
| 258 | .init = amdgpu_init, |
| 259 | .close = amdgpu_close, |
Satyajit | cdcebd8 | 2018-01-12 14:49:05 +0530 | [diff] [blame] | 260 | .bo_create = amdgpu_create_bo, |
| 261 | .bo_destroy = amdgpu_destroy_bo, |
| 262 | .bo_import = amdgpu_import_bo, |
| 263 | .bo_map = amdgpu_map_bo, |
| 264 | .bo_unmap = amdgpu_unmap_bo, |
Shirish S | df423df | 2017-04-18 16:21:59 +0530 | [diff] [blame] | 265 | .resolve_format = amdgpu_resolve_format, |
Akshu Agrawal | 0337d9b | 2016-07-28 15:35:45 +0530 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | #endif |