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Rajesh Yadav7f79cb52018-01-22 18:29:06 +05301/*
2 * Copyright 2018 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7#ifdef DRV_MSM
8
Tanmay Shah067594b2018-11-26 10:05:18 -08009#include <assert.h>
10#include <drm_fourcc.h>
Tanmay Shah617ee712018-07-11 16:41:05 -070011#include <errno.h>
Stephen Boyd5ff0cfd2019-04-09 11:03:00 -070012#include <inttypes.h>
Tanmay Shah617ee712018-07-11 16:41:05 -070013#include <msm_drm.h>
Tanmay Shah067594b2018-11-26 10:05:18 -080014#include <stdbool.h>
Tanmay Shah617ee712018-07-11 16:41:05 -070015#include <stdio.h>
16#include <string.h>
17#include <sys/mman.h>
18#include <xf86drm.h>
19
Rajesh Yadav7f79cb52018-01-22 18:29:06 +053020#include "drv_priv.h"
21#include "helpers.h"
22#include "util.h"
23
Tanmay Shah067594b2018-11-26 10:05:18 -080024/* Alignment values are based on SDM845 Gfx IP */
Tanmay Shah617ee712018-07-11 16:41:05 -070025#define DEFAULT_ALIGNMENT 64
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080026#define BUFFER_SIZE_ALIGN 4096
27
28#define VENUS_STRIDE_ALIGN 128
29#define VENUS_SCANLINE_ALIGN 16
30#define NV12_LINEAR_PADDING (12 * 1024)
Tanmay Shah067594b2018-11-26 10:05:18 -080031#define NV12_UBWC_PADDING(y_stride) (MAX(16 * 1024, y_stride * 48))
32#define MACROTILE_WIDTH_ALIGN 64
33#define MACROTILE_HEIGHT_ALIGN 16
34#define PLANE_SIZE_ALIGN 4096
35
36#define MSM_UBWC_TILING 1
Stéphane Marchesin23e006a2018-02-28 16:37:46 -080037
Gurchetan Singhb131c9d2018-08-28 14:17:05 -070038static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
Gurchetan Singh71bc6652018-09-17 17:42:05 -070039 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
40 DRM_FORMAT_XRGB8888 };
Rajesh Yadav7f79cb52018-01-22 18:29:06 +053041
Tanmay Shah617ee712018-07-11 16:41:05 -070042static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_R8,
43 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Alexandre Courbot1805a9b2018-05-21 19:05:10 +090044
Tanmay Shah067594b2018-11-26 10:05:18 -080045/*
46 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
47 * Pixel data pitch/stride is aligned with macrotile width.
48 * Pixel data height is aligned with macrotile height.
49 * Entire pixel data buffer is aligned with 4k(bytes).
50 */
51static uint32_t get_ubwc_meta_size(uint32_t width, uint32_t height, uint32_t tile_width,
52 uint32_t tile_height)
53{
54 uint32_t macrotile_width, macrotile_height;
55
56 macrotile_width = DIV_ROUND_UP(width, tile_width);
57 macrotile_height = DIV_ROUND_UP(height, tile_height);
58
59 // Align meta buffer width to 64 blocks
60 macrotile_width = ALIGN(macrotile_width, MACROTILE_WIDTH_ALIGN);
61
62 // Align meta buffer height to 16 blocks
63 macrotile_height = ALIGN(macrotile_height, MACROTILE_HEIGHT_ALIGN);
64
65 return ALIGN(macrotile_width * macrotile_height, PLANE_SIZE_ALIGN);
66}
67
68static void msm_calculate_layout(struct bo *bo)
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080069{
70 uint32_t width, height;
71
72 width = bo->width;
73 height = bo->height;
74
75 /* NV12 format requires extra padding with platform
76 * specific alignments for venus driver
77 */
78 if (bo->format == DRM_FORMAT_NV12) {
Tanmay Shah067594b2018-11-26 10:05:18 -080079 uint32_t y_stride, uv_stride, y_scanline, uv_scanline, y_plane, uv_plane, size,
80 extra_padding;
81
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080082 y_stride = ALIGN(width, VENUS_STRIDE_ALIGN);
83 uv_stride = ALIGN(width, VENUS_STRIDE_ALIGN);
84 y_scanline = ALIGN(height, VENUS_SCANLINE_ALIGN * 2);
85 uv_scanline = ALIGN(DIV_ROUND_UP(height, 2), VENUS_SCANLINE_ALIGN);
86 y_plane = y_stride * y_scanline;
87 uv_plane = uv_stride * uv_scanline;
88
Tanmay Shah067594b2018-11-26 10:05:18 -080089 if (bo->tiling == MSM_UBWC_TILING) {
90 y_plane += get_ubwc_meta_size(width, height, 32, 8);
91 uv_plane += get_ubwc_meta_size(width >> 1, height >> 1, 16, 8);
92 extra_padding = NV12_UBWC_PADDING(y_stride);
93 } else {
94 extra_padding = NV12_LINEAR_PADDING;
95 }
96
Tanmay Shahc65bd8c2018-11-21 09:14:14 -080097 bo->strides[0] = y_stride;
98 bo->sizes[0] = y_plane;
99 bo->offsets[1] = y_plane;
100 bo->strides[1] = uv_stride;
Tanmay Shah067594b2018-11-26 10:05:18 -0800101 size = y_plane + uv_plane + extra_padding;
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800102 bo->total_size = ALIGN(size, BUFFER_SIZE_ALIGN);
103 bo->sizes[1] = bo->total_size - bo->sizes[0];
104 } else {
105 uint32_t stride, alignw, alignh;
106
107 alignw = ALIGN(width, DEFAULT_ALIGNMENT);
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800108 /* HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned. */
109 if (bo->format == DRM_FORMAT_YVU420_ANDROID) {
110 alignh = height;
111 } else {
112 alignh = ALIGN(height, DEFAULT_ALIGNMENT);
113 }
114
115 stride = drv_stride_from_format(bo->format, alignw, 0);
116
117 /* Calculate size and assign stride, size, offset to each plane based on format */
118 drv_bo_from_format(bo, stride, alignh, bo->format);
Tanmay Shah067594b2018-11-26 10:05:18 -0800119
120 /* For all RGB UBWC formats */
121 if (bo->tiling == MSM_UBWC_TILING) {
122 bo->sizes[0] += get_ubwc_meta_size(width, height, 16, 4);
123 bo->total_size = bo->sizes[0];
124 assert(IS_ALIGNED(bo->total_size, BUFFER_SIZE_ALIGN));
125 }
126 }
127}
128
129static bool is_ubwc_fmt(uint32_t format)
130{
131 switch (format) {
132 case DRM_FORMAT_XBGR8888:
133 case DRM_FORMAT_ABGR8888:
134 case DRM_FORMAT_NV12:
135 return 1;
136 default:
137 return 0;
138 }
139}
140
141static void msm_add_ubwc_combinations(struct driver *drv, const uint32_t *formats,
142 uint32_t num_formats, struct format_metadata *metadata,
143 uint64_t use_flags)
144{
145 for (uint32_t i = 0; i < num_formats; i++) {
146 if (is_ubwc_fmt(formats[i])) {
147 struct combination combo = { .format = formats[i],
148 .metadata = *metadata,
149 .use_flags = use_flags };
150 drv_array_append(drv->combos, &combo);
151 }
Tanmay Shahc65bd8c2018-11-21 09:14:14 -0800152 }
153}
154
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530155static int msm_init(struct driver *drv)
156{
Tanmay Shah067594b2018-11-26 10:05:18 -0800157 struct format_metadata metadata;
158 uint64_t render_use_flags = BO_USE_RENDER_MASK;
159 uint64_t texture_use_flags = BO_USE_TEXTURE_MASK | BO_USE_HW_VIDEO_DECODER;
160 uint64_t sw_flags = (BO_USE_RENDERSCRIPT | BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_OFTEN |
161 BO_USE_LINEAR | BO_USE_PROTECTED);
162
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530163 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Tanmay Shah067594b2018-11-26 10:05:18 -0800164 &LINEAR_METADATA, render_use_flags);
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530165
Tanmay Shah617ee712018-07-11 16:41:05 -0700166 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
Tanmay Shah067594b2018-11-26 10:05:18 -0800167 &LINEAR_METADATA, texture_use_flags);
Alexandre Courbot1805a9b2018-05-21 19:05:10 +0900168
Hirokazu Honda3b8d4d02019-07-31 16:35:52 +0900169 /*
170 * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
171 * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
172 */
173 drv_modify_combination(drv, DRM_FORMAT_YVU420, &LINEAR_METADATA, BO_USE_HW_VIDEO_ENCODER);
174 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_HW_VIDEO_ENCODER);
175
Gurchetan Singh71bc6652018-09-17 17:42:05 -0700176 /* Android CTS tests require this. */
177 drv_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
178
Tanmay Shah067594b2018-11-26 10:05:18 -0800179 drv_modify_linear_combinations(drv);
180
181 metadata.tiling = MSM_UBWC_TILING;
182 metadata.priority = 2;
183 metadata.modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
184
185 render_use_flags &= ~sw_flags;
186 texture_use_flags &= ~sw_flags;
187
188 msm_add_ubwc_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
189 &metadata, render_use_flags);
190
191 msm_add_ubwc_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
192 &metadata, texture_use_flags);
193
194 return 0;
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530195}
196
Tanmay Shah067594b2018-11-26 10:05:18 -0800197static int msm_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
198 uint32_t format, const uint64_t modifier)
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800199{
Tanmay Shah617ee712018-07-11 16:41:05 -0700200 struct drm_msm_gem_new req;
Tanmay Shah617ee712018-07-11 16:41:05 -0700201 int ret;
202 size_t i;
203
Tanmay Shah067594b2018-11-26 10:05:18 -0800204 bo->tiling = (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) ? MSM_UBWC_TILING : 0;
205
206 msm_calculate_layout(bo);
Tanmay Shah617ee712018-07-11 16:41:05 -0700207
208 memset(&req, 0, sizeof(req));
209 req.flags = MSM_BO_WC | MSM_BO_SCANOUT;
210 req.size = bo->total_size;
211
212 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MSM_GEM_NEW, &req);
213 if (ret) {
214 drv_log("DRM_IOCTL_MSM_GEM_NEW failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700215 return -errno;
Tanmay Shah617ee712018-07-11 16:41:05 -0700216 }
217
218 /*
219 * Though we use only one plane, we need to set handle for
220 * all planes to pass kernel checks
221 */
222 for (i = 0; i < bo->num_planes; i++) {
223 bo->handles[i].u32 = req.handle;
Tanmay Shah067594b2018-11-26 10:05:18 -0800224 bo->format_modifiers[i] = modifier;
Tanmay Shah617ee712018-07-11 16:41:05 -0700225 }
226
227 return 0;
228}
229
Tanmay Shah067594b2018-11-26 10:05:18 -0800230static int msm_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
231 uint32_t format, const uint64_t *modifiers, uint32_t count)
232{
233 static const uint64_t modifier_order[] = {
234 DRM_FORMAT_MOD_QCOM_COMPRESSED,
235 DRM_FORMAT_MOD_LINEAR,
236 };
237
238 uint64_t modifier =
239 drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
240
241 return msm_bo_create_for_modifier(bo, width, height, format, modifier);
242}
243
244/* msm_bo_create will create linear buffers for now */
245static int msm_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
246 uint64_t flags)
247{
248 struct combination *combo = drv_get_combination(bo->drv, format, flags);
249
250 if (!combo) {
Stephen Boyd5ff0cfd2019-04-09 11:03:00 -0700251 drv_log("invalid format = %d, flags = %" PRIx64 " combination\n", format, flags);
Tanmay Shah067594b2018-11-26 10:05:18 -0800252 return -EINVAL;
253 }
254
255 return msm_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
256}
257
Tanmay Shah617ee712018-07-11 16:41:05 -0700258static void *msm_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
259{
260 int ret;
261 struct drm_msm_gem_info req;
262
263 memset(&req, 0, sizeof(req));
264 req.handle = bo->handles[0].u32;
265
266 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MSM_GEM_INFO, &req);
267 if (ret) {
268 drv_log("DRM_IOCLT_MSM_GEM_INFO failed with %s\n", strerror(errno));
269 return MAP_FAILED;
270 }
271 vma->length = bo->total_size;
272
273 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
274 req.offset);
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800275}
276
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530277const struct backend backend_msm = {
278 .name = "msm",
279 .init = msm_init,
Stéphane Marchesin23e006a2018-02-28 16:37:46 -0800280 .bo_create = msm_bo_create,
Tanmay Shah067594b2018-11-26 10:05:18 -0800281 .bo_create_with_modifiers = msm_bo_create_with_modifiers,
Tanmay Shah617ee712018-07-11 16:41:05 -0700282 .bo_destroy = drv_gem_bo_destroy,
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530283 .bo_import = drv_prime_bo_import,
Tanmay Shah617ee712018-07-11 16:41:05 -0700284 .bo_map = msm_bo_map,
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530285 .bo_unmap = drv_bo_munmap,
286};
Rajesh Yadav7f79cb52018-01-22 18:29:06 +0530287#endif /* DRV_MSM */