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H. Peter Anvin9e6747c2009-06-28 17:13:04 -07001/* ----------------------------------------------------------------------- *
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002 *
H. Peter Anvind24dd5f2016-02-08 10:32:13 -08003 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
H. Peter Anvin9e6747c2009-06-28 17:13:04 -07004 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00006 *
H. Peter Anvin9e6747c2009-06-28 17:13:04 -07007 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
Cyrill Gorcunov1de95002009-11-06 00:08:38 +030017 *
H. Peter Anvin9e6747c2009-06-28 17:13:04 -070018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34/*
35 * assemble.c code generation for the Netwide Assembler
H. Peter Anvinea6e34d2002-04-30 20:51:32 +000036 *
Cyrill Gorcunov5d488a32014-08-25 17:50:53 +040037 * Bytecode specification
38 * ----------------------
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -070039 *
Cyrill Gorcunov5d488a32014-08-25 17:50:53 +040040 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -070082 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 000 0mm
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
Cyrill Gorcunov5d488a32014-08-25 17:50:53 +0400106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
H. Peter Anvind85d2502008-05-04 17:53:31 -0700111 *
H. Peter Anvina04019c2009-05-03 21:42:34 -0700112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
H. Peter Anvin421059c2010-08-16 14:56:33 -0700114 * 00 wwl lpp
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -0700115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
H. Peter Anvin421059c2010-08-16 14:56:33 -0700118 *
H. Peter Anvin978c2172010-08-16 13:48:43 -0700119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
H. Peter Anvinbd420c72008-05-22 11:24:35 -0700123 *
H. Peter Anvina04019c2009-05-03 21:42:34 -0700124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
H. Peter Anvind85d2502008-05-04 17:53:31 -0700125 *
Cyrill Gorcunov5d488a32014-08-25 17:50:53 +0400126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
Cyrill Gorcunov8a5d3e62014-08-25 20:04:30 +0400163 * \360 np no SSE prefix (== \364\331)
Cyrill Gorcunov5d488a32014-08-25 17:50:53 +0400164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000176 */
177
H. Peter Anvinfe501952007-10-02 21:53:51 -0700178#include "compiler.h"
179
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000180#include <stdio.h>
181#include <string.h>
H. Peter Anvin89a2ac02013-11-26 18:23:20 -0800182#include <stdlib.h>
Keith Kaniosb7a89542007-04-12 02:40:54 +0000183#include <inttypes.h>
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000184
185#include "nasm.h"
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000186#include "nasmlib.h"
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000187#include "assemble.h"
188#include "insns.h"
H. Peter Anvina4835d42008-05-20 14:21:29 -0700189#include "tables.h"
Jin Kyu Song5f3bfee2013-11-20 15:32:52 -0800190#include "disp8.h"
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000191
H. Peter Anvin65289e82009-07-25 17:25:11 -0700192enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
Jin Kyu Song25c22122013-10-30 03:12:45 -0700200 MERR_BRNUMMISMATCH,
H. Peter Anvin65289e82009-07-25 17:25:11 -0700201 MERR_BADCPU,
202 MERR_BADMODE,
H. Peter Anvinfb3f4e62012-02-25 22:22:07 -0800203 MERR_BADHLE,
Jin Kyu Song66c61922013-08-26 20:28:43 -0700204 MERR_ENCMISMATCH,
Jin Kyu Song03041092013-10-15 19:38:51 -0700205 MERR_BADBND,
Jin Kyu Songb287ff02013-12-04 20:05:55 -0800206 MERR_BADREPNE,
H. Peter Anvin65289e82009-07-25 17:25:11 -0700207 /*
208 * Matching success; the conditional ones first
209 */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
H. Peter Anvin65289e82009-07-25 17:25:11 -0700212};
213
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000214typedef struct {
H. Peter Anvin3089f7e2011-06-22 18:19:28 -0700215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -0700220 int8_t disp8; /* compressed displacement for EVEX */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000221} ea;
222
Cyrill Gorcunov10734c72011-08-29 00:07:17 +0400223#define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226#define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
Cyrill Gorcunov08359152013-11-09 22:16:11 +0400229static iflag_t cpu; /* cpu level received from nasm.c */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000230static efunc errfunc;
231static struct ofmt *outfmt;
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000232static ListGen *list;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000233
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800234static int64_t calcsize(int32_t, int64_t, int, insn *,
235 const struct itemplate *);
H. Peter Anvin833caea2008-10-04 19:02:30 -0700236static void gencode(int32_t segment, int64_t offset, int bits,
237 insn * ins, const struct itemplate *temp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400238 int64_t insn_end);
H. Peter Anvin23595f52009-07-25 17:44:25 -0700239static enum match_result find_match(const struct itemplate **tempp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400240 insn *instruction,
241 int32_t segment, int64_t offset, int bits);
H. Peter Anvin65289e82009-07-25 17:25:11 -0700242static enum match_result matches(const struct itemplate *, insn *, int bits);
H. Peter Anvinf8563f72009-10-13 12:28:14 -0700243static opflags_t regflag(const operand *);
H. Peter Anvin3df97a72007-05-30 03:25:21 +0000244static int32_t regval(const operand *);
H. Peter Anvinf8563f72009-10-13 12:28:14 -0700245static int rexflags(int, opflags_t, int);
H. Peter Anvin3df97a72007-05-30 03:25:21 +0000246static int op_rexflags(const operand *, int);
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -0700247static int op_evexflags(const operand *, int, uint8_t);
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -0700248static void add_asp(insn *, int);
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000249
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -0700250static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
H. Peter Anvin3089f7e2011-06-22 18:19:28 -0700251
Cyrill Gorcunov18914e62011-11-12 11:41:51 +0400252static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
H. Peter Anvin0db11e22007-04-17 20:23:11 +0000253{
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700254 return ins->prefixes[pos] == prefix;
255}
256
257static void assert_no_prefix(insn * ins, enum prefix_pos pos)
258{
259 if (ins->prefixes[pos])
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400260 errfunc(ERR_NONFATAL, "invalid %s prefix",
261 prefix_name(ins->prefixes[pos]));
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700262}
263
264static const char *size_name(int size)
265{
266 switch (size) {
267 case 1:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400268 return "byte";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700269 case 2:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400270 return "word";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700271 case 4:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400272 return "dword";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700273 case 8:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400274 return "qword";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700275 case 10:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400276 return "tword";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700277 case 16:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400278 return "oword";
H. Peter Anvindfb91802008-05-20 11:43:53 -0700279 case 32:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400280 return "yword";
Jin Kyu Songd4760c12013-08-21 19:29:11 -0700281 case 64:
282 return "zword";
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700283 default:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400284 return "???";
H. Peter Anvin0db11e22007-04-17 20:23:11 +0000285 }
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -0700286}
287
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +0400288static void warn_overflow(int pass, int size)
289{
290 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
291 "%s data exceeds bounds", size_name(size));
292}
293
294static void warn_overflow_const(int64_t data, int size)
295{
296 if (overflow_general(data, size))
297 warn_overflow(ERR_PASS1, size);
298}
299
300static void warn_overflow_opd(const struct operand *o, int size)
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -0700301{
Victor van den Elzen0d268fb2010-01-24 21:24:57 +0100302 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +0400303 if (overflow_general(o->offset, size))
304 warn_overflow(ERR_PASS2, size);
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700305 }
306}
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +0400307
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000308/*
309 * This routine wrappers the real output format's output routine,
310 * in order to pass a copy of the data off to the listing file
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800311 * generator at the same time, flatten unnecessary relocations,
312 * and verify backend compatibility.
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000313 */
Charles Crayne1f8bc4c2007-11-06 18:27:23 -0800314static void out(int64_t offset, int32_t segto, const void *data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800315 enum out_type type, uint64_t size,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400316 int32_t segment, int32_t wrt)
H. Peter Anvineba20a72002-04-30 20:53:55 +0000317{
Keith Kaniosb7a89542007-04-12 02:40:54 +0000318 static int32_t lineno = 0; /* static!!! */
Keith Kaniosa6dfa782007-04-13 16:47:53 +0000319 static char *lnfname = NULL;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800320 uint8_t p[8];
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800321 const int asize = abs((int)size); /* True address size */
H. Peter Anvin33814132016-02-11 20:40:07 -0800322 const int amax = outfmt->maxbits >> 3; /* Maximum address size in bytes */
H. Peter Anvineba20a72002-04-30 20:53:55 +0000323
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800324 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400325 /*
326 * This is a non-relocated address, and we're going to
327 * convert it into RAWDATA format.
328 */
329 uint8_t *q = p;
H. Peter Anvin89a2ac02013-11-26 18:23:20 -0800330
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800331 if (asize > 8) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400332 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
333 return;
334 }
H. Peter Anvind85d2502008-05-04 17:53:31 -0700335
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800336 WRITEADDR(q, *(int64_t *)data, asize);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400337 data = p;
338 type = OUT_RAWDATA;
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000339 }
340
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800341 list->output(offset, data, type, size);
342
Frank Kotlerabebb082003-09-06 04:45:37 +0000343 /*
344 * this call to src_get determines when we call the
345 * debug-format-specific "linenum" function
346 * it updates lineno and lnfname to the current values
347 * returning 0 if "same as last time", -2 if lnfname
348 * changed, and the amount by which lineno changed,
349 * if it did. thus, these variables must be static
350 */
351
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400352 if (src_get(&lineno, &lnfname))
H. Peter Anvine2c80182005-01-15 22:15:51 +0000353 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
H. Peter Anvineba20a72002-04-30 20:53:55 +0000354
H. Peter Anvin33814132016-02-11 20:40:07 -0800355 if (type == OUT_ADDRESS && asize > amax) {
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800356 if (asize < 0) {
357 errfunc(ERR_NONFATAL,
358 "%d-bit signed relocation unsupported by output format %s\n",
H. Peter Anvin33814132016-02-11 20:40:07 -0800359 asize << 3, outfmt->shortname);
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800360 } else {
361 errfunc(ERR_WARNING | ERR_WARN_ZEXTRELOC,
H. Peter Anvinecc9e0e2016-02-11 20:29:34 -0800362 "%d-bit unsigned relocation zero-extended from %d bits\n",
H. Peter Anvin33814132016-02-11 20:40:07 -0800363 asize << 4, outfmt->maxbits);
H. Peter Anvind24dd5f2016-02-08 10:32:13 -0800364 outfmt->output(segto, data, type, amax, segment, wrt);
365 size -= amax;
366 }
367 data = zero_buffer;
368 type = OUT_RAWDATA;
369 }
370
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800371 outfmt->output(segto, data, type, size, segment, wrt);
H. Peter Anvin6768eb72002-04-30 20:52:26 +0000372}
373
H. Peter Anvin89a2ac02013-11-26 18:23:20 -0800374static void out_imm8(int64_t offset, int32_t segment,
375 struct operand *opx, int asize)
Ben Rudiak-Gould4e8396b2013-03-01 10:28:32 +0400376{
377 if (opx->segment != NO_SEG) {
378 uint64_t data = opx->offset;
H. Peter Anvin89a2ac02013-11-26 18:23:20 -0800379 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
Ben Rudiak-Gould4e8396b2013-03-01 10:28:32 +0400380 } else {
381 uint8_t byte = opx->offset;
382 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
383 }
384}
385
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700386static bool jmp_match(int32_t segment, int64_t offset, int bits,
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800387 insn * ins, const struct itemplate *temp)
H. Peter Anvine2c80182005-01-15 22:15:51 +0000388{
Charles Crayne5fbbc8c2007-11-07 19:03:46 -0800389 int64_t isize;
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800390 const uint8_t *code = temp->code;
Keith Kaniosb7a89542007-04-12 02:40:54 +0000391 uint8_t c = code[0];
Jin Kyu Song305f3ce2013-11-21 19:40:42 -0800392 bool is_byte;
H. Peter Anvinaf535c12002-04-30 20:59:21 +0000393
H. Peter Anvin755f5212012-02-25 11:41:34 -0800394 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700395 return false;
396 if (!optimizing)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400397 return false;
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700398 if (optimizing < 0 && c == 0371)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400399 return false;
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700400
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800401 isize = calcsize(segment, offset, bits, ins, temp);
Victor van den Elzenccafc3c2009-02-23 04:35:00 +0100402
Victor van den Elzen154e5922009-02-25 17:32:00 +0100403 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
Victor van den Elzenccafc3c2009-02-23 04:35:00 +0100404 /* Be optimistic in pass 1 */
405 return true;
406
H. Peter Anvine2c80182005-01-15 22:15:51 +0000407 if (ins->oprs[0].segment != segment)
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700408 return false;
H. Peter Anvinaf535c12002-04-30 20:59:21 +0000409
H. Peter Anvin2d5baaa2008-09-30 16:31:06 -0700410 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
Jin Kyu Song305f3ce2013-11-21 19:40:42 -0800411 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
412
413 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
414 /* jmp short (opcode eb) cannot be used with bnd prefix. */
415 ins->prefixes[PPS_REP] = P_none;
Jin Kyu Songbb8cf3f2013-11-29 00:38:29 -0800416 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
417 "jmp short does not init bnd regs - bnd prefix dropped.");
Jin Kyu Song305f3ce2013-11-21 19:40:42 -0800418 }
419
420 return is_byte;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000421}
H. Peter Anvinaf535c12002-04-30 20:59:21 +0000422
Cyrill Gorcunov08359152013-11-09 22:16:11 +0400423int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400424 insn * instruction, struct ofmt *output, efunc error,
425 ListGen * listgen)
H. Peter Anvineba20a72002-04-30 20:53:55 +0000426{
H. Peter Anvin3360d792007-09-11 04:16:57 +0000427 const struct itemplate *temp;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000428 int j;
H. Peter Anvin23595f52009-07-25 17:44:25 -0700429 enum match_result m;
Charles Crayne1f8bc4c2007-11-06 18:27:23 -0800430 int64_t insn_end;
Keith Kaniosb7a89542007-04-12 02:40:54 +0000431 int32_t itimes;
Charles Crayne1f8bc4c2007-11-06 18:27:23 -0800432 int64_t start = offset;
Cyrill Gorcunovbafd8772009-10-31 20:02:14 +0300433 int64_t wsize; /* size for DB etc. */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000434
H. Peter Anvine2c80182005-01-15 22:15:51 +0000435 errfunc = error; /* to pass to other functions */
H. Peter Anvinaf535c12002-04-30 20:59:21 +0000436 cpu = cp;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000437 outfmt = output; /* likewise */
438 list = listgen; /* and again */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000439
Cyrill Gorcunovbafd8772009-10-31 20:02:14 +0300440 wsize = idata_bytes(instruction->opcode);
441 if (wsize == -1)
H. Peter Anvine2c80182005-01-15 22:15:51 +0000442 return 0;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000443
H. Peter Anvineba20a72002-04-30 20:53:55 +0000444 if (wsize) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000445 extop *e;
Keith Kaniosb7a89542007-04-12 02:40:54 +0000446 int32_t t = instruction->times;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000447 if (t < 0)
448 errfunc(ERR_PANIC,
449 "instruction->times < 0 (%ld) in assemble()", t);
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000450
H. Peter Anvine2c80182005-01-15 22:15:51 +0000451 while (t--) { /* repeat TIMES times */
Cyrill Gorcunova92a3a52009-07-27 22:33:59 +0400452 list_for_each(e, instruction->eops) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000453 if (e->type == EOT_DB_NUMBER) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400454 if (wsize > 8) {
H. Peter Anvin3be5d852008-05-20 14:49:32 -0700455 errfunc(ERR_NONFATAL,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400456 "integer supplied to a DT, DO or DY"
Keith Kanios61ff53c2007-04-14 18:54:52 +0000457 " instruction");
H. Peter Anvin55ae1202010-05-06 15:25:43 -0700458 } else {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000459 out(offset, segment, &e->offset,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800460 OUT_ADDRESS, wsize, e->segment, e->wrt);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400461 offset += wsize;
462 }
H. Peter Anvin518df302008-06-14 16:53:48 -0700463 } else if (e->type == EOT_DB_STRING ||
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400464 e->type == EOT_DB_STRING_FREE) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000465 int align;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000466
H. Peter Anvine2c80182005-01-15 22:15:51 +0000467 out(offset, segment, e->stringval,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800468 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000469 align = e->stringlen % wsize;
H. Peter Anvineba20a72002-04-30 20:53:55 +0000470
H. Peter Anvine2c80182005-01-15 22:15:51 +0000471 if (align) {
472 align = wsize - align;
H. Peter Anvin999868f2009-02-09 11:03:33 +0100473 out(offset, segment, zero_buffer,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800474 OUT_RAWDATA, align, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000475 }
476 offset += e->stringlen + align;
477 }
478 }
479 if (t > 0 && t == instruction->times - 1) {
480 /*
481 * Dummy call to list->output to give the offset to the
482 * listing module.
483 */
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800484 list->output(offset, NULL, OUT_RAWDATA, 0);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000485 list->uplevel(LIST_TIMES);
486 }
487 }
488 if (instruction->times > 1)
489 list->downlevel(LIST_TIMES);
490 return offset - start;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000491 }
492
H. Peter Anvine2c80182005-01-15 22:15:51 +0000493 if (instruction->opcode == I_INCBIN) {
H. Peter Anvin518df302008-06-14 16:53:48 -0700494 const char *fname = instruction->eops->stringval;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000495 FILE *fp;
H. Peter Anvineba20a72002-04-30 20:53:55 +0000496
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400497 fp = fopen(fname, "rb");
498 if (!fp) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000499 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
500 fname);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400501 } else if (fseek(fp, 0L, SEEK_END) < 0) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000502 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
503 fname);
Philipp Klokedae212d2013-03-31 12:02:30 +0200504 fclose(fp);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400505 } else {
H. Peter Anvin518df302008-06-14 16:53:48 -0700506 static char buf[4096];
507 size_t t = instruction->times;
508 size_t base = 0;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400509 size_t len;
H. Peter Anvind7ed89e2002-04-30 20:52:08 +0000510
H. Peter Anvine2c80182005-01-15 22:15:51 +0000511 len = ftell(fp);
512 if (instruction->eops->next) {
513 base = instruction->eops->next->offset;
514 len -= base;
515 if (instruction->eops->next->next &&
H. Peter Anvin518df302008-06-14 16:53:48 -0700516 len > (size_t)instruction->eops->next->next->offset)
517 len = (size_t)instruction->eops->next->next->offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000518 }
519 /*
520 * Dummy call to list->output to give the offset to the
521 * listing module.
522 */
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800523 list->output(offset, NULL, OUT_RAWDATA, 0);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000524 list->uplevel(LIST_INCBIN);
525 while (t--) {
H. Peter Anvin518df302008-06-14 16:53:48 -0700526 size_t l;
H. Peter Anvineba20a72002-04-30 20:53:55 +0000527
H. Peter Anvine2c80182005-01-15 22:15:51 +0000528 fseek(fp, base, SEEK_SET);
529 l = len;
530 while (l > 0) {
H. Peter Anvin4a5a6df2009-06-27 16:14:18 -0700531 int32_t m;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400532 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000533 if (!m) {
534 /*
535 * This shouldn't happen unless the file
536 * actually changes while we are reading
537 * it.
538 */
539 error(ERR_NONFATAL,
540 "`incbin': unexpected EOF while"
541 " reading file `%s'", fname);
542 t = 0; /* Try to exit cleanly */
543 break;
544 }
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800545 out(offset, segment, buf, OUT_RAWDATA, m,
H. Peter Anvine2c80182005-01-15 22:15:51 +0000546 NO_SEG, NO_SEG);
547 l -= m;
548 }
549 }
550 list->downlevel(LIST_INCBIN);
551 if (instruction->times > 1) {
552 /*
553 * Dummy call to list->output to give the offset to the
554 * listing module.
555 */
H. Peter Anvin34f6fb02007-11-09 14:44:02 -0800556 list->output(offset, NULL, OUT_RAWDATA, 0);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000557 list->uplevel(LIST_TIMES);
558 list->downlevel(LIST_TIMES);
559 }
560 fclose(fp);
561 return instruction->times * len;
562 }
563 return 0; /* if we're here, there's an error */
H. Peter Anvind7ed89e2002-04-30 20:52:08 +0000564 }
565
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -0700566 /* Check to see if we need an address-size prefix */
567 add_asp(instruction, bits);
568
H. Peter Anvin23595f52009-07-25 17:44:25 -0700569 m = find_match(&temp, instruction, segment, offset, bits);
H. Peter Anvin70653092007-10-19 14:42:29 -0700570
H. Peter Anvin23595f52009-07-25 17:44:25 -0700571 if (m == MOK_GOOD) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400572 /* Matches! */
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800573 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400574 itimes = instruction->times;
575 if (insn_size < 0) /* shouldn't be, on pass two */
576 error(ERR_PANIC, "errors made it through from pass one");
577 else
578 while (itimes--) {
579 for (j = 0; j < MAXPREFIX; j++) {
580 uint8_t c = 0;
581 switch (instruction->prefixes[j]) {
582 case P_WAIT:
583 c = 0x9B;
584 break;
585 case P_LOCK:
586 c = 0xF0;
587 break;
588 case P_REPNE:
589 case P_REPNZ:
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800590 case P_XACQUIRE:
Jin Kyu Song03041092013-10-15 19:38:51 -0700591 case P_BND:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400592 c = 0xF2;
593 break;
594 case P_REPE:
595 case P_REPZ:
596 case P_REP:
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800597 case P_XRELEASE:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400598 c = 0xF3;
599 break;
600 case R_CS:
601 if (bits == 64) {
602 error(ERR_WARNING | ERR_PASS2,
603 "cs segment base generated, but will be ignored in 64-bit mode");
604 }
605 c = 0x2E;
606 break;
607 case R_DS:
608 if (bits == 64) {
609 error(ERR_WARNING | ERR_PASS2,
610 "ds segment base generated, but will be ignored in 64-bit mode");
611 }
612 c = 0x3E;
613 break;
614 case R_ES:
615 if (bits == 64) {
616 error(ERR_WARNING | ERR_PASS2,
617 "es segment base generated, but will be ignored in 64-bit mode");
618 }
619 c = 0x26;
620 break;
621 case R_FS:
622 c = 0x64;
623 break;
624 case R_GS:
625 c = 0x65;
626 break;
627 case R_SS:
628 if (bits == 64) {
629 error(ERR_WARNING | ERR_PASS2,
630 "ss segment base generated, but will be ignored in 64-bit mode");
631 }
632 c = 0x36;
633 break;
634 case R_SEGR6:
635 case R_SEGR7:
636 error(ERR_NONFATAL,
637 "segr6 and segr7 cannot be used as prefixes");
638 break;
639 case P_A16:
640 if (bits == 64) {
641 error(ERR_NONFATAL,
642 "16-bit addressing is not supported "
643 "in 64-bit mode");
644 } else if (bits != 16)
645 c = 0x67;
646 break;
647 case P_A32:
648 if (bits != 32)
649 c = 0x67;
650 break;
651 case P_A64:
652 if (bits != 64) {
653 error(ERR_NONFATAL,
654 "64-bit addressing is only supported "
655 "in 64-bit mode");
656 }
657 break;
658 case P_ASP:
659 c = 0x67;
660 break;
661 case P_O16:
662 if (bits != 16)
663 c = 0x66;
664 break;
665 case P_O32:
666 if (bits == 16)
667 c = 0x66;
668 break;
669 case P_O64:
670 /* REX.W */
671 break;
672 case P_OSP:
673 c = 0x66;
674 break;
Jin Kyu Song945b1b82013-10-25 19:29:53 -0700675 case P_EVEX:
H. Peter Anvin621a69a2013-11-28 12:11:24 -0800676 case P_VEX3:
677 case P_VEX2:
Jin Kyu Songb287ff02013-12-04 20:05:55 -0800678 case P_NOBND:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400679 case P_none:
680 break;
681 default:
682 error(ERR_PANIC, "invalid instruction prefix");
683 }
684 if (c != 0) {
685 out(offset, segment, &c, OUT_RAWDATA, 1,
686 NO_SEG, NO_SEG);
687 offset++;
688 }
689 }
690 insn_end = offset + insn_size;
691 gencode(segment, offset, bits, instruction,
692 temp, insn_end);
693 offset += insn_size;
694 if (itimes > 0 && itimes == instruction->times - 1) {
695 /*
696 * Dummy call to list->output to give the offset to the
697 * listing module.
698 */
699 list->output(offset, NULL, OUT_RAWDATA, 0);
700 list->uplevel(LIST_TIMES);
701 }
702 }
703 if (instruction->times > 1)
704 list->downlevel(LIST_TIMES);
705 return offset - start;
H. Peter Anvin23595f52009-07-25 17:44:25 -0700706 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400707 /* No match */
708 switch (m) {
709 case MERR_OPSIZEMISSING:
710 error(ERR_NONFATAL, "operation size not specified");
711 break;
712 case MERR_OPSIZEMISMATCH:
H. Peter Anvine2c80182005-01-15 22:15:51 +0000713 error(ERR_NONFATAL, "mismatch in operand sizes");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400714 break;
Jin Kyu Song25c22122013-10-30 03:12:45 -0700715 case MERR_BRNUMMISMATCH:
716 error(ERR_NONFATAL,
717 "mismatch in the number of broadcasting elements");
718 break;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400719 case MERR_BADCPU:
H. Peter Anvine2c80182005-01-15 22:15:51 +0000720 error(ERR_NONFATAL, "no instruction for this cpu level");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400721 break;
722 case MERR_BADMODE:
H. Peter Anvin6cda4142008-12-29 20:52:28 -0800723 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400724 bits);
725 break;
Jin Kyu Song6cfa9682013-11-26 17:27:48 -0800726 case MERR_ENCMISMATCH:
727 error(ERR_NONFATAL, "specific encoding scheme not available");
728 break;
Jin Kyu Song305f3ce2013-11-21 19:40:42 -0800729 case MERR_BADBND:
730 error(ERR_NONFATAL, "bnd prefix is not allowed");
731 break;
Jin Kyu Songb287ff02013-12-04 20:05:55 -0800732 case MERR_BADREPNE:
733 error(ERR_NONFATAL, "%s prefix is not allowed",
734 (has_prefix(instruction, PPS_REP, P_REPNE) ?
735 "repne" : "repnz"));
736 break;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400737 default:
H. Peter Anvine2c80182005-01-15 22:15:51 +0000738 error(ERR_NONFATAL,
739 "invalid combination of opcode and operands");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400740 break;
741 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000742 }
743 return 0;
744}
745
Cyrill Gorcunov08359152013-11-09 22:16:11 +0400746int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400747 insn * instruction, efunc error)
H. Peter Anvineba20a72002-04-30 20:53:55 +0000748{
H. Peter Anvin3360d792007-09-11 04:16:57 +0000749 const struct itemplate *temp;
H. Peter Anvin23595f52009-07-25 17:44:25 -0700750 enum match_result m;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000751
H. Peter Anvine2c80182005-01-15 22:15:51 +0000752 errfunc = error; /* to pass to other functions */
H. Peter Anvinaf535c12002-04-30 20:59:21 +0000753 cpu = cp;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000754
Cyrill Gorcunov37575242009-08-16 12:00:01 +0400755 if (instruction->opcode == I_none)
H. Peter Anvine2c80182005-01-15 22:15:51 +0000756 return 0;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000757
H. Peter Anvincfbe7c32007-09-18 17:49:09 -0700758 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
759 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400760 instruction->opcode == I_DT || instruction->opcode == I_DO ||
761 instruction->opcode == I_DY) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000762 extop *e;
Cyrill Gorcunovbafd8772009-10-31 20:02:14 +0300763 int32_t isize, osize, wsize;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000764
H. Peter Anvine2c80182005-01-15 22:15:51 +0000765 isize = 0;
Cyrill Gorcunovbafd8772009-10-31 20:02:14 +0300766 wsize = idata_bytes(instruction->opcode);
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000767
Cyrill Gorcunova92a3a52009-07-27 22:33:59 +0400768 list_for_each(e, instruction->eops) {
Keith Kaniosb7a89542007-04-12 02:40:54 +0000769 int32_t align;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000770
H. Peter Anvine2c80182005-01-15 22:15:51 +0000771 osize = 0;
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +0400772 if (e->type == EOT_DB_NUMBER) {
H. Peter Anvine2c80182005-01-15 22:15:51 +0000773 osize = 1;
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +0400774 warn_overflow_const(e->offset, wsize);
775 } else if (e->type == EOT_DB_STRING ||
776 e->type == EOT_DB_STRING_FREE)
H. Peter Anvine2c80182005-01-15 22:15:51 +0000777 osize = e->stringlen;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000778
H. Peter Anvine2c80182005-01-15 22:15:51 +0000779 align = (-osize) % wsize;
780 if (align < 0)
781 align += wsize;
782 isize += osize + align;
783 }
784 return isize * instruction->times;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000785 }
786
H. Peter Anvine2c80182005-01-15 22:15:51 +0000787 if (instruction->opcode == I_INCBIN) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400788 const char *fname = instruction->eops->stringval;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000789 FILE *fp;
Cyrill Gorcunov6531d6d2009-12-05 14:04:55 +0300790 int64_t val = 0;
H. Peter Anvin518df302008-06-14 16:53:48 -0700791 size_t len;
H. Peter Anvind7ed89e2002-04-30 20:52:08 +0000792
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400793 fp = fopen(fname, "rb");
794 if (!fp)
H. Peter Anvine2c80182005-01-15 22:15:51 +0000795 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
796 fname);
797 else if (fseek(fp, 0L, SEEK_END) < 0)
798 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
799 fname);
800 else {
801 len = ftell(fp);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000802 if (instruction->eops->next) {
803 len -= instruction->eops->next->offset;
804 if (instruction->eops->next->next &&
H. Peter Anvin518df302008-06-14 16:53:48 -0700805 len > (size_t)instruction->eops->next->next->offset) {
806 len = (size_t)instruction->eops->next->next->offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000807 }
808 }
Cyrill Gorcunov6531d6d2009-12-05 14:04:55 +0300809 val = instruction->times * len;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000810 }
Cyrill Gorcunov6531d6d2009-12-05 14:04:55 +0300811 if (fp)
812 fclose(fp);
813 return val;
H. Peter Anvind7ed89e2002-04-30 20:52:08 +0000814 }
815
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -0700816 /* Check to see if we need an address-size prefix */
817 add_asp(instruction, bits);
818
H. Peter Anvin23595f52009-07-25 17:44:25 -0700819 m = find_match(&temp, instruction, segment, offset, bits);
820 if (m == MOK_GOOD) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400821 /* we've matched an instruction. */
822 int64_t isize;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400823 int j;
Victor van den Elzen0d268fb2010-01-24 21:24:57 +0100824
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800825 isize = calcsize(segment, offset, bits, instruction, temp);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400826 if (isize < 0)
827 return -1;
828 for (j = 0; j < MAXPREFIX; j++) {
829 switch (instruction->prefixes[j]) {
830 case P_A16:
831 if (bits != 16)
832 isize++;
833 break;
834 case P_A32:
835 if (bits != 32)
836 isize++;
837 break;
838 case P_O16:
839 if (bits != 16)
840 isize++;
841 break;
842 case P_O32:
843 if (bits == 16)
844 isize++;
845 break;
846 case P_A64:
847 case P_O64:
Jin Kyu Song945b1b82013-10-25 19:29:53 -0700848 case P_EVEX:
H. Peter Anvin621a69a2013-11-28 12:11:24 -0800849 case P_VEX3:
850 case P_VEX2:
Jin Kyu Songb287ff02013-12-04 20:05:55 -0800851 case P_NOBND:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400852 case P_none:
853 break;
854 default:
855 isize++;
856 break;
857 }
858 }
859 return isize * instruction->times;
H. Peter Anvin23595f52009-07-25 17:44:25 -0700860 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400861 return -1; /* didn't match any instruction */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000862 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000863}
864
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800865static void bad_hle_warn(const insn * ins, uint8_t hleok)
866{
867 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800868 enum whatwarn { w_none, w_lock, w_inval } ww;
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800869 static const enum whatwarn warn[2][4] =
870 {
871 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
872 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
873 };
874 unsigned int n;
875
876 n = (unsigned int)rep_pfx - P_XACQUIRE;
877 if (n > 1)
878 return; /* Not XACQUIRE/XRELEASE */
879
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800880 ww = warn[n][hleok];
881 if (!is_class(MEMORY, ins->oprs[0].type))
882 ww = w_inval; /* HLE requires operand 0 to be memory */
883
884 switch (ww) {
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800885 case w_none:
886 break;
887
888 case w_lock:
889 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
H. Peter Anvin5a24fdd2012-02-25 15:10:04 -0800890 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800891 "%s with this instruction requires lock",
892 prefix_name(rep_pfx));
893 }
894 break;
895
896 case w_inval:
H. Peter Anvin5a24fdd2012-02-25 15:10:04 -0800897 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800898 "%s invalid with this instruction",
899 prefix_name(rep_pfx));
900 break;
901 }
902}
903
H. Peter Anvin507ae032008-10-09 15:37:10 -0700904/* Common construct */
Cyrill Gorcunov62576a02012-12-02 02:47:16 +0400905#define case3(x) case (x): case (x)+1: case (x)+2
906#define case4(x) case3(x): case (x)+3
H. Peter Anvin507ae032008-10-09 15:37:10 -0700907
Charles Crayne1f8bc4c2007-11-06 18:27:23 -0800908static int64_t calcsize(int32_t segment, int64_t offset, int bits,
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800909 insn * ins, const struct itemplate *temp)
H. Peter Anvineba20a72002-04-30 20:53:55 +0000910{
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800911 const uint8_t *codes = temp->code;
Charles Crayne1f8bc4c2007-11-06 18:27:23 -0800912 int64_t length = 0;
Keith Kaniosb7a89542007-04-12 02:40:54 +0000913 uint8_t c;
H. Peter Anvin3df97a72007-05-30 03:25:21 +0000914 int rex_mask = ~0;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -0700915 int op1, op2;
H. Peter Anvin839eca22007-10-29 23:12:47 -0700916 struct operand *opx;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -0700917 uint8_t opex = 0;
H. Peter Anvin3089f7e2011-06-22 18:19:28 -0700918 enum ea_type eat;
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -0800919 uint8_t hleok = 0;
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -0800920 bool lockcheck = true;
Jin Kyu Song164d6072013-10-15 19:10:13 -0700921 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
H. Peter Anvineba20a72002-04-30 20:53:55 +0000922
H. Peter Anvine3917fc2007-11-01 14:53:32 -0700923 ins->rex = 0; /* Ensure REX is reset */
H. Peter Anvin3089f7e2011-06-22 18:19:28 -0700924 eat = EA_SCALAR; /* Expect a scalar EA */
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -0700925 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
H. Peter Anvine3917fc2007-11-01 14:53:32 -0700926
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700927 if (ins->prefixes[PPS_OSIZE] == P_O64)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400928 ins->rex |= REX_W;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700929
H. Peter Anvine2c80182005-01-15 22:15:51 +0000930 (void)segment; /* Don't warn that this parameter is unused */
931 (void)offset; /* Don't warn that this parameter is unused */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +0000932
H. Peter Anvin839eca22007-10-29 23:12:47 -0700933 while (*codes) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400934 c = *codes++;
935 op1 = (c & 3) + ((opex & 1) << 2);
936 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
937 opx = &ins->oprs[op1];
938 opex = 0; /* For the next iteration */
H. Peter Anvindcffe4b2008-10-10 22:10:31 -0700939
H. Peter Anvin839eca22007-10-29 23:12:47 -0700940 switch (c) {
Cyrill Gorcunov59df4212012-12-02 02:51:18 +0400941 case4(01):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000942 codes += c, length += c;
943 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700944
Cyrill Gorcunov59df4212012-12-02 02:51:18 +0400945 case3(05):
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400946 opex = c;
947 break;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -0700948
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400949 case4(010):
950 ins->rex |=
951 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
H. Peter Anvine2c80182005-01-15 22:15:51 +0000952 codes++, length++;
953 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700954
Jin Kyu Song164d6072013-10-15 19:10:13 -0700955 case4(014):
956 /* this is an index reg of MIB operand */
957 mib_index = opx->basereg;
958 break;
959
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400960 case4(020):
961 case4(024):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000962 length++;
963 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700964
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400965 case4(030):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000966 length += 2;
967 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700968
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400969 case4(034):
H. Peter Anvin839eca22007-10-29 23:12:47 -0700970 if (opx->type & (BITS16 | BITS32 | BITS64))
971 length += (opx->type & BITS16) ? 2 : 4;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000972 else
973 length += (bits == 16) ? 2 : 4;
974 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700975
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400976 case4(040):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000977 length += 4;
978 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700979
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400980 case4(044):
H. Peter Anvinde4b89b2007-10-01 15:41:25 -0700981 length += ins->addr_size >> 3;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000982 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700983
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400984 case4(050):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000985 length++;
986 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700987
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400988 case4(054):
Keith Kaniosb7a89542007-04-12 02:40:54 +0000989 length += 8; /* MOV reg64/imm */
990 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700991
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400992 case4(060):
H. Peter Anvine2c80182005-01-15 22:15:51 +0000993 length += 2;
994 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -0700995
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +0400996 case4(064):
H. Peter Anvin839eca22007-10-29 23:12:47 -0700997 if (opx->type & (BITS16 | BITS32 | BITS64))
998 length += (opx->type & BITS16) ? 2 : 4;
H. Peter Anvine2c80182005-01-15 22:15:51 +0000999 else
1000 length += (bits == 16) ? 2 : 4;
1001 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001002
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001003 case4(070):
H. Peter Anvine2c80182005-01-15 22:15:51 +00001004 length += 4;
1005 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001006
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001007 case4(074):
H. Peter Anvin7eb4a382007-09-17 15:49:30 -07001008 length += 2;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001009 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001010
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001011 case 0172:
1012 case 0173:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001013 codes++;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001014 length++;
1015 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001016
H. Peter Anvincffe61e2011-07-07 17:21:24 -07001017 case4(0174):
1018 length++;
1019 break;
1020
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001021 case4(0240):
1022 ins->rex |= REX_EV;
1023 ins->vexreg = regval(opx);
1024 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1025 ins->vex_cm = *codes++;
1026 ins->vex_wlp = *codes++;
1027 ins->evex_tuple = (*codes++ - 0300);
1028 break;
1029
1030 case 0250:
1031 ins->rex |= REX_EV;
1032 ins->vexreg = 0;
1033 ins->vex_cm = *codes++;
1034 ins->vex_wlp = *codes++;
1035 ins->evex_tuple = (*codes++ - 0300);
1036 break;
1037
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001038 case4(0254):
1039 length += 4;
1040 break;
1041
1042 case4(0260):
1043 ins->rex |= REX_V;
H. Peter Anvinfc561202011-07-07 16:58:22 -07001044 ins->vexreg = regval(opx);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001045 ins->vex_cm = *codes++;
1046 ins->vex_wlp = *codes++;
1047 break;
1048
1049 case 0270:
1050 ins->rex |= REX_V;
H. Peter Anvinfc561202011-07-07 16:58:22 -07001051 ins->vexreg = 0;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001052 ins->vex_cm = *codes++;
1053 ins->vex_wlp = *codes++;
1054 break;
1055
Cyrill Gorcunov59df4212012-12-02 02:51:18 +04001056 case3(0271):
H. Peter Anvin574784d2012-02-25 22:33:46 -08001057 hleok = c & 3;
1058 break;
1059
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001060 case4(0274):
1061 length++;
1062 break;
1063
1064 case4(0300):
H. Peter Anvine2c80182005-01-15 22:15:51 +00001065 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001066
H. Peter Anvine2c80182005-01-15 22:15:51 +00001067 case 0310:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001068 if (bits == 64)
1069 return -1;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07001070 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001071 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001072
H. Peter Anvine2c80182005-01-15 22:15:51 +00001073 case 0311:
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07001074 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001075 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001076
H. Peter Anvine2c80182005-01-15 22:15:51 +00001077 case 0312:
H. Peter Anvin70653092007-10-19 14:42:29 -07001078 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001079
Keith Kaniosb7a89542007-04-12 02:40:54 +00001080 case 0313:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001081 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1082 has_prefix(ins, PPS_ASIZE, P_A32))
1083 return -1;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001084 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001085
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001086 case4(0314):
1087 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001088
H. Peter Anvine2c80182005-01-15 22:15:51 +00001089 case 0320:
Victor van den Elzen6dfbddb2010-12-29 17:13:38 +00001090 {
1091 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1092 if (pfx == P_O16)
1093 break;
1094 if (pfx != P_none)
1095 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1096 else
1097 ins->prefixes[PPS_OSIZE] = P_O16;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001098 break;
Victor van den Elzen6dfbddb2010-12-29 17:13:38 +00001099 }
H. Peter Anvin507ae032008-10-09 15:37:10 -07001100
H. Peter Anvine2c80182005-01-15 22:15:51 +00001101 case 0321:
Victor van den Elzen6dfbddb2010-12-29 17:13:38 +00001102 {
1103 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1104 if (pfx == P_O32)
1105 break;
1106 if (pfx != P_none)
1107 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1108 else
1109 ins->prefixes[PPS_OSIZE] = P_O32;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001110 break;
Victor van den Elzen6dfbddb2010-12-29 17:13:38 +00001111 }
H. Peter Anvin507ae032008-10-09 15:37:10 -07001112
H. Peter Anvine2c80182005-01-15 22:15:51 +00001113 case 0322:
1114 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001115
Keith Kaniosb7a89542007-04-12 02:40:54 +00001116 case 0323:
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001117 rex_mask &= ~REX_W;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001118 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001119
Keith Kaniosb7a89542007-04-12 02:40:54 +00001120 case 0324:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001121 ins->rex |= REX_W;
H. Peter Anvin8d7316a2007-04-18 02:27:18 +00001122 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001123
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001124 case 0325:
1125 ins->rex |= REX_NH;
1126 break;
H. Peter Anvin9472dab2009-06-24 21:38:29 -07001127
Ben Rudiak-Gouldd7ab1f92013-02-20 23:25:54 +04001128 case 0326:
1129 break;
1130
H. Peter Anvine2c80182005-01-15 22:15:51 +00001131 case 0330:
1132 codes++, length++;
1133 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001134
H. Peter Anvine2c80182005-01-15 22:15:51 +00001135 case 0331:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001136 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001137
H. Peter Anvincb9b6902007-09-12 21:58:51 -07001138 case 0332:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001139 case 0333:
1140 length++;
1141 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001142
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001143 case 0334:
1144 ins->rex |= REX_L;
1145 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001146
H. Peter Anvincb9b6902007-09-12 21:58:51 -07001147 case 0335:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001148 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001149
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001150 case 0336:
H. Peter Anvin10da41e2012-02-24 20:57:04 -08001151 if (!ins->prefixes[PPS_REP])
1152 ins->prefixes[PPS_REP] = P_REP;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001153 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001154
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001155 case 0337:
H. Peter Anvin10da41e2012-02-24 20:57:04 -08001156 if (!ins->prefixes[PPS_REP])
1157 ins->prefixes[PPS_REP] = P_REPNE;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001158 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001159
H. Peter Anvine2c80182005-01-15 22:15:51 +00001160 case 0340:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001161 if (ins->oprs[0].segment != NO_SEG)
1162 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1163 " quantity of BSS space");
1164 else
H. Peter Anvin428fd672007-11-15 10:25:52 -08001165 length += ins->oprs[0].offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001166 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001167
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001168 case 0341:
1169 if (!ins->prefixes[PPS_WAIT])
1170 ins->prefixes[PPS_WAIT] = P_WAIT;
1171 break;
H. Peter Anvinc2acf7b2009-02-21 18:22:56 -08001172
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001173 case 0360:
1174 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001175
Ben Rudiak-Gould94ba02f2013-03-10 21:46:12 +04001176 case 0361:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001177 length++;
1178 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001179
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001180 case 0364:
1181 case 0365:
1182 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001183
Keith Kanios48af1772007-08-17 07:37:52 +00001184 case 0366:
H. Peter Anvin62cb6062007-09-11 22:44:03 +00001185 case 0367:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001186 length++;
1187 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001188
Jin Kyu Songb4e1ae12013-11-08 13:31:58 -08001189 case 0370:
1190 case 0371:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001191 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001192
H. Peter Anvine2c80182005-01-15 22:15:51 +00001193 case 0373:
1194 length++;
1195 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001196
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07001197 case 0374:
1198 eat = EA_XMMVSIB;
1199 break;
1200
1201 case 0375:
1202 eat = EA_YMMVSIB;
1203 break;
1204
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001205 case 0376:
1206 eat = EA_ZMMVSIB;
1207 break;
1208
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001209 case4(0100):
1210 case4(0110):
1211 case4(0120):
1212 case4(0130):
1213 case4(0200):
1214 case4(0204):
1215 case4(0210):
1216 case4(0214):
1217 case4(0220):
1218 case4(0224):
1219 case4(0230):
1220 case4(0234):
1221 {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001222 ea ea_data;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001223 int rfield;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001224 opflags_t rflags;
1225 struct operand *opy = &ins->oprs[op2];
Jin Kyu Songe3a06b92013-08-28 19:15:23 -07001226 struct operand *op_er_sae;
H. Peter Anvinae64c9d2008-10-25 00:41:00 -07001227
Keith Kaniosb7a89542007-04-12 02:40:54 +00001228 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
H. Peter Anvin70653092007-10-19 14:42:29 -07001229
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001230 if (c <= 0177) {
1231 /* pick rfield from operand b (opx) */
1232 rflags = regflag(opx);
1233 rfield = nasm_regvals[opx->basereg];
1234 } else {
1235 rflags = 0;
1236 rfield = c & 7;
1237 }
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001238
Jin Kyu Songe3a06b92013-08-28 19:15:23 -07001239 /* EVEX.b1 : evex_brerop contains the operand position */
1240 op_er_sae = (ins->evex_brerop >= 0 ?
1241 &ins->oprs[ins->evex_brerop] : NULL);
1242
Jin Kyu Songc47ef942013-08-30 18:10:35 -07001243 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1244 /* set EVEX.b */
1245 ins->evex_p[2] |= EVEX_P2B;
1246 if (op_er_sae->decoflags & ER) {
1247 /* set EVEX.RC (rounding control) */
1248 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1249 & EVEX_P2RC;
1250 }
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001251 } else {
1252 /* set EVEX.L'L (vector length) */
1253 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
Jin Kyu Song5f3bfee2013-11-20 15:32:52 -08001254 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
Jin Kyu Songc47ef942013-08-30 18:10:35 -07001255 if (opy->decoflags & BRDCAST_MASK) {
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001256 /* set EVEX.b */
1257 ins->evex_p[2] |= EVEX_P2B;
1258 }
1259 }
1260
Jin Kyu Song4360ba22013-12-10 16:24:45 -08001261 if (itemp_has(temp, IF_MIB)) {
1262 opy->eaflags |= EAF_MIB;
1263 /*
1264 * if a separate form of MIB (ICC style) is used,
1265 * the index reg info is merged into mem operand
1266 */
1267 if (mib_index != R_none) {
1268 opy->indexreg = mib_index;
1269 opy->scale = 1;
1270 opy->hintbase = mib_index;
1271 opy->hinttype = EAH_NOTBASE;
1272 }
Jin Kyu Song3b653232013-11-08 11:41:12 -08001273 }
1274
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001275 if (process_ea(opy, &ea_data, bits,
1276 rfield, rflags, ins) != eat) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001277 errfunc(ERR_NONFATAL, "invalid effective address");
1278 return -1;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001279 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001280 ins->rex |= ea_data.rex;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001281 length += ea_data.size;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001282 }
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001283 }
1284 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001285
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001286 default:
1287 errfunc(ERR_PANIC, "internal instruction table corrupt"
1288 ": instruction code \\%o (0x%02X) given", c, c);
1289 break;
1290 }
H. Peter Anvin839eca22007-10-29 23:12:47 -07001291 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00001292
H. Peter Anvin0db11e22007-04-17 20:23:11 +00001293 ins->rex &= rex_mask;
H. Peter Anvin70653092007-10-19 14:42:29 -07001294
H. Peter Anvin9472dab2009-06-24 21:38:29 -07001295 if (ins->rex & REX_NH) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001296 if (ins->rex & REX_H) {
1297 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1298 return -1;
1299 }
1300 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
H. Peter Anvin9472dab2009-06-24 21:38:29 -07001301 }
1302
H. Peter Anvin621a69a2013-11-28 12:11:24 -08001303 switch (ins->prefixes[PPS_VEX]) {
1304 case P_EVEX:
1305 if (!(ins->rex & REX_EV))
1306 return -1;
1307 break;
1308 case P_VEX3:
1309 case P_VEX2:
1310 if (!(ins->rex & REX_V))
1311 return -1;
1312 break;
1313 default:
1314 break;
1315 }
1316
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001317 if (ins->rex & (REX_V | REX_EV)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001318 int bad32 = REX_R|REX_W|REX_X|REX_B;
H. Peter Anvind85d2502008-05-04 17:53:31 -07001319
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001320 if (ins->rex & REX_H) {
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001321 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001322 return -1;
1323 }
H. Peter Anvin421059c2010-08-16 14:56:33 -07001324 switch (ins->vex_wlp & 060) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001325 case 000:
H. Peter Anvin229fa6c2010-08-16 15:21:48 -07001326 case 040:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001327 ins->rex &= ~REX_W;
1328 break;
H. Peter Anvin229fa6c2010-08-16 15:21:48 -07001329 case 020:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001330 ins->rex |= REX_W;
1331 bad32 &= ~REX_W;
1332 break;
H. Peter Anvin421059c2010-08-16 14:56:33 -07001333 case 060:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001334 /* Follow REX_W */
1335 break;
1336 }
H. Peter Anvind85d2502008-05-04 17:53:31 -07001337
H. Peter Anvinfc561202011-07-07 16:58:22 -07001338 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001339 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1340 return -1;
Jin Kyu Song66c61922013-08-26 20:28:43 -07001341 } else if (!(ins->rex & REX_EV) &&
1342 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1343 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1344 return -1;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001345 }
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001346 if (ins->rex & REX_EV)
1347 length += 4;
H. Peter Anvin621a69a2013-11-28 12:11:24 -08001348 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1349 ins->prefixes[PPS_VEX] == P_VEX3)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001350 length += 3;
1351 else
1352 length += 2;
Cyrill Gorcunov5b144752014-05-06 01:50:22 +04001353 } else if (ins->rex & REX_MASK) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001354 if (ins->rex & REX_H) {
1355 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1356 return -1;
1357 } else if (bits == 64) {
1358 length++;
1359 } else if ((ins->rex & REX_L) &&
1360 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
Cyrill Gorcunov08359152013-11-09 22:16:11 +04001361 iflag_ffs(&cpu) >= IF_X86_64) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001362 /* LOCK-as-REX.R */
H. Peter Anvin10da41e2012-02-24 20:57:04 -08001363 assert_no_prefix(ins, PPS_LOCK);
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -08001364 lockcheck = false; /* Already errored, no need for warning */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001365 length++;
1366 } else {
1367 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1368 return -1;
1369 }
Keith Kaniosb7a89542007-04-12 02:40:54 +00001370 }
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -08001371
1372 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
Cyrill Gorcunov08359152013-11-09 22:16:11 +04001373 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
H. Peter Anvin5a24fdd2012-02-25 15:10:04 -08001374 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -08001375 "instruction is not lockable");
1376 }
1377
H. Peter Anvin4ecd5d72012-02-24 21:51:46 -08001378 bad_hle_warn(ins, hleok);
Keith Kaniosb7a89542007-04-12 02:40:54 +00001379
Jin Kyu Songb287ff02013-12-04 20:05:55 -08001380 /*
1381 * when BND prefix is set by DEFAULT directive,
1382 * BND prefix is added to every appropriate instruction line
1383 * unless it is overridden by NOBND prefix.
1384 */
1385 if (globalbnd &&
1386 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1387 ins->prefixes[PPS_REP] = P_BND;
1388
H. Peter Anvin0db11e22007-04-17 20:23:11 +00001389 return length;
1390}
Keith Kaniosb7a89542007-04-12 02:40:54 +00001391
Cyrill Gorcunov98238762013-03-02 02:48:23 +04001392static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1393{
1394 if (bits == 64) {
H. Peter Anvin89f78f52014-05-21 08:30:40 -07001395 if ((ins->rex & REX_MASK) &&
H. Peter Anvin0a9250c2014-05-21 08:19:16 -07001396 !(ins->rex & (REX_V | REX_EV)) &&
1397 !ins->rex_done) {
Cyrill Gorcunov5b144752014-05-06 01:50:22 +04001398 int rex = (ins->rex & REX_MASK) | REX_P;
Cyrill Gorcunovaa29b1d2014-05-05 00:30:58 +04001399 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvin0a9250c2014-05-21 08:19:16 -07001400 ins->rex_done = true;
Cyrill Gorcunov98238762013-03-02 02:48:23 +04001401 return 1;
1402 }
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001403 }
1404
Cyrill Gorcunov98238762013-03-02 02:48:23 +04001405 return 0;
1406}
1407
Charles Crayne1f8bc4c2007-11-06 18:27:23 -08001408static void gencode(int32_t segment, int64_t offset, int bits,
H. Peter Anvin833caea2008-10-04 19:02:30 -07001409 insn * ins, const struct itemplate *temp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001410 int64_t insn_end)
H. Peter Anvineba20a72002-04-30 20:53:55 +00001411{
Keith Kaniosb7a89542007-04-12 02:40:54 +00001412 uint8_t c;
1413 uint8_t bytes[4];
Charles Crayne1f8bc4c2007-11-06 18:27:23 -08001414 int64_t size;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001415 int64_t data;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -07001416 int op1, op2;
H. Peter Anvin839eca22007-10-29 23:12:47 -07001417 struct operand *opx;
H. Peter Anvin833caea2008-10-04 19:02:30 -07001418 const uint8_t *codes = temp->code;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -07001419 uint8_t opex = 0;
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07001420 enum ea_type eat = EA_SCALAR;
H. Peter Anvin70653092007-10-19 14:42:29 -07001421
H. Peter Anvin0a9250c2014-05-21 08:19:16 -07001422 ins->rex_done = false;
1423
H. Peter Anvin839eca22007-10-29 23:12:47 -07001424 while (*codes) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001425 c = *codes++;
1426 op1 = (c & 3) + ((opex & 1) << 2);
1427 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1428 opx = &ins->oprs[op1];
1429 opex = 0; /* For the next iteration */
H. Peter Anvindcffe4b2008-10-10 22:10:31 -07001430
H. Peter Anvin839eca22007-10-29 23:12:47 -07001431 switch (c) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001432 case 01:
1433 case 02:
1434 case 03:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001435 case 04:
Cyrill Gorcunov98238762013-03-02 02:48:23 +04001436 offset += emit_rex(ins, segment, offset, bits);
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001437 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001438 codes += c;
1439 offset += c;
1440 break;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00001441
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001442 case 05:
1443 case 06:
1444 case 07:
1445 opex = c;
1446 break;
H. Peter Anvindcffe4b2008-10-10 22:10:31 -07001447
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001448 case4(010):
Cyrill Gorcunov98238762013-03-02 02:48:23 +04001449 offset += emit_rex(ins, segment, offset, bits);
H. Peter Anvindcffe4b2008-10-10 22:10:31 -07001450 bytes[0] = *codes++ + (regval(opx) & 7);
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001451 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001452 offset += 1;
1453 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001454
Jin Kyu Song164d6072013-10-15 19:10:13 -07001455 case4(014):
1456 break;
1457
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001458 case4(020):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001459 if (opx->offset < -256 || opx->offset > 255) {
H. Peter Anvine9d7f1a2008-10-05 19:42:55 -07001460 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001461 "byte value exceeds bounds");
H. Peter Anvine2c80182005-01-15 22:15:51 +00001462 }
H. Peter Anvin89a2ac02013-11-26 18:23:20 -08001463 out_imm8(offset, segment, opx, -1);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001464 offset += 1;
1465 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001466
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001467 case4(024):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001468 if (opx->offset < 0 || opx->offset > 255)
H. Peter Anvine9d7f1a2008-10-05 19:42:55 -07001469 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001470 "unsigned byte value exceeds bounds");
H. Peter Anvin89a2ac02013-11-26 18:23:20 -08001471 out_imm8(offset, segment, opx, 1);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001472 offset += 1;
1473 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001474
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001475 case4(030):
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +04001476 warn_overflow_opd(opx, 2);
H. Peter Anvin839eca22007-10-29 23:12:47 -07001477 data = opx->offset;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001478 out(offset, segment, &data, OUT_ADDRESS, 2,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001479 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001480 offset += 2;
1481 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001482
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001483 case4(034):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001484 if (opx->type & (BITS16 | BITS32))
1485 size = (opx->type & BITS16) ? 2 : 4;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001486 else
1487 size = (bits == 16) ? 2 : 4;
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +04001488 warn_overflow_opd(opx, size);
H. Peter Anvin839eca22007-10-29 23:12:47 -07001489 data = opx->offset;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001490 out(offset, segment, &data, OUT_ADDRESS, size,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001491 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001492 offset += size;
1493 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001494
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001495 case4(040):
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +04001496 warn_overflow_opd(opx, 4);
H. Peter Anvin839eca22007-10-29 23:12:47 -07001497 data = opx->offset;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001498 out(offset, segment, &data, OUT_ADDRESS, 4,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001499 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001500 offset += 4;
1501 break;
H. Peter Anvin3ba46772002-05-27 23:19:35 +00001502
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001503 case4(044):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001504 data = opx->offset;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07001505 size = ins->addr_size >> 3;
Cyrill Gorcunov9ccabd22009-09-21 00:56:20 +04001506 warn_overflow_opd(opx, size);
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001507 out(offset, segment, &data, OUT_ADDRESS, size,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001508 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001509 offset += size;
1510 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001511
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001512 case4(050):
H. Peter Anvinfea84d72010-05-06 15:32:20 -07001513 if (opx->segment != segment) {
1514 data = opx->offset;
1515 out(offset, segment, &data,
1516 OUT_REL1ADR, insn_end - offset,
1517 opx->segment, opx->wrt);
1518 } else {
1519 data = opx->offset - insn_end;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001520 if (data > 127 || data < -128)
1521 errfunc(ERR_NONFATAL, "short jump is out of range");
H. Peter Anvinfea84d72010-05-06 15:32:20 -07001522 out(offset, segment, &data,
1523 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1524 }
H. Peter Anvine2c80182005-01-15 22:15:51 +00001525 offset += 1;
1526 break;
H. Peter Anvin70653092007-10-19 14:42:29 -07001527
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001528 case4(054):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001529 data = (int64_t)opx->offset;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001530 out(offset, segment, &data, OUT_ADDRESS, 8,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001531 opx->segment, opx->wrt);
Keith Kaniosb7a89542007-04-12 02:40:54 +00001532 offset += 8;
1533 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001534
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001535 case4(060):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001536 if (opx->segment != segment) {
1537 data = opx->offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001538 out(offset, segment, &data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001539 OUT_REL2ADR, insn_end - offset,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001540 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001541 } else {
H. Peter Anvin839eca22007-10-29 23:12:47 -07001542 data = opx->offset - insn_end;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001543 out(offset, segment, &data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001544 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001545 }
1546 offset += 2;
1547 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001548
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001549 case4(064):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001550 if (opx->type & (BITS16 | BITS32 | BITS64))
1551 size = (opx->type & BITS16) ? 2 : 4;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001552 else
1553 size = (bits == 16) ? 2 : 4;
H. Peter Anvin839eca22007-10-29 23:12:47 -07001554 if (opx->segment != segment) {
H. Peter Anvin839eca22007-10-29 23:12:47 -07001555 data = opx->offset;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001556 out(offset, segment, &data,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001557 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1558 insn_end - offset, opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001559 } else {
H. Peter Anvin839eca22007-10-29 23:12:47 -07001560 data = opx->offset - insn_end;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001561 out(offset, segment, &data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001562 OUT_ADDRESS, size, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001563 }
1564 offset += size;
1565 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001566
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001567 case4(070):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001568 if (opx->segment != segment) {
1569 data = opx->offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001570 out(offset, segment, &data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001571 OUT_REL4ADR, insn_end - offset,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001572 opx->segment, opx->wrt);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001573 } else {
H. Peter Anvin839eca22007-10-29 23:12:47 -07001574 data = opx->offset - insn_end;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001575 out(offset, segment, &data,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001576 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001577 }
1578 offset += 4;
1579 break;
H. Peter Anvinaf535c12002-04-30 20:59:21 +00001580
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001581 case4(074):
H. Peter Anvin839eca22007-10-29 23:12:47 -07001582 if (opx->segment == NO_SEG)
H. Peter Anvin7eb4a382007-09-17 15:49:30 -07001583 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1584 " relocatable");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001585 data = 0;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001586 out(offset, segment, &data, OUT_ADDRESS, 2,
H. Peter Anvin839eca22007-10-29 23:12:47 -07001587 outfmt->segbase(1 + opx->segment),
1588 opx->wrt);
H. Peter Anvin7eb4a382007-09-17 15:49:30 -07001589 offset += 2;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001590 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001591
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001592 case 0172:
1593 c = *codes++;
1594 opx = &ins->oprs[c >> 3];
1595 bytes[0] = nasm_regvals[opx->basereg] << 4;
1596 opx = &ins->oprs[c & 7];
1597 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1598 errfunc(ERR_NONFATAL,
1599 "non-absolute expression not permitted as argument %d",
1600 c & 7);
1601 } else {
1602 if (opx->offset & ~15) {
1603 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1604 "four-bit argument exceeds bounds");
1605 }
1606 bytes[0] |= opx->offset & 15;
1607 }
1608 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1609 offset++;
1610 break;
H. Peter Anvind85d2502008-05-04 17:53:31 -07001611
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001612 case 0173:
1613 c = *codes++;
1614 opx = &ins->oprs[c >> 4];
1615 bytes[0] = nasm_regvals[opx->basereg] << 4;
1616 bytes[0] |= c & 15;
1617 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1618 offset++;
1619 break;
H. Peter Anvind58656f2008-05-06 20:11:14 -07001620
H. Peter Anvincffe61e2011-07-07 17:21:24 -07001621 case4(0174):
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001622 bytes[0] = nasm_regvals[opx->basereg] << 4;
1623 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1624 offset++;
1625 break;
H. Peter Anvin52dc3532008-05-20 19:29:04 -07001626
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001627 case4(0254):
H. Peter Anvin588df782008-10-07 10:05:10 -07001628 data = opx->offset;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001629 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1630 (int32_t)data != (int64_t)data) {
1631 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1632 "signed dword immediate exceeds bounds");
1633 }
H. Peter Anvin89a2ac02013-11-26 18:23:20 -08001634 out(offset, segment, &data, OUT_ADDRESS, -4,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001635 opx->segment, opx->wrt);
1636 offset += 4;
H. Peter Anvin588df782008-10-07 10:05:10 -07001637 break;
1638
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001639 case4(0240):
1640 case 0250:
1641 codes += 3;
1642 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1643 EVEX_P2Z | EVEX_P2AAA, 2);
1644 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1645 bytes[0] = 0x62;
1646 /* EVEX.X can be set by either REX or EVEX for different reasons */
Jin Kyu Song1be09ee2013-11-08 01:14:39 -08001647 bytes[1] = ((((ins->rex & 7) << 5) |
1648 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1649 (ins->vex_cm & 3);
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001650 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1651 ((~ins->vexreg & 15) << 3) |
1652 (1 << 2) | (ins->vex_wlp & 3);
1653 bytes[3] = ins->evex_p[2];
1654 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1655 offset += 4;
1656 break;
1657
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001658 case4(0260):
1659 case 0270:
1660 codes += 2;
H. Peter Anvin621a69a2013-11-28 12:11:24 -08001661 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1662 ins->prefixes[PPS_VEX] == P_VEX3) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001663 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1664 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1665 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
H. Peter Anvinfc561202011-07-07 16:58:22 -07001666 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001667 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1668 offset += 3;
1669 } else {
1670 bytes[0] = 0xc5;
1671 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
H. Peter Anvinfc561202011-07-07 16:58:22 -07001672 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001673 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1674 offset += 2;
1675 }
1676 break;
H. Peter Anvind85d2502008-05-04 17:53:31 -07001677
H. Peter Anvine014f352012-02-25 22:35:19 -08001678 case 0271:
1679 case 0272:
1680 case 0273:
H. Peter Anvin8ea22002012-02-25 10:24:24 -08001681 break;
1682
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001683 case4(0274):
1684 {
1685 uint64_t uv, um;
1686 int s;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001687
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001688 if (ins->rex & REX_W)
1689 s = 64;
1690 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1691 s = 16;
1692 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1693 s = 32;
1694 else
1695 s = bits;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001696
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001697 um = (uint64_t)2 << (s-1);
1698 uv = opx->offset;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001699
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001700 if (uv > 127 && uv < (uint64_t)-128 &&
1701 (uv < um-128 || uv > um-1)) {
Ben Rudiak-Gould4e8396b2013-03-01 10:28:32 +04001702 /* If this wasn't explicitly byte-sized, warn as though we
1703 * had fallen through to the imm16/32/64 case.
1704 */
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001705 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
Ben Rudiak-Gould4e8396b2013-03-01 10:28:32 +04001706 "%s value exceeds bounds",
1707 (opx->type & BITS8) ? "signed byte" :
1708 s == 16 ? "word" :
1709 s == 32 ? "dword" :
1710 "signed dword");
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001711 }
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001712 if (opx->segment != NO_SEG) {
H. Peter Anvin779ed8b2008-10-16 13:01:43 -07001713 data = uv;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001714 out(offset, segment, &data, OUT_ADDRESS, 1,
1715 opx->segment, opx->wrt);
1716 } else {
H. Peter Anvin779ed8b2008-10-16 13:01:43 -07001717 bytes[0] = uv;
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001718 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1719 NO_SEG);
1720 }
1721 offset += 1;
1722 break;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001723 }
H. Peter Anvinc1377e92008-10-06 23:40:31 -07001724
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001725 case4(0300):
H. Peter Anvine2c80182005-01-15 22:15:51 +00001726 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001727
H. Peter Anvine2c80182005-01-15 22:15:51 +00001728 case 0310:
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07001729 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001730 *bytes = 0x67;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001731 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001732 offset += 1;
1733 } else
1734 offset += 0;
1735 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001736
H. Peter Anvine2c80182005-01-15 22:15:51 +00001737 case 0311:
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07001738 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001739 *bytes = 0x67;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001740 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001741 offset += 1;
1742 } else
1743 offset += 0;
1744 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001745
H. Peter Anvine2c80182005-01-15 22:15:51 +00001746 case 0312:
1747 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001748
Keith Kaniosb7a89542007-04-12 02:40:54 +00001749 case 0313:
1750 ins->rex = 0;
1751 break;
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -07001752
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001753 case4(0314):
1754 break;
H. Peter Anvin23440102007-11-12 21:02:33 -08001755
H. Peter Anvine2c80182005-01-15 22:15:51 +00001756 case 0320:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001757 case 0321:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001758 break;
H. Peter Anvinef7468f2002-04-30 20:57:59 +00001759
H. Peter Anvine2c80182005-01-15 22:15:51 +00001760 case 0322:
H. Peter Anvin70653092007-10-19 14:42:29 -07001761 case 0323:
1762 break;
1763
Keith Kaniosb7a89542007-04-12 02:40:54 +00001764 case 0324:
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001765 ins->rex |= REX_W;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001766 break;
H. Peter Anvin70653092007-10-19 14:42:29 -07001767
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001768 case 0325:
1769 break;
H. Peter Anvin9472dab2009-06-24 21:38:29 -07001770
Ben Rudiak-Gouldd7ab1f92013-02-20 23:25:54 +04001771 case 0326:
1772 break;
1773
H. Peter Anvine2c80182005-01-15 22:15:51 +00001774 case 0330:
Cyrill Gorcunov83e69242013-03-03 14:34:31 +04001775 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001776 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001777 offset += 1;
1778 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001779
H. Peter Anvine2c80182005-01-15 22:15:51 +00001780 case 0331:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001781 break;
H. Peter Anvinaf535c12002-04-30 20:59:21 +00001782
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001783 case 0332:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001784 case 0333:
H. Peter Anvincb9b6902007-09-12 21:58:51 -07001785 *bytes = c - 0332 + 0xF2;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001786 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001787 offset += 1;
1788 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001789
Keith Kanios48af1772007-08-17 07:37:52 +00001790 case 0334:
1791 if (ins->rex & REX_R) {
1792 *bytes = 0xF0;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001793 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
Keith Kanios48af1772007-08-17 07:37:52 +00001794 offset += 1;
1795 }
1796 ins->rex &= ~(REX_L|REX_R);
1797 break;
H. Peter Anvin0db11e22007-04-17 20:23:11 +00001798
H. Peter Anvincb9b6902007-09-12 21:58:51 -07001799 case 0335:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001800 break;
H. Peter Anvincb9b6902007-09-12 21:58:51 -07001801
H. Peter Anvin962e3052008-08-28 17:47:16 -07001802 case 0336:
1803 case 0337:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001804 break;
H. Peter Anvin962e3052008-08-28 17:47:16 -07001805
H. Peter Anvine2c80182005-01-15 22:15:51 +00001806 case 0340:
H. Peter Anvine2c80182005-01-15 22:15:51 +00001807 if (ins->oprs[0].segment != NO_SEG)
1808 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1809 else {
H. Peter Anvin428fd672007-11-15 10:25:52 -08001810 int64_t size = ins->oprs[0].offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001811 if (size > 0)
1812 out(offset, segment, NULL,
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001813 OUT_RESERVE, size, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001814 offset += size;
1815 }
1816 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001817
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001818 case 0341:
1819 break;
H. Peter Anvinc2acf7b2009-02-21 18:22:56 -08001820
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001821 case 0360:
1822 break;
H. Peter Anvinfff5a472008-05-20 09:46:24 -07001823
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001824 case 0361:
1825 bytes[0] = 0x66;
H. Peter Anvinfff5a472008-05-20 09:46:24 -07001826 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1827 offset += 1;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001828 break;
H. Peter Anvinfff5a472008-05-20 09:46:24 -07001829
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001830 case 0364:
1831 case 0365:
1832 break;
H. Peter Anvin62cb6062007-09-11 22:44:03 +00001833
Keith Kanios48af1772007-08-17 07:37:52 +00001834 case 0366:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001835 case 0367:
H. Peter Anvin62cb6062007-09-11 22:44:03 +00001836 *bytes = c - 0366 + 0x66;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001837 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
Keith Kanios48af1772007-08-17 07:37:52 +00001838 offset += 1;
1839 break;
H. Peter Anvin62cb6062007-09-11 22:44:03 +00001840
Jin Kyu Song03041092013-10-15 19:38:51 -07001841 case3(0370):
H. Peter Anvine2c80182005-01-15 22:15:51 +00001842 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001843
H. Peter Anvine2c80182005-01-15 22:15:51 +00001844 case 0373:
1845 *bytes = bits == 16 ? 3 : 5;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001846 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001847 offset += 1;
1848 break;
H. Peter Anvineba20a72002-04-30 20:53:55 +00001849
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07001850 case 0374:
1851 eat = EA_XMMVSIB;
1852 break;
1853
1854 case 0375:
1855 eat = EA_YMMVSIB;
1856 break;
1857
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001858 case 0376:
1859 eat = EA_ZMMVSIB;
1860 break;
1861
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001862 case4(0100):
1863 case4(0110):
1864 case4(0120):
1865 case4(0130):
1866 case4(0200):
1867 case4(0204):
1868 case4(0210):
1869 case4(0214):
1870 case4(0220):
1871 case4(0224):
1872 case4(0230):
1873 case4(0234):
1874 {
H. Peter Anvine2c80182005-01-15 22:15:51 +00001875 ea ea_data;
1876 int rfield;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001877 opflags_t rflags;
Keith Kaniosb7a89542007-04-12 02:40:54 +00001878 uint8_t *p;
1879 int32_t s;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001880 struct operand *opy = &ins->oprs[op2];
H. Peter Anvin70653092007-10-19 14:42:29 -07001881
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001882 if (c <= 0177) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001883 /* pick rfield from operand b (opx) */
1884 rflags = regflag(opx);
H. Peter Anvin33d5fc02008-10-23 23:07:53 -07001885 rfield = nasm_regvals[opx->basereg];
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001886 } else {
1887 /* rfield is constant */
1888 rflags = 0;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001889 rfield = c & 7;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001890 }
H. Peter Anvine2c80182005-01-15 22:15:51 +00001891
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001892 if (process_ea(opy, &ea_data, bits,
1893 rfield, rflags, ins) != eat)
H. Peter Anvine2c80182005-01-15 22:15:51 +00001894 errfunc(ERR_NONFATAL, "invalid effective address");
Charles Crayne7e975552007-11-03 22:06:13 -07001895
H. Peter Anvine2c80182005-01-15 22:15:51 +00001896 p = bytes;
1897 *p++ = ea_data.modrm;
1898 if (ea_data.sib_present)
1899 *p++ = ea_data.sib;
1900
1901 s = p - bytes;
H. Peter Anvin34f6fb02007-11-09 14:44:02 -08001902 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
H. Peter Anvine2c80182005-01-15 22:15:51 +00001903
Victor van den Elzencf9332c2008-10-01 12:18:28 +02001904 /*
1905 * Make sure the address gets the right offset in case
1906 * the line breaks in the .lst file (BR 1197827)
1907 */
1908 offset += s;
1909 s = 0;
1910
H. Peter Anvin72bf3fe2013-11-26 20:19:53 -08001911 if (ea_data.bytes) {
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001912 /* use compressed displacement, if available */
1913 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001914 s += ea_data.bytes;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001915 if (ea_data.rip) {
1916 if (opy->segment == segment) {
1917 data -= insn_end;
Victor van den Elzen0d268fb2010-01-24 21:24:57 +01001918 if (overflow_signed(data, ea_data.bytes))
1919 warn_overflow(ERR_PASS2, ea_data.bytes);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001920 out(offset, segment, &data, OUT_ADDRESS,
1921 ea_data.bytes, NO_SEG, NO_SEG);
1922 } else {
Victor van den Elzen0d268fb2010-01-24 21:24:57 +01001923 /* overflow check in output/linker? */
H. Peter Anvin89a2ac02013-11-26 18:23:20 -08001924 out(offset, segment, &data, OUT_REL4ADR,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001925 insn_end - offset, opy->segment, opy->wrt);
1926 }
1927 } else {
H. Peter Anvin72bf3fe2013-11-26 20:19:53 -08001928 int asize = ins->addr_size >> 3;
1929 int atype = ea_data.bytes;
1930
1931 if (overflow_general(data, asize) ||
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07001932 signed_bits(data, ins->addr_size) !=
H. Peter Anvin72bf3fe2013-11-26 20:19:53 -08001933 signed_bits(data, ea_data.bytes << 3))
Victor van den Elzen0d268fb2010-01-24 21:24:57 +01001934 warn_overflow(ERR_PASS2, ea_data.bytes);
1935
H. Peter Anvin72bf3fe2013-11-26 20:19:53 -08001936 if (asize > ea_data.bytes) {
1937 /*
1938 * If the address isn't the full width of
1939 * the address size, treat is as signed...
1940 */
1941 atype = -atype;
1942 }
1943
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001944 out(offset, segment, &data, OUT_ADDRESS,
H. Peter Anvin72bf3fe2013-11-26 20:19:53 -08001945 atype, opy->segment, opy->wrt);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001946 }
H. Peter Anvine2c80182005-01-15 22:15:51 +00001947 }
1948 offset += s;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001949 }
1950 break;
H. Peter Anvin507ae032008-10-09 15:37:10 -07001951
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001952 default:
1953 errfunc(ERR_PANIC, "internal instruction table corrupt"
1954 ": instruction code \\%o (0x%02X) given", c, c);
1955 break;
H. Peter Anvine2c80182005-01-15 22:15:51 +00001956 }
H. Peter Anvin839eca22007-10-29 23:12:47 -07001957 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00001958}
1959
H. Peter Anvinf8563f72009-10-13 12:28:14 -07001960static opflags_t regflag(const operand * o)
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001961{
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04001962 if (!is_register(o->basereg))
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001963 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
H. Peter Anvina4835d42008-05-20 14:21:29 -07001964 return nasm_reg_flags[o->basereg];
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001965}
1966
H. Peter Anvin5b0e3ec2007-07-07 02:01:08 +00001967static int32_t regval(const operand * o)
H. Peter Anvineba20a72002-04-30 20:53:55 +00001968{
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04001969 if (!is_register(o->basereg))
H. Peter Anvine2c80182005-01-15 22:15:51 +00001970 errfunc(ERR_PANIC, "invalid operand passed to regval()");
H. Peter Anvina4835d42008-05-20 14:21:29 -07001971 return nasm_regvals[o->basereg];
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00001972}
1973
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001974static int op_rexflags(const operand * o, int mask)
1975{
H. Peter Anvinf8563f72009-10-13 12:28:14 -07001976 opflags_t flags;
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001977 int val;
1978
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04001979 if (!is_register(o->basereg))
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001980 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001981
H. Peter Anvina4835d42008-05-20 14:21:29 -07001982 flags = nasm_reg_flags[o->basereg];
1983 val = nasm_regvals[o->basereg];
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001984
1985 return rexflags(val, flags, mask);
1986}
1987
H. Peter Anvinf8563f72009-10-13 12:28:14 -07001988static int rexflags(int val, opflags_t flags, int mask)
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001989{
1990 int rex = 0;
1991
H. Peter Anvinc6c750c2013-11-08 15:28:19 -08001992 if (val >= 0 && (val & 8))
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001993 rex |= REX_B|REX_X|REX_R;
H. Peter Anvin3df97a72007-05-30 03:25:21 +00001994 if (flags & BITS64)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04001995 rex |= REX_W;
1996 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1997 rex |= REX_H;
1998 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1999 rex |= REX_P;
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002000
2001 return rex & mask;
2002}
2003
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002004static int evexflags(int val, decoflags_t deco,
2005 int mask, uint8_t byte)
2006{
2007 int evex = 0;
2008
Jin Kyu Song1be09ee2013-11-08 01:14:39 -08002009 switch (byte) {
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002010 case 0:
H. Peter Anvinc6c750c2013-11-08 15:28:19 -08002011 if (val >= 0 && (val & 16))
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002012 evex |= (EVEX_P0RP | EVEX_P0X);
2013 break;
2014 case 2:
H. Peter Anvinc6c750c2013-11-08 15:28:19 -08002015 if (val >= 0 && (val & 16))
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002016 evex |= EVEX_P2VP;
2017 if (deco & Z)
2018 evex |= EVEX_P2Z;
2019 if (deco & OPMASK_MASK)
2020 evex |= deco & EVEX_P2AAA;
2021 break;
2022 }
2023 return evex & mask;
2024}
2025
2026static int op_evexflags(const operand * o, int mask, uint8_t byte)
2027{
2028 int val;
2029
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002030 val = nasm_regvals[o->basereg];
2031
2032 return evexflags(val, o->decoflags, mask, byte);
2033}
2034
H. Peter Anvin23595f52009-07-25 17:44:25 -07002035static enum match_result find_match(const struct itemplate **tempp,
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002036 insn *instruction,
2037 int32_t segment, int64_t offset, int bits)
H. Peter Anvin23595f52009-07-25 17:44:25 -07002038{
2039 const struct itemplate *temp;
2040 enum match_result m, merr;
H. Peter Anvina7643f42009-10-13 12:32:20 -07002041 opflags_t xsizeflags[MAX_OPERANDS];
H. Peter Anvina81655b2009-07-25 18:15:28 -07002042 bool opsizemissing = false;
Jin Kyu Songe3a06b92013-08-28 19:15:23 -07002043 int8_t broadcast = instruction->evex_brerop;
H. Peter Anvina81655b2009-07-25 18:15:28 -07002044 int i;
2045
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002046 /* broadcasting uses a different data element size */
2047 for (i = 0; i < instruction->operands; i++)
2048 if (i == broadcast)
2049 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2050 else
2051 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
H. Peter Anvin23595f52009-07-25 17:44:25 -07002052
2053 merr = MERR_INVALOP;
2054
2055 for (temp = nasm_instructions[instruction->opcode];
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002056 temp->opcode != I_none; temp++) {
2057 m = matches(temp, instruction, bits);
2058 if (m == MOK_JUMP) {
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -08002059 if (jmp_match(segment, offset, bits, instruction, temp))
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002060 m = MOK_GOOD;
2061 else
2062 m = MERR_INVALOP;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002063 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002064 /*
2065 * Missing operand size and a candidate for fuzzy matching...
2066 */
Ben Rudiak-Gould6e878932013-02-27 10:13:14 -08002067 for (i = 0; i < temp->operands; i++)
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002068 if (i == broadcast)
2069 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2070 else
2071 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002072 opsizemissing = true;
2073 }
2074 if (m > merr)
2075 merr = m;
2076 if (merr == MOK_GOOD)
2077 goto done;
H. Peter Anvina81655b2009-07-25 18:15:28 -07002078 }
2079
2080 /* No match, but see if we can get a fuzzy operand size match... */
2081 if (!opsizemissing)
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002082 goto done;
H. Peter Anvina81655b2009-07-25 18:15:28 -07002083
2084 for (i = 0; i < instruction->operands; i++) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002085 /*
2086 * We ignore extrinsic operand sizes on registers, so we should
2087 * never try to fuzzy-match on them. This also resolves the case
2088 * when we have e.g. "xmmrm128" in two different positions.
2089 */
2090 if (is_class(REGISTER, instruction->oprs[i].type))
2091 continue;
H. Peter Anvinff5d6562009-10-05 14:08:05 -07002092
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002093 /* This tests if xsizeflags[i] has more than one bit set */
2094 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2095 goto done; /* No luck */
H. Peter Anvina81655b2009-07-25 18:15:28 -07002096
Jin Kyu Song7903c072013-10-30 03:00:12 -07002097 if (i == broadcast) {
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002098 instruction->oprs[i].decoflags |= xsizeflags[i];
Jin Kyu Song7903c072013-10-30 03:00:12 -07002099 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2100 BITS32 : BITS64);
2101 } else {
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002102 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
Jin Kyu Song7903c072013-10-30 03:00:12 -07002103 }
H. Peter Anvina81655b2009-07-25 18:15:28 -07002104 }
2105
2106 /* Try matching again... */
2107 for (temp = nasm_instructions[instruction->opcode];
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002108 temp->opcode != I_none; temp++) {
2109 m = matches(temp, instruction, bits);
2110 if (m == MOK_JUMP) {
H. Peter Anvin8cc8a1d2012-02-25 11:11:42 -08002111 if (jmp_match(segment, offset, bits, instruction, temp))
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002112 m = MOK_GOOD;
2113 else
2114 m = MERR_INVALOP;
2115 }
2116 if (m > merr)
2117 merr = m;
2118 if (merr == MOK_GOOD)
2119 goto done;
H. Peter Anvin23595f52009-07-25 17:44:25 -07002120 }
2121
H. Peter Anvina81655b2009-07-25 18:15:28 -07002122done:
H. Peter Anvin23595f52009-07-25 17:44:25 -07002123 *tempp = temp;
2124 return merr;
2125}
2126
Mark Charneydcaef4b2014-10-09 13:45:17 -04002127static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2128{
2129 opflags_t opsize = opflags & SIZE_MASK;
2130 uint8_t brcast_num;
2131
2132 /*
2133 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2134 * this cannot be a simple arithmetic calculation.
2135 */
2136 if (brsize > BITS64)
2137 errfunc(ERR_FATAL,
2138 "size of broadcasting element is greater than 64 bits");
2139
2140 switch (opsize) {
2141 case BITS64:
2142 brcast_num = BITS64 / brsize;
2143 break;
2144 default:
2145 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2146 break;
2147 }
2148
2149 return brcast_num;
2150}
2151
H. Peter Anvin65289e82009-07-25 17:25:11 -07002152static enum match_result matches(const struct itemplate *itemp,
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002153 insn *instruction, int bits)
H. Peter Anvineba20a72002-04-30 20:53:55 +00002154{
Cyrill Gorcunov167917a2012-09-10 00:19:12 +04002155 opflags_t size[MAX_OPERANDS], asize;
H. Peter Anvin3fb86f22009-07-25 19:12:10 -07002156 bool opsizemissing = false;
Cyrill Gorcunov167917a2012-09-10 00:19:12 +04002157 int i, oprs;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002158
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002159 /*
2160 * Check the opcode
2161 */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002162 if (itemp->opcode != instruction->opcode)
H. Peter Anvin65289e82009-07-25 17:25:11 -07002163 return MERR_INVALOP;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002164
2165 /*
2166 * Count the operands
2167 */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002168 if (itemp->operands != instruction->operands)
H. Peter Anvin65289e82009-07-25 17:25:11 -07002169 return MERR_INVALOP;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002170
2171 /*
H. Peter Anvin47fb7bc2010-08-24 13:53:22 -07002172 * Is it legal?
2173 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002174 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
H. Peter Anvin47fb7bc2010-08-24 13:53:22 -07002175 return MERR_INVALOP;
2176
2177 /*
Jin Kyu Song6cfa9682013-11-26 17:27:48 -08002178 * {evex} available?
2179 */
H. Peter Anvin621a69a2013-11-28 12:11:24 -08002180 switch (instruction->prefixes[PPS_VEX]) {
2181 case P_EVEX:
2182 if (!itemp_has(itemp, IF_EVEX))
2183 return MERR_ENCMISMATCH;
2184 break;
2185 case P_VEX3:
2186 case P_VEX2:
2187 if (!itemp_has(itemp, IF_VEX))
2188 return MERR_ENCMISMATCH;
2189 break;
2190 default:
2191 break;
Jin Kyu Song6cfa9682013-11-26 17:27:48 -08002192 }
2193
2194 /*
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002195 * Check that no spurious colons or TOs are present
2196 */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002197 for (i = 0; i < itemp->operands; i++)
2198 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
H. Peter Anvin65289e82009-07-25 17:25:11 -07002199 return MERR_INVALOP;
H. Peter Anvin70653092007-10-19 14:42:29 -07002200
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002201 /*
H. Peter Anvin32cd4c22008-04-04 13:34:53 -07002202 * Process size flags
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002203 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002204 switch (itemp_smask(itemp)) {
2205 case IF_GENBIT(IF_SB):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002206 asize = BITS8;
2207 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002208 case IF_GENBIT(IF_SW):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002209 asize = BITS16;
2210 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002211 case IF_GENBIT(IF_SD):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002212 asize = BITS32;
2213 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002214 case IF_GENBIT(IF_SQ):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002215 asize = BITS64;
2216 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002217 case IF_GENBIT(IF_SO):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002218 asize = BITS128;
2219 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002220 case IF_GENBIT(IF_SY):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002221 asize = BITS256;
2222 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002223 case IF_GENBIT(IF_SZ):
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002224 asize = BITS512;
2225 break;
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002226 case IF_GENBIT(IF_SIZE):
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002227 switch (bits) {
2228 case 16:
2229 asize = BITS16;
2230 break;
2231 case 32:
2232 asize = BITS32;
2233 break;
2234 case 64:
2235 asize = BITS64;
2236 break;
2237 default:
2238 asize = 0;
2239 break;
2240 }
2241 break;
H. Peter Anvin60926242009-07-26 16:25:38 -07002242 default:
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002243 asize = 0;
2244 break;
H. Peter Anvin60926242009-07-26 16:25:38 -07002245 }
2246
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002247 if (itemp_armask(itemp)) {
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002248 /* S- flags only apply to a specific operand */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002249 i = itemp_arg(itemp);
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002250 memset(size, 0, sizeof size);
2251 size[i] = asize;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002252 } else {
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002253 /* S- flags apply to all operands */
2254 for (i = 0; i < MAX_OPERANDS; i++)
2255 size[i] = asize;
H. Peter Anvinef7468f2002-04-30 20:57:59 +00002256 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002257
H. Peter Anvin32cd4c22008-04-04 13:34:53 -07002258 /*
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002259 * Check that the operand flags all match up,
2260 * it's a bit tricky so lets be verbose:
2261 *
2262 * 1) Find out the size of operand. If instruction
2263 * doesn't have one specified -- we're trying to
2264 * guess it either from template (IF_S* flag) or
2265 * from code bits.
2266 *
Ben Rudiak-Gould6e878932013-02-27 10:13:14 -08002267 * 2) If template operand do not match the instruction OR
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002268 * template has an operand size specified AND this size differ
2269 * from which instruction has (perhaps we got it from code bits)
2270 * we are:
2271 * a) Check that only size of instruction and operand is differ
2272 * other characteristics do match
2273 * b) Perhaps it's a register specified in instruction so
2274 * for such a case we just mark that operand as "size
2275 * missing" and this will turn on fuzzy operand size
2276 * logic facility (handled by a caller)
H. Peter Anvin32cd4c22008-04-04 13:34:53 -07002277 */
2278 for (i = 0; i < itemp->operands; i++) {
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002279 opflags_t type = instruction->oprs[i].type;
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002280 decoflags_t deco = instruction->oprs[i].decoflags;
Jin Kyu Song7903c072013-10-30 03:00:12 -07002281 bool is_broadcast = deco & BRDCAST_MASK;
Jin Kyu Song25c22122013-10-30 03:12:45 -07002282 uint8_t brcast_num = 0;
Jin Kyu Song7903c072013-10-30 03:00:12 -07002283 opflags_t template_opsize, insn_opsize;
2284
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002285 if (!(type & SIZE_MASK))
2286 type |= size[i];
H. Peter Anvind85d2502008-05-04 17:53:31 -07002287
Jin Kyu Song7903c072013-10-30 03:00:12 -07002288 insn_opsize = type & SIZE_MASK;
2289 if (!is_broadcast) {
2290 template_opsize = itemp->opd[i] & SIZE_MASK;
2291 } else {
2292 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2293 /*
2294 * when broadcasting, the element size depends on
2295 * the instruction type. decorator flag should match.
2296 */
2297
2298 if (deco_brsize) {
2299 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
Jin Kyu Song25c22122013-10-30 03:12:45 -07002300 /* calculate the proper number : {1to<brcast_num>} */
Mark Charneydcaef4b2014-10-09 13:45:17 -04002301 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
Jin Kyu Song7903c072013-10-30 03:00:12 -07002302 } else {
2303 template_opsize = 0;
2304 }
2305 }
2306
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002307 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
Jin Kyu Song25c22122013-10-30 03:12:45 -07002308 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
Ben Rudiak-Gould4e8396b2013-03-01 10:28:32 +04002309 return MERR_INVALOP;
Jin Kyu Song7903c072013-10-30 03:00:12 -07002310 } else if (template_opsize) {
2311 if (template_opsize != insn_opsize) {
2312 if (insn_opsize) {
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002313 return MERR_INVALOP;
Jin Kyu Song7903c072013-10-30 03:00:12 -07002314 } else if (!is_class(REGISTER, type)) {
2315 /*
2316 * Note: we don't honor extrinsic operand sizes for registers,
2317 * so "missing operand size" for a register should be
2318 * considered a wildcard match rather than an error.
2319 */
2320 opsizemissing = true;
Jin Kyu Song4d1fc3f2013-08-21 19:29:10 -07002321 }
Jin Kyu Song25c22122013-10-30 03:12:45 -07002322 } else if (is_broadcast &&
2323 (brcast_num !=
Mark Charneydcaef4b2014-10-09 13:45:17 -04002324 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
Jin Kyu Song25c22122013-10-30 03:12:45 -07002325 /*
2326 * broadcasting opsize matches but the number of repeated memory
2327 * element does not match.
Mark Charneydcaef4b2014-10-09 13:45:17 -04002328 * if 64b double precision float is broadcasted to ymm (256b),
2329 * broadcasting decorator must be {1to4}.
Jin Kyu Song25c22122013-10-30 03:12:45 -07002330 */
2331 return MERR_BRNUMMISMATCH;
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002332 }
H. Peter Anvin32cd4c22008-04-04 13:34:53 -07002333 }
2334 }
2335
H. Peter Anvin3fb86f22009-07-25 19:12:10 -07002336 if (opsizemissing)
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002337 return MERR_OPSIZEMISSING;
H. Peter Anvin3fb86f22009-07-25 19:12:10 -07002338
H. Peter Anvin32cd4c22008-04-04 13:34:53 -07002339 /*
2340 * Check operand sizes
2341 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002342 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2343 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
H. Peter Anvine2c80182005-01-15 22:15:51 +00002344 for (i = 0; i < oprs; i++) {
Cyrill Gorcunovbc31bee2009-11-01 23:16:01 +03002345 asize = itemp->opd[i] & SIZE_MASK;
2346 if (asize) {
2347 for (i = 0; i < oprs; i++)
2348 size[i] = asize;
H. Peter Anvine2c80182005-01-15 22:15:51 +00002349 break;
2350 }
2351 }
H. Peter Anvinef7468f2002-04-30 20:57:59 +00002352 } else {
H. Peter Anvine2c80182005-01-15 22:15:51 +00002353 oprs = itemp->operands;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002354 }
2355
Keith Kaniosb7a89542007-04-12 02:40:54 +00002356 for (i = 0; i < itemp->operands; i++) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00002357 if (!(itemp->opd[i] & SIZE_MASK) &&
2358 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
H. Peter Anvin65289e82009-07-25 17:25:11 -07002359 return MERR_OPSIZEMISMATCH;
Keith Kaniosb7a89542007-04-12 02:40:54 +00002360 }
2361
H. Peter Anvinaf535c12002-04-30 20:59:21 +00002362 /*
2363 * Check template is okay at the set cpu level
2364 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002365 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
H. Peter Anvin65289e82009-07-25 17:25:11 -07002366 return MERR_BADCPU;
H. Peter Anvin70653092007-10-19 14:42:29 -07002367
Keith Kaniosb7a89542007-04-12 02:40:54 +00002368 /*
H. Peter Anvin6cda4142008-12-29 20:52:28 -08002369 * Verify the appropriate long mode flag.
Keith Kaniosb7a89542007-04-12 02:40:54 +00002370 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002371 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
H. Peter Anvin65289e82009-07-25 17:25:11 -07002372 return MERR_BADMODE;
H. Peter Anvine2c80182005-01-15 22:15:51 +00002373
H. Peter Anvinaf535c12002-04-30 20:59:21 +00002374 /*
H. Peter Anvinfb3f4e62012-02-25 22:22:07 -08002375 * If we have a HLE prefix, look for the NOHLE flag
2376 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002377 if (itemp_has(itemp, IF_NOHLE) &&
H. Peter Anvinfb3f4e62012-02-25 22:22:07 -08002378 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2379 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2380 return MERR_BADHLE;
2381
2382 /*
H. Peter Anvinaf535c12002-04-30 20:59:21 +00002383 * Check if special handling needed for Jumps
2384 */
H. Peter Anvin755f5212012-02-25 11:41:34 -08002385 if ((itemp->code[0] & ~1) == 0370)
Cyrill Gorcunov1de95002009-11-06 00:08:38 +03002386 return MOK_JUMP;
H. Peter Anvine2c80182005-01-15 22:15:51 +00002387
Jin Kyu Song03041092013-10-15 19:38:51 -07002388 /*
Jin Kyu Songb287ff02013-12-04 20:05:55 -08002389 * Check if BND prefix is allowed.
2390 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
Jin Kyu Song03041092013-10-15 19:38:51 -07002391 */
Cyrill Gorcunov08359152013-11-09 22:16:11 +04002392 if (!itemp_has(itemp, IF_BND) &&
Jin Kyu Songb287ff02013-12-04 20:05:55 -08002393 (has_prefix(instruction, PPS_REP, P_BND) ||
2394 has_prefix(instruction, PPS_REP, P_NOBND)))
Jin Kyu Song03041092013-10-15 19:38:51 -07002395 return MERR_BADBND;
Jin Kyu Songb287ff02013-12-04 20:05:55 -08002396 else if (itemp_has(itemp, IF_BND) &&
2397 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2398 has_prefix(instruction, PPS_REP, P_REPNZ)))
2399 return MERR_BADREPNE;
Jin Kyu Song03041092013-10-15 19:38:51 -07002400
H. Peter Anvin60926242009-07-26 16:25:38 -07002401 return MOK_GOOD;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002402}
2403
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002404/*
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002405 * Check if ModR/M.mod should/can be 01.
2406 * - EAF_BYTEOFFS is set
2407 * - offset can fit in a byte when EVEX is not used
2408 * - offset can be compressed when EVEX is used
2409 */
2410#define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2411 (o >= -128 && o <= 127 && \
2412 seg == NO_SEG && !forw_ref && \
2413 !(input->eaflags & EAF_WORDOFFS) && \
2414 !(ins->rex & REX_EV)) || \
2415 (ins->rex & REX_EV && \
2416 is_disp8n(input, ins, &output->disp8)))
2417
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002418static enum ea_type process_ea(operand *input, ea *output, int bits,
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002419 int rfield, opflags_t rflags, insn *ins)
H. Peter Anvineba20a72002-04-30 20:53:55 +00002420{
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002421 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002422 int addrbits = ins->addr_size;
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002423 int eaflags = input->eaflags;
H. Peter Anvin1c3277b2008-07-19 21:38:56 -07002424
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002425 output->type = EA_SCALAR;
2426 output->rip = false;
Jin Kyu Songdb358a22013-09-20 20:36:19 -07002427 output->disp8 = 0;
H. Peter Anvin99c4ecd2007-08-28 23:06:00 +00002428
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002429 /* REX flags for the rfield operand */
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002430 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002431 /* EVEX.R' flag for the REG operand */
2432 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002433
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002434 if (is_class(REGISTER, input->type)) {
2435 /*
2436 * It's a direct register.
2437 */
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04002438 if (!is_register(input->basereg))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002439 goto err;
Keith Kaniosb7a89542007-04-12 02:40:54 +00002440
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002441 if (!is_reg_class(REG_EA, input->basereg))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002442 goto err;
H. Peter Anvin70653092007-10-19 14:42:29 -07002443
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002444 /* broadcasting is not available with a direct register operand. */
2445 if (input->decoflags & BRDCAST_MASK) {
2446 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2447 goto err;
2448 }
2449
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002450 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002451 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002452 output->sib_present = false; /* no SIB necessary */
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002453 output->bytes = 0; /* no offset necessary either */
2454 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2455 } else {
2456 /*
2457 * It's a memory reference.
2458 */
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002459
2460 /* Embedded rounding or SAE is not available with a mem ref operand. */
2461 if (input->decoflags & (ER | SAE)) {
2462 nasm_error(ERR_NONFATAL,
2463 "Embedded rounding is available only with reg-reg op.");
2464 return -1;
2465 }
2466
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002467 if (input->basereg == -1 &&
2468 (input->indexreg == -1 || input->scale == 0)) {
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002469 /*
2470 * It's a pure offset.
2471 */
Victor van den Elzen0d268fb2010-01-24 21:24:57 +01002472 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2473 input->segment == NO_SEG) {
2474 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2475 input->type &= ~IP_REL;
2476 input->type |= MEMORY;
2477 }
2478
Jin Kyu Song97f6fae2013-12-18 21:28:17 -08002479 if (bits == 64 &&
2480 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2481 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2482 return -1;
2483 }
2484
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002485 if (eaflags & EAF_BYTEOFFS ||
2486 (eaflags & EAF_WORDOFFS &&
Victor van den Elzen0d268fb2010-01-24 21:24:57 +01002487 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2488 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2489 }
2490
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002491 if (bits == 64 && (~input->type & IP_REL)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002492 output->sib_present = true;
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002493 output->sib = GEN_SIB(0, 4, 5);
2494 output->bytes = 4;
2495 output->modrm = GEN_MODRM(0, rfield, 4);
2496 output->rip = false;
Chuck Crayne42fe6ce2007-06-03 02:42:41 +00002497 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002498 output->sib_present = false;
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002499 output->bytes = (addrbits != 16 ? 4 : 2);
2500 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2501 output->rip = bits == 64;
Chuck Crayne42fe6ce2007-06-03 02:42:41 +00002502 }
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002503 } else {
2504 /*
2505 * It's an indirection.
2506 */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002507 int i = input->indexreg, b = input->basereg, s = input->scale;
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002508 int32_t seg = input->segment;
H. Peter Anvine2c80182005-01-15 22:15:51 +00002509 int hb = input->hintbase, ht = input->hinttype;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002510 int t, it, bt; /* register numbers */
2511 opflags_t x, ix, bx; /* register flags */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002512
H. Peter Anvine2c80182005-01-15 22:15:51 +00002513 if (s == 0)
2514 i = -1; /* make this easy, at least */
H. Peter Anvin70653092007-10-19 14:42:29 -07002515
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04002516 if (is_register(i)) {
H. Peter Anvina4835d42008-05-20 14:21:29 -07002517 it = nasm_regvals[i];
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002518 ix = nasm_reg_flags[i];
2519 } else {
Keith Kaniosb7a89542007-04-12 02:40:54 +00002520 it = -1;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002521 ix = 0;
2522 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002523
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002524 if (is_register(b)) {
H. Peter Anvina4835d42008-05-20 14:21:29 -07002525 bt = nasm_regvals[b];
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002526 bx = nasm_reg_flags[b];
2527 } else {
Keith Kaniosb7a89542007-04-12 02:40:54 +00002528 bt = -1;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002529 bx = 0;
2530 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002531
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002532 /* if either one are a vector register... */
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002533 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
Cyrill Gorcunov167917a2012-09-10 00:19:12 +04002534 opflags_t sok = BITS32 | BITS64;
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002535 int32_t o = input->offset;
2536 int mod, scale, index, base;
2537
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002538 /*
2539 * For a vector SIB, one has to be a vector and the other,
2540 * if present, a GPR. The vector must be the index operand.
2541 */
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002542 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002543 if (s == 0)
2544 s = 1;
2545 else if (s != 1)
2546 goto err;
2547
2548 t = bt, bt = it, it = t;
2549 x = bx, bx = ix, ix = x;
2550 }
2551
2552 if (bt != -1) {
2553 if (REG_GPR & ~bx)
2554 goto err;
2555 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2556 sok &= bx;
2557 else
2558 goto err;
2559 }
2560
2561 /*
2562 * While we're here, ensure the user didn't specify
2563 * WORD or QWORD
2564 */
2565 if (input->disp_size == 16 || input->disp_size == 64)
2566 goto err;
2567
2568 if (addrbits == 16 ||
2569 (addrbits == 32 && !(sok & BITS32)) ||
2570 (addrbits == 64 && !(sok & BITS64)))
2571 goto err;
2572
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002573 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2574 : ((ix & YMMREG & ~REG_EA)
2575 ? EA_YMMVSIB : EA_XMMVSIB));
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002576
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002577 output->rex |= rexflags(it, ix, REX_X);
2578 output->rex |= rexflags(bt, bx, REX_B);
2579 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002580
2581 index = it & 7; /* it is known to be != -1 */
2582
2583 switch (s) {
2584 case 1:
2585 scale = 0;
2586 break;
2587 case 2:
2588 scale = 1;
2589 break;
2590 case 4:
2591 scale = 2;
2592 break;
2593 case 8:
2594 scale = 3;
2595 break;
2596 default: /* then what the smeg is it? */
2597 goto err; /* panic */
2598 }
2599
2600 if (bt == -1) {
2601 base = 5;
2602 mod = 0;
2603 } else {
2604 base = (bt & 7);
2605 if (base != REG_NUM_EBP && o == 0 &&
2606 seg == NO_SEG && !forw_ref &&
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002607 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002608 mod = 0;
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002609 else if (IS_MOD_01())
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002610 mod = 1;
2611 else
2612 mod = 2;
2613 }
2614
2615 output->sib_present = true;
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002616 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2617 output->modrm = GEN_MODRM(mod, rfield, 4);
2618 output->sib = GEN_SIB(scale, index, base);
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002619 } else if ((ix|bx) & (BITS32|BITS64)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002620 /*
2621 * it must be a 32/64-bit memory reference. Firstly we have
2622 * to check that all registers involved are type E/Rxx.
2623 */
Cyrill Gorcunov167917a2012-09-10 00:19:12 +04002624 opflags_t sok = BITS32 | BITS64;
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002625 int32_t o = input->offset;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002626
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002627 if (it != -1) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002628 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2629 sok &= ix;
2630 else
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002631 goto err;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002632 }
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002633
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002634 if (bt != -1) {
2635 if (REG_GPR & ~bx)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002636 goto err; /* Invalid register */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002637 if (~sok & bx & SIZE_MASK)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002638 goto err; /* Invalid size */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002639 sok &= bx;
2640 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002641
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002642 /*
2643 * While we're here, ensure the user didn't specify
2644 * WORD or QWORD
2645 */
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002646 if (input->disp_size == 16 || input->disp_size == 64)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002647 goto err;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002648
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002649 if (addrbits == 16 ||
2650 (addrbits == 32 && !(sok & BITS32)) ||
2651 (addrbits == 64 && !(sok & BITS64)))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002652 goto err;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002653
Keith Kaniosb7a89542007-04-12 02:40:54 +00002654 /* now reorganize base/index */
2655 if (s == 1 && bt != it && bt != -1 && it != -1 &&
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002656 ((hb == b && ht == EAH_NOTBASE) ||
2657 (hb == i && ht == EAH_MAKEBASE))) {
2658 /* swap if hints say so */
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002659 t = bt, bt = it, it = t;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002660 x = bx, bx = ix, ix = x;
2661 }
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002662
Jin Kyu Song164d6072013-10-15 19:10:13 -07002663 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002664 /* make single reg base, unless hint */
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002665 bt = it, bx = ix, it = -1, ix = 0;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002666 }
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002667 if (eaflags & EAF_MIB) {
2668 /* only for mib operands */
2669 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2670 /*
2671 * make a single reg index [reg*1].
2672 * gas uses this form for an explicit index register.
2673 */
2674 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2675 }
2676 if ((ht == EAH_SUMMED) && bt == -1) {
2677 /* separate once summed index into [base, index] */
2678 bt = it, bx = ix, s--;
2679 }
2680 } else {
2681 if (((s == 2 && it != REG_NUM_ESP &&
Jin Kyu Song3d06af22013-12-18 21:28:41 -08002682 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002683 s == 3 || s == 5 || s == 9) && bt == -1) {
2684 /* convert 3*EAX to EAX+2*EAX */
2685 bt = it, bx = ix, s--;
2686 }
2687 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
Jin Kyu Song26ddad62013-12-18 22:01:14 -08002688 (eaflags & EAF_TIMESTWO) &&
2689 (hb == b && ht == EAH_NOTBASE)) {
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002690 /*
Jin Kyu Song26ddad62013-12-18 22:01:14 -08002691 * convert [NOSPLIT EAX*1]
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002692 * to sib format with 0x0 displacement - [EAX*1+0].
2693 */
2694 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2695 }
2696 }
Keith Kanios48af1772007-08-17 07:37:52 +00002697 if (s == 1 && it == REG_NUM_ESP) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002698 /* swap ESP into base if scale is 1 */
Keith Kaniosb7a89542007-04-12 02:40:54 +00002699 t = it, it = bt, bt = t;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002700 x = ix, ix = bx, bx = x;
2701 }
2702 if (it == REG_NUM_ESP ||
2703 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002704 goto err; /* wrong, for various reasons */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002705
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002706 output->rex |= rexflags(it, ix, REX_X);
2707 output->rex |= rexflags(bt, bx, REX_B);
Keith Kaniosb7a89542007-04-12 02:40:54 +00002708
Keith Kanios48af1772007-08-17 07:37:52 +00002709 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002710 /* no SIB needed */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002711 int mod, rm;
H. Peter Anvin70653092007-10-19 14:42:29 -07002712
Keith Kaniosb7a89542007-04-12 02:40:54 +00002713 if (bt == -1) {
H. Peter Anvine2c80182005-01-15 22:15:51 +00002714 rm = 5;
H. Peter Anvine2c80182005-01-15 22:15:51 +00002715 mod = 0;
Keith Kaniosb7a89542007-04-12 02:40:54 +00002716 } else {
2717 rm = (bt & 7);
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002718 if (rm != REG_NUM_EBP && o == 0 &&
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002719 seg == NO_SEG && !forw_ref &&
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002720 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
Keith Kaniosb7a89542007-04-12 02:40:54 +00002721 mod = 0;
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002722 else if (IS_MOD_01())
Keith Kaniosb7a89542007-04-12 02:40:54 +00002723 mod = 1;
2724 else
2725 mod = 2;
2726 }
H. Peter Anvinea838272002-04-30 20:51:53 +00002727
H. Peter Anvin6867acc2007-10-10 14:58:45 -07002728 output->sib_present = false;
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002729 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2730 output->modrm = GEN_MODRM(mod, rfield, rm);
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002731 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002732 /* we need a SIB */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002733 int mod, scale, index, base;
H. Peter Anvin70653092007-10-19 14:42:29 -07002734
Keith Kaniosb7a89542007-04-12 02:40:54 +00002735 if (it == -1)
2736 index = 4, s = 1;
2737 else
2738 index = (it & 7);
H. Peter Anvin70653092007-10-19 14:42:29 -07002739
H. Peter Anvine2c80182005-01-15 22:15:51 +00002740 switch (s) {
2741 case 1:
2742 scale = 0;
2743 break;
2744 case 2:
2745 scale = 1;
2746 break;
2747 case 4:
2748 scale = 2;
2749 break;
2750 case 8:
2751 scale = 3;
2752 break;
2753 default: /* then what the smeg is it? */
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002754 goto err; /* panic */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002755 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002756
Keith Kaniosb7a89542007-04-12 02:40:54 +00002757 if (bt == -1) {
2758 base = 5;
2759 mod = 0;
2760 } else {
2761 base = (bt & 7);
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002762 if (base != REG_NUM_EBP && o == 0 &&
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002763 seg == NO_SEG && !forw_ref &&
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002764 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
Keith Kaniosb7a89542007-04-12 02:40:54 +00002765 mod = 0;
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002766 else if (IS_MOD_01())
Keith Kaniosb7a89542007-04-12 02:40:54 +00002767 mod = 1;
2768 else
2769 mod = 2;
2770 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002771
H. Peter Anvin6867acc2007-10-10 14:58:45 -07002772 output->sib_present = true;
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002773 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2774 output->modrm = GEN_MODRM(mod, rfield, 4);
2775 output->sib = GEN_SIB(scale, index, base);
H. Peter Anvine2c80182005-01-15 22:15:51 +00002776 }
2777 } else { /* it's 16-bit */
2778 int mod, rm;
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002779 int16_t o = input->offset;
H. Peter Anvin70653092007-10-19 14:42:29 -07002780
Keith Kaniosb7a89542007-04-12 02:40:54 +00002781 /* check for 64-bit long mode */
2782 if (addrbits == 64)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002783 goto err;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002784
H. Peter Anvine2c80182005-01-15 22:15:51 +00002785 /* check all registers are BX, BP, SI or DI */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002786 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2787 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002788 goto err;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002789
Keith Kaniosb7a89542007-04-12 02:40:54 +00002790 /* ensure the user didn't specify DWORD/QWORD */
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002791 if (input->disp_size == 32 || input->disp_size == 64)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002792 goto err;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002793
H. Peter Anvine2c80182005-01-15 22:15:51 +00002794 if (s != 1 && i != -1)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002795 goto err; /* no can do, in 16-bit EA */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002796 if (b == -1 && i != -1) {
2797 int tmp = b;
2798 b = i;
2799 i = tmp;
2800 } /* swap */
2801 if ((b == R_SI || b == R_DI) && i != -1) {
2802 int tmp = b;
2803 b = i;
2804 i = tmp;
2805 }
2806 /* have BX/BP as base, SI/DI index */
2807 if (b == i)
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002808 goto err; /* shouldn't ever happen, in theory */
H. Peter Anvine2c80182005-01-15 22:15:51 +00002809 if (i != -1 && b != -1 &&
2810 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002811 goto err; /* invalid combinations */
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002812 if (b == -1) /* pure offset: handled above */
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002813 goto err; /* so if it gets to here, panic! */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002814
H. Peter Anvine2c80182005-01-15 22:15:51 +00002815 rm = -1;
2816 if (i != -1)
2817 switch (i * 256 + b) {
2818 case R_SI * 256 + R_BX:
2819 rm = 0;
2820 break;
2821 case R_DI * 256 + R_BX:
2822 rm = 1;
2823 break;
2824 case R_SI * 256 + R_BP:
2825 rm = 2;
2826 break;
2827 case R_DI * 256 + R_BP:
2828 rm = 3;
2829 break;
2830 } else
2831 switch (b) {
2832 case R_SI:
2833 rm = 4;
2834 break;
2835 case R_DI:
2836 rm = 5;
2837 break;
2838 case R_BP:
2839 rm = 6;
2840 break;
2841 case R_BX:
2842 rm = 7;
2843 break;
2844 }
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002845 if (rm == -1) /* can't happen, in theory */
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002846 goto err; /* so panic if it does */
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002847
H. Peter Anvinab5bd052010-07-25 12:43:30 -07002848 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
Jin Kyu Song4360ba22013-12-10 16:24:45 -08002849 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
H. Peter Anvine2c80182005-01-15 22:15:51 +00002850 mod = 0;
Jin Kyu Songcc1dc9d2013-08-15 19:01:25 -07002851 else if (IS_MOD_01())
H. Peter Anvine2c80182005-01-15 22:15:51 +00002852 mod = 1;
2853 else
2854 mod = 2;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002855
H. Peter Anvin6867acc2007-10-10 14:58:45 -07002856 output->sib_present = false; /* no SIB - it's 16-bit */
Cyrill Gorcunov10734c72011-08-29 00:07:17 +04002857 output->bytes = mod; /* bytes of offset needed */
2858 output->modrm = GEN_MODRM(mod, rfield, rm);
H. Peter Anvine2c80182005-01-15 22:15:51 +00002859 }
2860 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002861 }
H. Peter Anvin70653092007-10-19 14:42:29 -07002862
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002863 output->size = 1 + output->sib_present + output->bytes;
H. Peter Anvin3089f7e2011-06-22 18:19:28 -07002864 return output->type;
2865
2866err:
2867 return output->type = EA_INVALID;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002868}
2869
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002870static void add_asp(insn *ins, int addrbits)
H. Peter Anvineba20a72002-04-30 20:53:55 +00002871{
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -07002872 int j, valid;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002873 int defdisp;
Keith Kaniosb7a89542007-04-12 02:40:54 +00002874
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -07002875 valid = (addrbits == 64) ? 64|32 : 32|16;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002876
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002877 switch (ins->prefixes[PPS_ASIZE]) {
2878 case P_A16:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002879 valid &= 16;
2880 break;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002881 case P_A32:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002882 valid &= 32;
2883 break;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002884 case P_A64:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002885 valid &= 64;
2886 break;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002887 case P_ASP:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002888 valid &= (addrbits == 32) ? 16 : 32;
2889 break;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002890 default:
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002891 break;
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002892 }
2893
2894 for (j = 0; j < ins->operands; j++) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002895 if (is_class(MEMORY, ins->oprs[j].type)) {
2896 opflags_t i, b;
H. Peter Anvin70653092007-10-19 14:42:29 -07002897
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002898 /* Verify as Register */
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04002899 if (!is_register(ins->oprs[j].indexreg))
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002900 i = 0;
2901 else
2902 i = nasm_reg_flags[ins->oprs[j].indexreg];
H. Peter Anvin70653092007-10-19 14:42:29 -07002903
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002904 /* Verify as Register */
Cyrill Gorcunov2124b7b2010-07-25 01:16:33 +04002905 if (!is_register(ins->oprs[j].basereg))
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002906 b = 0;
2907 else
2908 b = nasm_reg_flags[ins->oprs[j].basereg];
H. Peter Anvin70653092007-10-19 14:42:29 -07002909
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002910 if (ins->oprs[j].scale == 0)
2911 i = 0;
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002912
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002913 if (!i && !b) {
2914 int ds = ins->oprs[j].disp_size;
2915 if ((addrbits != 64 && ds > 8) ||
2916 (addrbits == 64 && ds == 16))
2917 valid &= ds;
2918 } else {
2919 if (!(REG16 & ~b))
2920 valid &= 16;
2921 if (!(REG32 & ~b))
2922 valid &= 32;
2923 if (!(REG64 & ~b))
2924 valid &= 64;
H. Peter Anvin70653092007-10-19 14:42:29 -07002925
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002926 if (!(REG16 & ~i))
2927 valid &= 16;
2928 if (!(REG32 & ~i))
2929 valid &= 32;
2930 if (!(REG64 & ~i))
2931 valid &= 64;
2932 }
2933 }
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -07002934 }
2935
2936 if (valid & addrbits) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002937 ins->addr_size = addrbits;
H. Peter Anvinc5b9ce02007-09-22 21:49:51 -07002938 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002939 /* Add an address size prefix */
Cyrill Gorcunovd6851d42011-09-25 18:01:45 +04002940 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002941 ins->addr_size = (addrbits == 32) ? 16 : 32;
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002942 } else {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002943 /* Impossible... */
2944 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2945 ins->addr_size = addrbits; /* Error recovery */
H. Peter Anvinde4b89b2007-10-01 15:41:25 -07002946 }
2947
2948 defdisp = ins->addr_size == 16 ? 16 : 32;
2949
2950 for (j = 0; j < ins->operands; j++) {
Cyrill Gorcunovd6f31242010-07-26 23:14:40 +04002951 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2952 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2953 /*
2954 * mem_offs sizes must match the address size; if not,
2955 * strip the MEM_OFFS bit and match only EA instructions
2956 */
2957 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2958 }
H. Peter Anvin3df97a72007-05-30 03:25:21 +00002959 }
H. Peter Anvinea6e34d2002-04-30 20:51:32 +00002960}