blob: 13809821e1f8547c3b012fd53a6e3a3ea9f588f5 [file] [log] [blame]
Oder Chiou6eebf352016-06-06 18:33:31 +08001/*
2 * rt5514-spi.c -- RT5514 SPI driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/input.h>
14#include <linux/spi/spi.h>
15#include <linux/device.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/slab.h>
21#include <linux/gpio.h>
22#include <linux/sched.h>
Oder Chiou6eebf352016-06-06 18:33:31 +080023#include <linux/uaccess.h>
Oder Chiou6eebf352016-06-06 18:33:31 +080024#include <linux/regulator/consumer.h>
25#include <linux/pm_qos.h>
26#include <linux/sysfs.h>
27#include <linux/clk.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35
36#include "rt5514-spi.h"
37
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +000038#define DRV_NAME "rt5514-spi"
39
Oder Chiou6eebf352016-06-06 18:33:31 +080040static struct spi_device *rt5514_spi;
41
42struct rt5514_dsp {
43 struct device *dev;
44 struct delayed_work copy_work;
45 struct mutex dma_lock;
46 struct snd_pcm_substream *substream;
47 unsigned int buf_base, buf_limit, buf_rp;
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +080048 size_t buf_size, get_size, dma_offset;
Oder Chiou6eebf352016-06-06 18:33:31 +080049};
50
51static const struct snd_pcm_hardware rt5514_spi_pcm_hardware = {
52 .info = SNDRV_PCM_INFO_MMAP |
53 SNDRV_PCM_INFO_MMAP_VALID |
54 SNDRV_PCM_INFO_INTERLEAVED,
55 .formats = SNDRV_PCM_FMTBIT_S16_LE,
56 .period_bytes_min = PAGE_SIZE,
57 .period_bytes_max = 0x20000 / 8,
58 .periods_min = 8,
59 .periods_max = 8,
60 .channels_min = 1,
61 .channels_max = 1,
62 .buffer_bytes_max = 0x20000,
63};
64
65static struct snd_soc_dai_driver rt5514_spi_dai = {
66 .name = "rt5514-dsp-cpu-dai",
67 .id = 0,
68 .capture = {
69 .stream_name = "DSP Capture",
70 .channels_min = 1,
71 .channels_max = 1,
72 .rates = SNDRV_PCM_RATE_16000,
73 .formats = SNDRV_PCM_FMTBIT_S16_LE,
74 },
75};
76
77static void rt5514_spi_copy_work(struct work_struct *work)
78{
79 struct rt5514_dsp *rt5514_dsp =
80 container_of(work, struct rt5514_dsp, copy_work.work);
Oder Chioub63d4d12016-06-17 11:02:23 +080081 struct snd_pcm_runtime *runtime;
Oder Chiou6eebf352016-06-06 18:33:31 +080082 size_t period_bytes, truncated_bytes = 0;
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +080083 unsigned int cur_wp, remain_data;
84 u8 buf[8];
Oder Chiou6eebf352016-06-06 18:33:31 +080085
86 mutex_lock(&rt5514_dsp->dma_lock);
87 if (!rt5514_dsp->substream) {
88 dev_err(rt5514_dsp->dev, "No pcm substream\n");
89 goto done;
90 }
91
Oder Chioub63d4d12016-06-17 11:02:23 +080092 runtime = rt5514_dsp->substream->runtime;
Oder Chiou6eebf352016-06-06 18:33:31 +080093 period_bytes = snd_pcm_lib_period_bytes(rt5514_dsp->substream);
Oder Chioufbb673f2018-09-17 19:03:09 +080094 if (!period_bytes) {
95 schedule_delayed_work(&rt5514_dsp->copy_work, 5);
96 goto done;
97 }
98
99 if (rt5514_dsp->buf_size % period_bytes)
100 rt5514_dsp->buf_size = (rt5514_dsp->buf_size / period_bytes) *
101 period_bytes;
Oder Chiou6eebf352016-06-06 18:33:31 +0800102
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800103 if (rt5514_dsp->get_size >= rt5514_dsp->buf_size) {
104 rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
105 sizeof(buf));
106 cur_wp = buf[0] | buf[1] << 8 | buf[2] << 16 |
107 buf[3] << 24;
108
109 if (cur_wp >= rt5514_dsp->buf_rp)
110 remain_data = (cur_wp - rt5514_dsp->buf_rp);
111 else
112 remain_data =
113 (rt5514_dsp->buf_limit - rt5514_dsp->buf_rp) +
114 (cur_wp - rt5514_dsp->buf_base);
115
116 if (remain_data < period_bytes) {
117 schedule_delayed_work(&rt5514_dsp->copy_work, 5);
118 goto done;
119 }
120 }
Oder Chiou6eebf352016-06-06 18:33:31 +0800121
122 if (rt5514_dsp->buf_rp + period_bytes <= rt5514_dsp->buf_limit) {
123 rt5514_spi_burst_read(rt5514_dsp->buf_rp,
124 runtime->dma_area + rt5514_dsp->dma_offset,
125 period_bytes);
126
127 if (rt5514_dsp->buf_rp + period_bytes == rt5514_dsp->buf_limit)
128 rt5514_dsp->buf_rp = rt5514_dsp->buf_base;
129 else
130 rt5514_dsp->buf_rp += period_bytes;
131 } else {
132 truncated_bytes = rt5514_dsp->buf_limit - rt5514_dsp->buf_rp;
133 rt5514_spi_burst_read(rt5514_dsp->buf_rp,
134 runtime->dma_area + rt5514_dsp->dma_offset,
135 truncated_bytes);
136
137 rt5514_spi_burst_read(rt5514_dsp->buf_base,
138 runtime->dma_area + rt5514_dsp->dma_offset +
139 truncated_bytes, period_bytes - truncated_bytes);
140
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800141 rt5514_dsp->buf_rp = rt5514_dsp->buf_base + period_bytes -
142 truncated_bytes;
Oder Chiou6eebf352016-06-06 18:33:31 +0800143 }
144
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800145 rt5514_dsp->get_size += period_bytes;
Oder Chiou6eebf352016-06-06 18:33:31 +0800146 rt5514_dsp->dma_offset += period_bytes;
147 if (rt5514_dsp->dma_offset >= runtime->dma_bytes)
148 rt5514_dsp->dma_offset = 0;
149
Oder Chiou6eebf352016-06-06 18:33:31 +0800150 snd_pcm_period_elapsed(rt5514_dsp->substream);
151
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800152 schedule_delayed_work(&rt5514_dsp->copy_work, 5);
153
Oder Chiou6eebf352016-06-06 18:33:31 +0800154done:
155 mutex_unlock(&rt5514_dsp->dma_lock);
156}
157
Hsin-Yu Chao659178f2017-09-13 17:54:28 +0800158static void rt5514_schedule_copy(struct rt5514_dsp *rt5514_dsp)
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800159{
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800160 u8 buf[8];
161
Oder Chiouc4a71ff2017-11-08 19:21:47 +0800162 if (!rt5514_dsp->substream)
163 return;
164
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800165 rt5514_dsp->get_size = 0;
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800166
167 /**
168 * The address area x1800XXXX is the register address, and it cannot
169 * support spi burst read perfectly. So we use the spi burst read
170 * individually to make sure the data correctly.
171 */
172 rt5514_spi_burst_read(RT5514_BUFFER_VOICE_BASE, (u8 *)&buf,
173 sizeof(buf));
174 rt5514_dsp->buf_base = buf[0] | buf[1] << 8 | buf[2] << 16 |
175 buf[3] << 24;
176
177 rt5514_spi_burst_read(RT5514_BUFFER_VOICE_LIMIT, (u8 *)&buf,
178 sizeof(buf));
179 rt5514_dsp->buf_limit = buf[0] | buf[1] << 8 | buf[2] << 16 |
180 buf[3] << 24;
181
182 rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
183 sizeof(buf));
184 rt5514_dsp->buf_rp = buf[0] | buf[1] << 8 | buf[2] << 16 |
185 buf[3] << 24;
186
oder_chiou@realtek.com818010d2017-07-31 13:47:42 +0800187 if (rt5514_dsp->buf_rp % 8)
188 rt5514_dsp->buf_rp = (rt5514_dsp->buf_rp / 8) * 8;
189
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800190 rt5514_dsp->buf_size = rt5514_dsp->buf_limit - rt5514_dsp->buf_base;
191
oder_chiou@realtek.com818010d2017-07-31 13:47:42 +0800192 if (rt5514_dsp->buf_base && rt5514_dsp->buf_limit &&
193 rt5514_dsp->buf_rp && rt5514_dsp->buf_size)
194 schedule_delayed_work(&rt5514_dsp->copy_work, 0);
Hsin-Yu Chao659178f2017-09-13 17:54:28 +0800195}
196
197static irqreturn_t rt5514_spi_irq(int irq, void *data)
198{
199 struct rt5514_dsp *rt5514_dsp = data;
200
201 rt5514_schedule_copy(rt5514_dsp);
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800202
203 return IRQ_HANDLED;
204}
205
Oder Chiou6eebf352016-06-06 18:33:31 +0800206/* PCM for streaming audio from the DSP buffer */
207static int rt5514_spi_pcm_open(struct snd_pcm_substream *substream)
208{
209 snd_soc_set_runtime_hwparams(substream, &rt5514_spi_pcm_hardware);
210
211 return 0;
212}
213
214static int rt5514_spi_hw_params(struct snd_pcm_substream *substream,
215 struct snd_pcm_hw_params *hw_params)
216{
217 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000218 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
Oder Chiou6eebf352016-06-06 18:33:31 +0800219 struct rt5514_dsp *rt5514_dsp =
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000220 snd_soc_component_get_drvdata(component);
Oder Chiou6eebf352016-06-06 18:33:31 +0800221 int ret;
Hsin-Yu Chao659178f2017-09-13 17:54:28 +0800222 u8 buf[8];
Oder Chiou6eebf352016-06-06 18:33:31 +0800223
224 mutex_lock(&rt5514_dsp->dma_lock);
225 ret = snd_pcm_lib_alloc_vmalloc_buffer(substream,
226 params_buffer_bytes(hw_params));
227 rt5514_dsp->substream = substream;
oder_chiou@realtek.comb56bff42017-08-07 18:39:32 +0800228 rt5514_dsp->dma_offset = 0;
Hsin-Yu Chao659178f2017-09-13 17:54:28 +0800229
230 /* Read IRQ status and schedule copy accordingly. */
231 rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf, sizeof(buf));
232 if (buf[0] & RT5514_IRQ_STATUS_BIT)
233 rt5514_schedule_copy(rt5514_dsp);
234
Oder Chiou6eebf352016-06-06 18:33:31 +0800235 mutex_unlock(&rt5514_dsp->dma_lock);
236
237 return ret;
238}
239
240static int rt5514_spi_hw_free(struct snd_pcm_substream *substream)
241{
242 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000243 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
Oder Chiou6eebf352016-06-06 18:33:31 +0800244 struct rt5514_dsp *rt5514_dsp =
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000245 snd_soc_component_get_drvdata(component);
Oder Chiou6eebf352016-06-06 18:33:31 +0800246
247 mutex_lock(&rt5514_dsp->dma_lock);
248 rt5514_dsp->substream = NULL;
249 mutex_unlock(&rt5514_dsp->dma_lock);
250
251 cancel_delayed_work_sync(&rt5514_dsp->copy_work);
252
253 return snd_pcm_lib_free_vmalloc_buffer(substream);
254}
255
Oder Chiou6eebf352016-06-06 18:33:31 +0800256static snd_pcm_uframes_t rt5514_spi_pcm_pointer(
257 struct snd_pcm_substream *substream)
258{
259 struct snd_pcm_runtime *runtime = substream->runtime;
260 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000261 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
Oder Chiou6eebf352016-06-06 18:33:31 +0800262 struct rt5514_dsp *rt5514_dsp =
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000263 snd_soc_component_get_drvdata(component);
Oder Chiou6eebf352016-06-06 18:33:31 +0800264
265 return bytes_to_frames(runtime, rt5514_dsp->dma_offset);
266}
267
Julia Lawall115c7252016-09-08 02:35:23 +0200268static const struct snd_pcm_ops rt5514_spi_pcm_ops = {
Oder Chiou6eebf352016-06-06 18:33:31 +0800269 .open = rt5514_spi_pcm_open,
270 .hw_params = rt5514_spi_hw_params,
271 .hw_free = rt5514_spi_hw_free,
Oder Chiou6eebf352016-06-06 18:33:31 +0800272 .pointer = rt5514_spi_pcm_pointer,
273 .mmap = snd_pcm_lib_mmap_vmalloc,
274 .page = snd_pcm_lib_get_vmalloc_page,
275};
276
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000277static int rt5514_spi_pcm_probe(struct snd_soc_component *component)
Oder Chiou6eebf352016-06-06 18:33:31 +0800278{
279 struct rt5514_dsp *rt5514_dsp;
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800280 int ret;
Oder Chiou6eebf352016-06-06 18:33:31 +0800281
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000282 rt5514_dsp = devm_kzalloc(component->dev, sizeof(*rt5514_dsp),
Oder Chiou6eebf352016-06-06 18:33:31 +0800283 GFP_KERNEL);
284
285 rt5514_dsp->dev = &rt5514_spi->dev;
286 mutex_init(&rt5514_dsp->dma_lock);
287 INIT_DELAYED_WORK(&rt5514_dsp->copy_work, rt5514_spi_copy_work);
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000288 snd_soc_component_set_drvdata(component, rt5514_dsp);
Oder Chiou6eebf352016-06-06 18:33:31 +0800289
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800290 if (rt5514_spi->irq) {
291 ret = devm_request_threaded_irq(&rt5514_spi->dev,
292 rt5514_spi->irq, NULL, rt5514_spi_irq,
293 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5514-spi",
294 rt5514_dsp);
295 if (ret)
296 dev_err(&rt5514_spi->dev,
297 "%s Failed to reguest IRQ: %d\n", __func__,
298 ret);
Brian Norris20220942017-12-15 20:07:23 -0800299 else
300 device_init_wakeup(rt5514_dsp->dev, true);
oder_chiou@realtek.com173f4612017-07-13 19:42:20 +0800301 }
302
Oder Chiou6eebf352016-06-06 18:33:31 +0800303 return 0;
304}
305
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000306static const struct snd_soc_component_driver rt5514_spi_component = {
307 .name = DRV_NAME,
Oder Chiou6eebf352016-06-06 18:33:31 +0800308 .probe = rt5514_spi_pcm_probe,
309 .ops = &rt5514_spi_pcm_ops,
310};
311
Oder Chiou6eebf352016-06-06 18:33:31 +0800312/**
313 * rt5514_spi_burst_read - Read data from SPI by rt5514 address.
314 * @addr: Start address.
315 * @rxbuf: Data Buffer for reading.
316 * @len: Data length, it must be a multiple of 8.
317 *
318 *
319 * Returns true for success.
320 */
321int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len)
322{
323 u8 spi_cmd = RT5514_SPI_CMD_BURST_READ;
324 int status;
325 u8 write_buf[8];
326 unsigned int i, end, offset = 0;
327
328 struct spi_message message;
329 struct spi_transfer x[3];
330
331 while (offset < len) {
332 if (offset + RT5514_SPI_BUF_LEN <= len)
333 end = RT5514_SPI_BUF_LEN;
334 else
335 end = len % RT5514_SPI_BUF_LEN;
336
337 write_buf[0] = spi_cmd;
338 write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
339 write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
340 write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
341 write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
342
343 spi_message_init(&message);
344 memset(x, 0, sizeof(x));
345
346 x[0].len = 5;
347 x[0].tx_buf = write_buf;
348 spi_message_add_tail(&x[0], &message);
349
350 x[1].len = 4;
351 x[1].tx_buf = write_buf;
352 spi_message_add_tail(&x[1], &message);
353
354 x[2].len = end;
355 x[2].rx_buf = rxbuf + offset;
356 spi_message_add_tail(&x[2], &message);
357
358 status = spi_sync(rt5514_spi, &message);
359
360 if (status)
361 return false;
362
363 offset += RT5514_SPI_BUF_LEN;
364 }
365
366 for (i = 0; i < len; i += 8) {
367 write_buf[0] = rxbuf[i + 0];
368 write_buf[1] = rxbuf[i + 1];
369 write_buf[2] = rxbuf[i + 2];
370 write_buf[3] = rxbuf[i + 3];
371 write_buf[4] = rxbuf[i + 4];
372 write_buf[5] = rxbuf[i + 5];
373 write_buf[6] = rxbuf[i + 6];
374 write_buf[7] = rxbuf[i + 7];
375
376 rxbuf[i + 0] = write_buf[7];
377 rxbuf[i + 1] = write_buf[6];
378 rxbuf[i + 2] = write_buf[5];
379 rxbuf[i + 3] = write_buf[4];
380 rxbuf[i + 4] = write_buf[3];
381 rxbuf[i + 5] = write_buf[2];
382 rxbuf[i + 6] = write_buf[1];
383 rxbuf[i + 7] = write_buf[0];
384 }
385
386 return true;
387}
oder_chiou@realtek.comfc9cab02017-11-07 12:31:14 +0800388EXPORT_SYMBOL_GPL(rt5514_spi_burst_read);
Oder Chiou6eebf352016-06-06 18:33:31 +0800389
390/**
391 * rt5514_spi_burst_write - Write data to SPI by rt5514 address.
392 * @addr: Start address.
393 * @txbuf: Data Buffer for writng.
394 * @len: Data length, it must be a multiple of 8.
395 *
396 *
397 * Returns true for success.
398 */
399int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len)
400{
401 u8 spi_cmd = RT5514_SPI_CMD_BURST_WRITE;
402 u8 *write_buf;
403 unsigned int i, end, offset = 0;
404
405 write_buf = kmalloc(RT5514_SPI_BUF_LEN + 6, GFP_KERNEL);
406
407 if (write_buf == NULL)
408 return -ENOMEM;
409
410 while (offset < len) {
411 if (offset + RT5514_SPI_BUF_LEN <= len)
412 end = RT5514_SPI_BUF_LEN;
413 else
414 end = len % RT5514_SPI_BUF_LEN;
415
416 write_buf[0] = spi_cmd;
417 write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
418 write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
419 write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
420 write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
421
422 for (i = 0; i < end; i += 8) {
423 write_buf[i + 12] = txbuf[offset + i + 0];
424 write_buf[i + 11] = txbuf[offset + i + 1];
425 write_buf[i + 10] = txbuf[offset + i + 2];
426 write_buf[i + 9] = txbuf[offset + i + 3];
427 write_buf[i + 8] = txbuf[offset + i + 4];
428 write_buf[i + 7] = txbuf[offset + i + 5];
429 write_buf[i + 6] = txbuf[offset + i + 6];
430 write_buf[i + 5] = txbuf[offset + i + 7];
431 }
432
433 write_buf[end + 5] = spi_cmd;
434
435 spi_write(rt5514_spi, write_buf, end + 6);
436
437 offset += RT5514_SPI_BUF_LEN;
438 }
439
440 kfree(write_buf);
441
442 return 0;
443}
444EXPORT_SYMBOL_GPL(rt5514_spi_burst_write);
445
446static int rt5514_spi_probe(struct spi_device *spi)
447{
448 int ret;
449
450 rt5514_spi = spi;
451
Axel Line9802c52016-07-14 16:57:05 +0800452 ret = devm_snd_soc_register_component(&spi->dev,
Kuninori Morimoto9fe3b2b2018-01-29 02:45:13 +0000453 &rt5514_spi_component,
Axel Line9802c52016-07-14 16:57:05 +0800454 &rt5514_spi_dai, 1);
Oder Chiou6eebf352016-06-06 18:33:31 +0800455 if (ret < 0) {
456 dev_err(&spi->dev, "Failed to register component.\n");
Axel Line9802c52016-07-14 16:57:05 +0800457 return ret;
Oder Chiou6eebf352016-06-06 18:33:31 +0800458 }
459
460 return 0;
Oder Chiou6eebf352016-06-06 18:33:31 +0800461}
462
Arnd Bergmann7e6358e2017-11-10 15:54:42 +0100463static int __maybe_unused rt5514_suspend(struct device *dev)
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800464{
465 int irq = to_spi_device(dev)->irq;
466
467 if (device_may_wakeup(dev))
468 enable_irq_wake(irq);
469
470 return 0;
471}
472
Arnd Bergmann7e6358e2017-11-10 15:54:42 +0100473static int __maybe_unused rt5514_resume(struct device *dev)
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800474{
Kuninori Morimoto04e82622018-01-29 03:45:07 +0000475 struct snd_soc_component *component = snd_soc_lookup_component(dev, DRV_NAME);
oder_chiou@realtek.come9c50aa2017-11-08 15:04:22 +0800476 struct rt5514_dsp *rt5514_dsp =
Kuninori Morimoto04e82622018-01-29 03:45:07 +0000477 snd_soc_component_get_drvdata(component);
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800478 int irq = to_spi_device(dev)->irq;
oder_chiou@realtek.come9c50aa2017-11-08 15:04:22 +0800479 u8 buf[8];
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800480
481 if (device_may_wakeup(dev))
482 disable_irq_wake(irq);
483
oder_chiou@realtek.com346cccf2017-11-20 18:23:19 +0800484 if (rt5514_dsp) {
485 if (rt5514_dsp->substream) {
486 rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf,
487 sizeof(buf));
488 if (buf[0] & RT5514_IRQ_STATUS_BIT)
489 rt5514_schedule_copy(rt5514_dsp);
490 }
oder_chiou@realtek.come9c50aa2017-11-08 15:04:22 +0800491 }
492
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800493 return 0;
494}
495
496static const struct dev_pm_ops rt5514_pm_ops = {
497 SET_SYSTEM_SLEEP_PM_OPS(rt5514_suspend, rt5514_resume)
498};
499
Oder Chiou6eebf352016-06-06 18:33:31 +0800500static const struct of_device_id rt5514_of_match[] = {
501 { .compatible = "realtek,rt5514", },
502 {},
503};
504MODULE_DEVICE_TABLE(of, rt5514_of_match);
505
506static struct spi_driver rt5514_spi_driver = {
507 .driver = {
508 .name = "rt5514",
oder_chiou@realtek.com58f1c072017-11-08 15:04:21 +0800509 .pm = &rt5514_pm_ops,
Oder Chiou6eebf352016-06-06 18:33:31 +0800510 .of_match_table = of_match_ptr(rt5514_of_match),
511 },
512 .probe = rt5514_spi_probe,
Oder Chiou6eebf352016-06-06 18:33:31 +0800513};
514module_spi_driver(rt5514_spi_driver);
515
516MODULE_DESCRIPTION("RT5514 SPI driver");
517MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
518MODULE_LICENSE("GPL v2");