| Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| David Brownell | e58b9e2 | 2008-02-04 22:28:25 -0800 | [diff] [blame] | 2 | struct mcp23s08_platform_data { |
| Peter Korsgaard | 0b7bb77 | 2011-03-09 17:56:30 +0100 | [diff] [blame] | 3 | /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI |
| 4 | * chipselect, each providing 1 gpio_chip instance with 8 gpios. |
| 5 | * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI |
| 6 | * chipselect, each providing 1 gpio_chip (port A + port B) with |
| 7 | * 16 gpios. |
| David Brownell | 8f1cc3b | 2008-07-25 01:46:09 -0700 | [diff] [blame] | 8 | */ |
| Sebastian Reichel | ce9bd0a | 2017-05-15 11:24:36 +0200 | [diff] [blame] | 9 | u32 spi_present_mask; |
| David Brownell | e58b9e2 | 2008-02-04 22:28:25 -0800 | [diff] [blame] | 10 | |
| Sebastian Reichel | 7f38c5b | 2017-05-15 11:24:38 +0200 | [diff] [blame] | 11 | /* "base" is the number of the first GPIO or -1 for dynamic |
| 12 | * assignment. If there are gaps in chip addressing the GPIO |
| 13 | * numbers are sequential .. so for example if only slaves 0 |
| 14 | * and 3 are present, their GPIOs range from base to base+15 |
| 15 | * (or base+31 for s17 variant). |
| David Brownell | 8f1cc3b | 2008-07-25 01:46:09 -0700 | [diff] [blame] | 16 | */ |
| David Brownell | e58b9e2 | 2008-02-04 22:28:25 -0800 | [diff] [blame] | 17 | unsigned base; |
| David Brownell | e58b9e2 | 2008-02-04 22:28:25 -0800 | [diff] [blame] | 18 | }; |