| Patrick Havelange | cdff431 | 2019-04-02 15:30:47 +0900 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | #ifndef __FSL_FTM_H__ |
| 3 | #define __FSL_FTM_H__ |
| 4 | |
| 5 | #define FTM_SC 0x0 /* Status And Control */ |
| 6 | #define FTM_CNT 0x4 /* Counter */ |
| 7 | #define FTM_MOD 0x8 /* Modulo */ |
| 8 | |
| 9 | #define FTM_CNTIN 0x4C /* Counter Initial Value */ |
| 10 | #define FTM_STATUS 0x50 /* Capture And Compare Status */ |
| 11 | #define FTM_MODE 0x54 /* Features Mode Selection */ |
| 12 | #define FTM_SYNC 0x58 /* Synchronization */ |
| 13 | #define FTM_OUTINIT 0x5C /* Initial State For Channels Output */ |
| 14 | #define FTM_OUTMASK 0x60 /* Output Mask */ |
| 15 | #define FTM_COMBINE 0x64 /* Function For Linked Channels */ |
| 16 | #define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */ |
| 17 | #define FTM_EXTTRIG 0x6C /* FTM External Trigger */ |
| 18 | #define FTM_POL 0x70 /* Channels Polarity */ |
| 19 | #define FTM_FMS 0x74 /* Fault Mode Status */ |
| 20 | #define FTM_FILTER 0x78 /* Input Capture Filter Control */ |
| 21 | #define FTM_FLTCTRL 0x7C /* Fault Control */ |
| 22 | #define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */ |
| 23 | #define FTM_CONF 0x84 /* Configuration */ |
| 24 | #define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */ |
| 25 | #define FTM_SYNCONF 0x8C /* Synchronization Configuration */ |
| 26 | #define FTM_INVCTRL 0x90 /* FTM Inverting Control */ |
| 27 | #define FTM_SWOCTRL 0x94 /* FTM Software Output Control */ |
| 28 | #define FTM_PWMLOAD 0x98 /* FTM PWM Load */ |
| 29 | |
| 30 | #define FTM_SC_CLK_MASK_SHIFT 3 |
| 31 | #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) |
| 32 | #define FTM_SC_TOF 0x80 |
| 33 | #define FTM_SC_TOIE 0x40 |
| 34 | #define FTM_SC_CPWMS 0x20 |
| 35 | #define FTM_SC_CLKS 0x18 |
| 36 | #define FTM_SC_PS_1 0x0 |
| 37 | #define FTM_SC_PS_2 0x1 |
| 38 | #define FTM_SC_PS_4 0x2 |
| 39 | #define FTM_SC_PS_8 0x3 |
| 40 | #define FTM_SC_PS_16 0x4 |
| 41 | #define FTM_SC_PS_32 0x5 |
| 42 | #define FTM_SC_PS_64 0x6 |
| 43 | #define FTM_SC_PS_128 0x7 |
| 44 | #define FTM_SC_PS_MASK 0x7 |
| 45 | |
| 46 | #define FTM_MODE_FAULTIE 0x80 |
| 47 | #define FTM_MODE_FAULTM 0x60 |
| 48 | #define FTM_MODE_CAPTEST 0x10 |
| 49 | #define FTM_MODE_PWMSYNC 0x8 |
| 50 | #define FTM_MODE_WPDIS 0x4 |
| 51 | #define FTM_MODE_INIT 0x2 |
| 52 | #define FTM_MODE_FTMEN 0x1 |
| 53 | |
| 54 | /* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally |
| 55 | * and these bits cannot be set. Flextimer cannot use Filter in |
| 56 | * Quadrature Decoder Mode. |
| 57 | * https://community.nxp.com/thread/467648#comment-1010319 |
| 58 | */ |
| 59 | #define FTM_QDCTRL_PHAFLTREN 0x80 |
| 60 | #define FTM_QDCTRL_PHBFLTREN 0x40 |
| 61 | #define FTM_QDCTRL_PHAPOL 0x20 |
| 62 | #define FTM_QDCTRL_PHBPOL 0x10 |
| 63 | #define FTM_QDCTRL_QUADMODE 0x8 |
| 64 | #define FTM_QDCTRL_QUADDIR 0x4 |
| 65 | #define FTM_QDCTRL_TOFDIR 0x2 |
| 66 | #define FTM_QDCTRL_QUADEN 0x1 |
| 67 | |
| 68 | #define FTM_FMS_FAULTF 0x80 |
| 69 | #define FTM_FMS_WPEN 0x40 |
| 70 | #define FTM_FMS_FAULTIN 0x10 |
| 71 | #define FTM_FMS_FAULTF3 0x8 |
| 72 | #define FTM_FMS_FAULTF2 0x4 |
| 73 | #define FTM_FMS_FAULTF1 0x2 |
| 74 | #define FTM_FMS_FAULTF0 0x1 |
| 75 | |
| 76 | #define FTM_CSC_BASE 0xC |
| 77 | #define FTM_CSC_MSB 0x20 |
| 78 | #define FTM_CSC_MSA 0x10 |
| 79 | #define FTM_CSC_ELSB 0x8 |
| 80 | #define FTM_CSC_ELSA 0x4 |
| 81 | #define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) |
| 82 | |
| 83 | #define FTM_CV_BASE 0x10 |
| 84 | #define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) |
| 85 | |
| 86 | #define FTM_PS_MAX 7 |
| 87 | |
| 88 | #endif |