| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Thierry Reding | 497c56a | 2013-10-07 09:55:57 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 NVIDIA Corporation |
| Thierry Reding | 497c56a | 2013-10-07 09:55:57 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef TEGRA_GR2D_H |
| 7 | #define TEGRA_GR2D_H |
| 8 | |
| 9 | #define GR2D_UA_BASE_ADDR 0x1a |
| 10 | #define GR2D_VA_BASE_ADDR 0x1b |
| 11 | #define GR2D_PAT_BASE_ADDR 0x26 |
| 12 | #define GR2D_DSTA_BASE_ADDR 0x2b |
| 13 | #define GR2D_DSTB_BASE_ADDR 0x2c |
| 14 | #define GR2D_DSTC_BASE_ADDR 0x2d |
| 15 | #define GR2D_SRCA_BASE_ADDR 0x31 |
| 16 | #define GR2D_SRCB_BASE_ADDR 0x32 |
| 17 | #define GR2D_SRC_BASE_ADDR_SB 0x48 |
| 18 | #define GR2D_DSTA_BASE_ADDR_SB 0x49 |
| 19 | #define GR2D_DSTB_BASE_ADDR_SB 0x4a |
| 20 | #define GR2D_UA_BASE_ADDR_SB 0x4b |
| 21 | #define GR2D_VA_BASE_ADDR_SB 0x4c |
| 22 | |
| 23 | #define GR2D_NUM_REGS 0x4d |
| 24 | |
| 25 | #endif |