blob: 44bda75355e2bc5c7f268d90ee6c6990dccf3b1b [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002/*
Arto Merilainende2ba662013-03-22 16:34:08 +02003 * Copyright (C) 2012-2013 Avionic Design GmbH
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
Arto Merilainende2ba662013-03-22 16:34:08 +02006 * Based on the KMS/FB CMA helpers
7 * Copyright (C) 2012 Analog Device Inc.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00008 */
9
Thierry Reding986c58d2015-08-11 13:11:49 +020010#include <linux/console.h>
11
Arto Merilainende2ba662013-03-22 16:34:08 +020012#include "drm.h"
13#include "gem.h"
Daniel Stone0bc6af02018-03-30 15:11:26 +010014#include <drm/drm_gem_framebuffer_helper.h>
Daniel Vetterfcd70cd2019-01-17 22:03:34 +010015#include <drm/drm_modeset_helper.h>
Arto Merilainende2ba662013-03-22 16:34:08 +020016
Archit Tanejab110ef32015-10-27 13:40:59 +053017#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020018static inline struct tegra_fbdev *to_tegra_fbdev(struct drm_fb_helper *helper)
19{
20 return container_of(helper, struct tegra_fbdev, base);
21}
Thierry Reding60c2f702013-10-31 13:28:50 +010022#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020023
24struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
25 unsigned int index)
26{
Daniel Stone0bc6af02018-03-30 15:11:26 +010027 return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
Arto Merilainende2ba662013-03-22 16:34:08 +020028}
29
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020030bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
31{
Daniel Stone0bc6af02018-03-30 15:11:26 +010032 struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020033
Daniel Stone0bc6af02018-03-30 15:11:26 +010034 if (bo->flags & TEGRA_BO_BOTTOM_UP)
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020035 return true;
36
37 return false;
38}
39
Thierry Redingc134f012014-06-03 14:48:12 +020040int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
41 struct tegra_bo_tiling *tiling)
Thierry Reding773af772013-10-04 22:34:01 +020042{
Daniel Stone0bc6af02018-03-30 15:11:26 +010043 uint64_t modifier = framebuffer->modifier;
Thierry Reding773af772013-10-04 22:34:01 +020044
Thierry Reding268892c2017-10-12 16:39:20 +020045 switch (modifier) {
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010046 case DRM_FORMAT_MOD_LINEAR:
47 tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
48 tiling->value = 0;
49 break;
50
Thierry Reding268892c2017-10-12 16:39:20 +020051 case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
Alexandre Courbot5e911442016-11-08 16:50:42 +090052 tiling->mode = TEGRA_BO_TILING_MODE_TILED;
53 tiling->value = 0;
54 break;
55
Thierry Reding268892c2017-10-12 16:39:20 +020056 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
Alexandre Courbot5e911442016-11-08 16:50:42 +090057 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
Thierry Reding268892c2017-10-12 16:39:20 +020058 tiling->value = 0;
59 break;
60
61 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
62 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
63 tiling->value = 1;
64 break;
65
66 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
67 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
68 tiling->value = 2;
69 break;
70
71 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
72 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
73 tiling->value = 3;
74 break;
75
76 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
77 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
78 tiling->value = 4;
79 break;
80
81 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
82 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
83 tiling->value = 5;
Alexandre Courbot5e911442016-11-08 16:50:42 +090084 break;
85
86 default:
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010087 return -EINVAL;
Alexandre Courbot5e911442016-11-08 16:50:42 +090088 }
Thierry Reding773af772013-10-04 22:34:01 +020089
Thierry Redingc134f012014-06-03 14:48:12 +020090 return 0;
Thierry Reding773af772013-10-04 22:34:01 +020091}
92
Ville Syrjälä4ecae782015-12-15 12:21:13 +010093static const struct drm_framebuffer_funcs tegra_fb_funcs = {
Daniel Stone5cb8b992018-03-30 15:11:29 +010094 .destroy = drm_gem_fb_destroy,
Daniel Stone0bc6af02018-03-30 15:11:26 +010095 .create_handle = drm_gem_fb_create_handle,
Arto Merilainende2ba662013-03-22 16:34:08 +020096};
97
Daniel Stonedbc33c72018-03-30 15:11:27 +010098static struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
99 const struct drm_mode_fb_cmd2 *mode_cmd,
100 struct tegra_bo **planes,
101 unsigned int num_planes)
Arto Merilainende2ba662013-03-22 16:34:08 +0200102{
Daniel Stonedbc33c72018-03-30 15:11:27 +0100103 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200104 unsigned int i;
105 int err;
106
107 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
108 if (!fb)
109 return ERR_PTR(-ENOMEM);
110
Daniel Stonedbc33c72018-03-30 15:11:27 +0100111 drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
Arto Merilainende2ba662013-03-22 16:34:08 +0200112
Daniel Stonedbc33c72018-03-30 15:11:27 +0100113 for (i = 0; i < fb->format->num_planes; i++)
114 fb->obj[i] = &planes[i]->gem;
Arto Merilainende2ba662013-03-22 16:34:08 +0200115
Daniel Stonedbc33c72018-03-30 15:11:27 +0100116 err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200117 if (err < 0) {
118 dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
119 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200120 kfree(fb);
121 return ERR_PTR(err);
122 }
123
124 return fb;
125}
126
Thierry Redingf9914212014-11-26 13:03:57 +0100127struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
128 struct drm_file *file,
Ville Syrjälä1eb834512015-11-11 19:11:29 +0200129 const struct drm_mode_fb_cmd2 *cmd)
Arto Merilainende2ba662013-03-22 16:34:08 +0200130{
131 unsigned int hsub, vsub, i;
132 struct tegra_bo *planes[4];
133 struct drm_gem_object *gem;
Daniel Stonedbc33c72018-03-30 15:11:27 +0100134 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200135 int err;
136
137 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format);
138 vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format);
139
140 for (i = 0; i < drm_format_num_planes(cmd->pixel_format); i++) {
141 unsigned int width = cmd->width / (i ? hsub : 1);
142 unsigned int height = cmd->height / (i ? vsub : 1);
143 unsigned int size, bpp;
144
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100145 gem = drm_gem_object_lookup(file, cmd->handles[i]);
Arto Merilainende2ba662013-03-22 16:34:08 +0200146 if (!gem) {
147 err = -ENXIO;
148 goto unreference;
149 }
150
151 bpp = drm_format_plane_cpp(cmd->pixel_format, i);
152
153 size = (height - 1) * cmd->pitches[i] +
154 width * bpp + cmd->offsets[i];
155
156 if (gem->size < size) {
157 err = -EINVAL;
158 goto unreference;
159 }
160
161 planes[i] = to_tegra_bo(gem);
162 }
163
164 fb = tegra_fb_alloc(drm, cmd, planes, i);
165 if (IS_ERR(fb)) {
166 err = PTR_ERR(fb);
167 goto unreference;
168 }
169
Daniel Stonedbc33c72018-03-30 15:11:27 +0100170 return fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200171
172unreference:
173 while (i--)
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300174 drm_gem_object_put_unlocked(&planes[i]->gem);
Arto Merilainende2ba662013-03-22 16:34:08 +0200175
176 return ERR_PTR(err);
177}
178
Archit Tanejab110ef32015-10-27 13:40:59 +0530179#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingb8f3f502018-02-07 18:45:56 +0100180static int tegra_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
181{
182 struct drm_fb_helper *helper = info->par;
183 struct tegra_bo *bo;
184 int err;
185
186 bo = tegra_fb_get_plane(helper->fb, 0);
187
188 err = drm_gem_mmap_obj(&bo->gem, bo->gem.size, vma);
189 if (err < 0)
190 return err;
191
192 return __tegra_gem_mmap(&bo->gem, vma);
193}
194
Arto Merilainende2ba662013-03-22 16:34:08 +0200195static struct fb_ops tegra_fb_ops = {
196 .owner = THIS_MODULE,
Stefan Christ902c2552016-11-14 00:03:22 +0100197 DRM_FB_HELPER_DEFAULT_OPS,
Archit Taneja0f7d9052015-07-22 14:58:07 +0530198 .fb_fillrect = drm_fb_helper_sys_fillrect,
199 .fb_copyarea = drm_fb_helper_sys_copyarea,
200 .fb_imageblit = drm_fb_helper_sys_imageblit,
Thierry Redingb8f3f502018-02-07 18:45:56 +0100201 .fb_mmap = tegra_fb_mmap,
Arto Merilainende2ba662013-03-22 16:34:08 +0200202};
203
204static int tegra_fbdev_probe(struct drm_fb_helper *helper,
205 struct drm_fb_helper_surface_size *sizes)
206{
207 struct tegra_fbdev *fbdev = to_tegra_fbdev(helper);
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200208 struct tegra_drm *tegra = helper->dev->dev_private;
Arto Merilainende2ba662013-03-22 16:34:08 +0200209 struct drm_device *drm = helper->dev;
210 struct drm_mode_fb_cmd2 cmd = { 0 };
211 unsigned int bytes_per_pixel;
212 struct drm_framebuffer *fb;
213 unsigned long offset;
214 struct fb_info *info;
215 struct tegra_bo *bo;
216 size_t size;
217 int err;
218
219 bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
220
221 cmd.width = sizes->surface_width;
222 cmd.height = sizes->surface_height;
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200223 cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
224 tegra->pitch_align);
Thierry Reding71835ca2017-11-14 16:09:30 +0100225
Arto Merilainende2ba662013-03-22 16:34:08 +0200226 cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
227 sizes->surface_depth);
228
229 size = cmd.pitches[0] * cmd.height;
230
Thierry Reding773af772013-10-04 22:34:01 +0200231 bo = tegra_bo_create(drm, size, 0);
Arto Merilainende2ba662013-03-22 16:34:08 +0200232 if (IS_ERR(bo))
233 return PTR_ERR(bo);
234
Archit Taneja0f7d9052015-07-22 14:58:07 +0530235 info = drm_fb_helper_alloc_fbi(helper);
236 if (IS_ERR(info)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200237 dev_err(drm->dev, "failed to allocate framebuffer info\n");
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300238 drm_gem_object_put_unlocked(&bo->gem);
Archit Taneja0f7d9052015-07-22 14:58:07 +0530239 return PTR_ERR(info);
Arto Merilainende2ba662013-03-22 16:34:08 +0200240 }
241
242 fbdev->fb = tegra_fb_alloc(drm, &cmd, &bo, 1);
243 if (IS_ERR(fbdev->fb)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200244 err = PTR_ERR(fbdev->fb);
Thierry Redingcb10c812014-11-06 14:36:19 +0100245 dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n",
246 err);
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300247 drm_gem_object_put_unlocked(&bo->gem);
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100248 return PTR_ERR(fbdev->fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200249 }
250
Daniel Stonedbc33c72018-03-30 15:11:27 +0100251 fb = fbdev->fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200252 helper->fb = fb;
253 helper->fbdev = info;
254
Arto Merilainende2ba662013-03-22 16:34:08 +0200255 info->fbops = &tegra_fb_ops;
256
Daniel Vetter4a536932019-03-26 14:20:05 +0100257 drm_fb_helper_fill_info(info, helper, sizes);
Arto Merilainende2ba662013-03-22 16:34:08 +0200258
259 offset = info->var.xoffset * bytes_per_pixel +
260 info->var.yoffset * fb->pitches[0];
261
Thierry Redingdf06b752014-06-26 21:41:53 +0200262 if (bo->pages) {
263 bo->vaddr = vmap(bo->pages, bo->num_pages, VM_MAP,
264 pgprot_writecombine(PAGE_KERNEL));
265 if (!bo->vaddr) {
266 dev_err(drm->dev, "failed to vmap() framebuffer\n");
267 err = -ENOMEM;
268 goto destroy;
269 }
270 }
271
Arto Merilainende2ba662013-03-22 16:34:08 +0200272 drm->mode_config.fb_base = (resource_size_t)bo->paddr;
Thierry Reding9ab34152013-11-08 13:18:14 +0100273 info->screen_base = (void __iomem *)bo->vaddr + offset;
Arto Merilainende2ba662013-03-22 16:34:08 +0200274 info->screen_size = size;
275 info->fix.smem_start = (unsigned long)(bo->paddr + offset);
276 info->fix.smem_len = size;
277
278 return 0;
279
280destroy:
Daniel Vetter3e7d2fdd2016-12-27 11:49:25 +0100281 drm_framebuffer_remove(fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200282 return err;
283}
284
Thierry Reding3a493872014-06-27 17:19:23 +0200285static const struct drm_fb_helper_funcs tegra_fb_helper_funcs = {
Arto Merilainende2ba662013-03-22 16:34:08 +0200286 .fb_probe = tegra_fbdev_probe,
287};
288
Thierry Redinge2215321f2014-06-27 17:19:25 +0200289static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm)
Arto Merilainende2ba662013-03-22 16:34:08 +0200290{
Arto Merilainende2ba662013-03-22 16:34:08 +0200291 struct tegra_fbdev *fbdev;
Arto Merilainende2ba662013-03-22 16:34:08 +0200292
293 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
294 if (!fbdev) {
295 dev_err(drm->dev, "failed to allocate DRM fbdev\n");
296 return ERR_PTR(-ENOMEM);
297 }
298
Thierry Reding10a23102014-06-27 17:19:24 +0200299 drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200300
Thierry Redinge2215321f2014-06-27 17:19:25 +0200301 return fbdev;
302}
303
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100304static void tegra_fbdev_free(struct tegra_fbdev *fbdev)
305{
306 kfree(fbdev);
307}
308
Thierry Redinge2215321f2014-06-27 17:19:25 +0200309static int tegra_fbdev_init(struct tegra_fbdev *fbdev,
310 unsigned int preferred_bpp,
311 unsigned int num_crtc,
312 unsigned int max_connectors)
313{
314 struct drm_device *drm = fbdev->base.dev;
315 int err;
316
Gabriel Krisman Bertazie4563f62017-02-02 14:26:40 -0200317 err = drm_fb_helper_init(drm, &fbdev->base, max_connectors);
Arto Merilainende2ba662013-03-22 16:34:08 +0200318 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100319 dev_err(drm->dev, "failed to initialize DRM FB helper: %d\n",
320 err);
Thierry Redinge2215321f2014-06-27 17:19:25 +0200321 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200322 }
323
324 err = drm_fb_helper_single_add_all_connectors(&fbdev->base);
325 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100326 dev_err(drm->dev, "failed to add connectors: %d\n", err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200327 goto fini;
328 }
329
Arto Merilainende2ba662013-03-22 16:34:08 +0200330 err = drm_fb_helper_initial_config(&fbdev->base, preferred_bpp);
331 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100332 dev_err(drm->dev, "failed to set initial configuration: %d\n",
333 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200334 goto fini;
335 }
336
Thierry Redinge2215321f2014-06-27 17:19:25 +0200337 return 0;
Arto Merilainende2ba662013-03-22 16:34:08 +0200338
339fini:
340 drm_fb_helper_fini(&fbdev->base);
Thierry Redinge2215321f2014-06-27 17:19:25 +0200341 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200342}
343
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100344static void tegra_fbdev_exit(struct tegra_fbdev *fbdev)
Arto Merilainende2ba662013-03-22 16:34:08 +0200345{
Archit Taneja0f7d9052015-07-22 14:58:07 +0530346 drm_fb_helper_unregister_fbi(&fbdev->base);
Arto Merilainende2ba662013-03-22 16:34:08 +0200347
Daniel Stonec34a9972018-03-30 15:11:28 +0100348 if (fbdev->fb) {
349 struct tegra_bo *bo = tegra_fb_get_plane(fbdev->fb, 0);
350
351 /* Undo the special mapping we made in fbdev probe. */
352 if (bo && bo->pages) {
353 vunmap(bo->vaddr);
Souptick Joarder53f1e062018-08-01 01:37:05 +0530354 bo->vaddr = NULL;
Daniel Stonec34a9972018-03-30 15:11:28 +0100355 }
356
Daniel Stonedbc33c72018-03-30 15:11:27 +0100357 drm_framebuffer_remove(fbdev->fb);
Daniel Stonec34a9972018-03-30 15:11:28 +0100358 }
Arto Merilainende2ba662013-03-22 16:34:08 +0200359
360 drm_fb_helper_fini(&fbdev->base);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100361 tegra_fbdev_free(fbdev);
Arto Merilainende2ba662013-03-22 16:34:08 +0200362}
Thierry Reding60c2f702013-10-31 13:28:50 +0100363#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000364
Thierry Redinge2215321f2014-06-27 17:19:25 +0200365int tegra_drm_fb_prepare(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000366{
Archit Tanejab110ef32015-10-27 13:40:59 +0530367#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200368 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000369
Thierry Redinge2215321f2014-06-27 17:19:25 +0200370 tegra->fbdev = tegra_fbdev_create(drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100371 if (IS_ERR(tegra->fbdev))
372 return PTR_ERR(tegra->fbdev);
373#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000374
375 return 0;
376}
377
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100378void tegra_drm_fb_free(struct drm_device *drm)
379{
Archit Tanejab110ef32015-10-27 13:40:59 +0530380#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100381 struct tegra_drm *tegra = drm->dev_private;
382
383 tegra_fbdev_free(tegra->fbdev);
384#endif
385}
386
Thierry Redinge2215321f2014-06-27 17:19:25 +0200387int tegra_drm_fb_init(struct drm_device *drm)
388{
Archit Tanejab110ef32015-10-27 13:40:59 +0530389#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redinge2215321f2014-06-27 17:19:25 +0200390 struct tegra_drm *tegra = drm->dev_private;
391 int err;
392
393 err = tegra_fbdev_init(tegra->fbdev, 32, drm->mode_config.num_crtc,
394 drm->mode_config.num_connector);
395 if (err < 0)
396 return err;
397#endif
398
399 return 0;
400}
401
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000402void tegra_drm_fb_exit(struct drm_device *drm)
403{
Archit Tanejab110ef32015-10-27 13:40:59 +0530404#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200405 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000406
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100407 tegra_fbdev_exit(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100408#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000409}