Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-lpc32xx/include/mach/uncompress.h |
| 4 | * |
| 5 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 6 | * |
| 7 | * Copyright (C) 2010 NXP Semiconductors |
Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __ASM_ARM_ARCH_UNCOMPRESS_H |
| 11 | #define __ASM_ARM_ARCH_UNCOMPRESS_H |
| 12 | |
| 13 | #include <linux/io.h> |
| 14 | |
| 15 | #include <mach/hardware.h> |
| 16 | #include <mach/platform.h> |
| 17 | |
| 18 | /* |
| 19 | * Uncompress output is hardcoded to standard UART 5 |
| 20 | */ |
| 21 | |
| 22 | #define UART_FIFO_CTL_TX_RESET (1 << 2) |
| 23 | #define UART_STATUS_TX_MT (1 << 6) |
| 24 | |
| 25 | #define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) |
| 26 | |
| 27 | #define LPC32XX_UART_DLLFIFO_O 0x00 |
| 28 | #define LPC32XX_UART_IIRFCR_O 0x08 |
| 29 | #define LPC32XX_UART_LSR_O 0x14 |
| 30 | |
| 31 | static inline void putc(int ch) |
| 32 | { |
| 33 | /* Wait for transmit FIFO to empty */ |
| 34 | while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & |
| 35 | UART_STATUS_TX_MT) == 0) |
| 36 | ; |
| 37 | |
| 38 | __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); |
| 39 | } |
| 40 | |
| 41 | static inline void flush(void) |
| 42 | { |
| 43 | __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | |
| 44 | UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); |
| 45 | } |
| 46 | |
| 47 | /* NULL functions; we don't presently need them */ |
| 48 | #define arch_decomp_setup() |
Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 49 | |
| 50 | #endif |