| Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Kevin Wells | 343d353 | 2010-02-26 15:53:39 -0800 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-lpc32xx/include/mach/entry-macro.S |
| 4 | * |
| 5 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 6 | * |
| 7 | * Copyright (C) 2010 NXP Semiconductors |
| Kevin Wells | 343d353 | 2010-02-26 15:53:39 -0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <mach/hardware.h> |
| 11 | #include <mach/platform.h> |
| 12 | |
| 13 | #define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 |
| 14 | |
| Kevin Wells | 343d353 | 2010-02-26 15:53:39 -0800 | [diff] [blame] | 15 | .macro get_irqnr_preamble, base, tmp |
| 16 | ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) |
| 17 | .endm |
| 18 | |
| Kevin Wells | 343d353 | 2010-02-26 15:53:39 -0800 | [diff] [blame] | 19 | /* |
| 20 | * Return IRQ number in irqnr. Also return processor Z flag status in CPSR |
| 21 | * as set if an interrupt is pending. |
| 22 | */ |
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 24 | ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] |
| 25 | clz \irqnr, \irqstat |
| 26 | rsb \irqnr, \irqnr, #31 |
| 27 | teq \irqstat, #0 |
| 28 | .endm |