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Alexandru M Stan89bf26c2014-11-26 17:30:27 -08001/*
2 * Copyright 2014 Google, Inc
3 * Author: Alexandru M Stan <amstan@chromium.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/slab.h>
Stephen Boydf684ff82015-06-19 15:00:46 -070017#include <linux/clk.h>
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080018#include <linux/clk-provider.h>
Heiko Stuebner7c494ad2015-07-05 11:00:15 +020019#include <linux/io.h>
20#include <linux/kernel.h>
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080021#include "clk.h"
22
23struct rockchip_mmc_clock {
24 struct clk_hw hw;
25 void __iomem *reg;
26 int id;
27 int shift;
Shawn Lin60cf09e2018-03-09 09:51:03 +080028 int cached_phase;
29 struct notifier_block clk_rate_change_nb;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080030};
31
32#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
33
34#define RK3288_MMC_CLKGEN_DIV 2
35
36static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
37 unsigned long parent_rate)
38{
39 return parent_rate / RK3288_MMC_CLKGEN_DIV;
40}
41
42#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
43#define ROCKCHIP_MMC_DEGREE_MASK 0x3
44#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
45#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
46
47#define PSECS_PER_SEC 1000000000000LL
48
49/*
Douglas Andersonf0232062015-09-30 16:07:37 +020050 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
51 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080052 */
53#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
54
55static int rockchip_mmc_get_phase(struct clk_hw *hw)
56{
57 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
58 unsigned long rate = clk_get_rate(hw->clk);
59 u32 raw_value;
60 u16 degrees;
61 u32 delay_num = 0;
62
Shawn Lin4bf59902018-03-05 11:25:58 +080063 /* See the comment for rockchip_mmc_set_phase below */
64 if (!rate) {
65 pr_err("%s: invalid clk rate\n", __func__);
66 return -EINVAL;
67 }
68
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080069 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
70
71 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
72
73 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
74 /* degrees/delaynum * 10000 */
75 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
76 36 * (rate / 1000000);
77
78 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
79 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
Douglas Anderson4351f192015-09-30 16:07:38 +020080 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080081 }
82
83 return degrees % 360;
84}
85
86static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
87{
88 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
89 unsigned long rate = clk_get_rate(hw->clk);
90 u8 nineties, remainder;
91 u8 delay_num;
92 u32 raw_value;
Douglas Anderson4351f192015-09-30 16:07:38 +020093 u32 delay;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -080094
Shawn Lin4bf59902018-03-05 11:25:58 +080095 /*
96 * The below calculation is based on the output clock from
97 * MMC host to the card, which expects the phase clock inherits
98 * the clock rate from its parent, namely the output clock
99 * provider of MMC host. However, things may go wrong if
100 * (1) It is orphan.
101 * (2) It is assigned to the wrong parent.
102 *
103 * This check help debug the case (1), which seems to be the
104 * most likely problem we often face and which makes it difficult
105 * for people to debug unstable mmc tuning results.
106 */
107 if (!rate) {
108 pr_err("%s: invalid clk rate\n", __func__);
109 return -EINVAL;
110 }
111
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800112 nineties = degrees / 90;
Douglas Andersonf0232062015-09-30 16:07:37 +0200113 remainder = (degrees % 90);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800114
Douglas Andersonf0232062015-09-30 16:07:37 +0200115 /*
116 * Due to the inexact nature of the "fine" delay, we might
117 * actually go non-monotonic. We don't go _too_ monotonic
118 * though, so we should be OK. Here are options of how we may
119 * work:
120 *
121 * Ideally we end up with:
122 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
123 *
124 * On one extreme (if delay is actually 44ps):
125 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
126 * The other (if delay is actually 77ps):
127 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
128 *
129 * It's possible we might make a delay that is up to 25
130 * degrees off from what we think we're making. That's OK
131 * though because we should be REALLY far from any bad range.
132 */
133
134 /*
135 * Convert to delay; do a little extra work to make sure we
136 * don't overflow 32-bit / 64-bit numbers.
137 */
Douglas Anderson4351f192015-09-30 16:07:38 +0200138 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800139 delay *= remainder;
Douglas Anderson4351f192015-09-30 16:07:38 +0200140 delay = DIV_ROUND_CLOSEST(delay,
141 (rate / 1000) * 36 *
142 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
Douglas Andersonf0232062015-09-30 16:07:37 +0200143
Douglas Anderson4351f192015-09-30 16:07:38 +0200144 delay_num = (u8) min_t(u32, delay, 255);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800145
146 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
147 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
148 raw_value |= nineties;
Heiko Stuebner03ae1742016-04-19 21:29:27 +0200149 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
150 mmc_clock->reg);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800151
152 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700153 clk_hw_get_name(hw), degrees, delay_num,
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800154 mmc_clock->reg, raw_value>>(mmc_clock->shift),
155 rockchip_mmc_get_phase(hw)
156 );
157
158 return 0;
159}
160
161static const struct clk_ops rockchip_mmc_clk_ops = {
162 .recalc_rate = rockchip_mmc_recalc,
163 .get_phase = rockchip_mmc_get_phase,
164 .set_phase = rockchip_mmc_set_phase,
165};
166
Shawn Lin60cf09e2018-03-09 09:51:03 +0800167#define to_rockchip_mmc_clock(x) \
168 container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)
169static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,
170 unsigned long event, void *data)
171{
172 struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);
Shawn Lin570fda92018-03-21 10:39:20 +0800173 struct clk_notifier_data *ndata = data;
Shawn Lin60cf09e2018-03-09 09:51:03 +0800174
175 /*
176 * rockchip_mmc_clk is mostly used by mmc controllers to sample
177 * the intput data, which expects the fixed phase after the tuning
178 * process. However if the clock rate is changed, the phase is stale
179 * and may break the data sampling. So here we try to restore the phase
Shawn Lin570fda92018-03-21 10:39:20 +0800180 * for that case, except that
181 * (1) cached_phase is invaild since we inevitably cached it when the
182 * clock provider be reparented from orphan to its real parent in the
183 * first place. Otherwise we may mess up the initialization of MMC cards
184 * since we only set the default sample phase and drive phase later on.
185 * (2) the new coming rate is higher than the older one since mmc driver
186 * set the max-frequency to match the boards' ability but we can't go
187 * over the heads of that, otherwise the tests smoke out the issue.
Shawn Lin60cf09e2018-03-09 09:51:03 +0800188 */
Shawn Lin570fda92018-03-21 10:39:20 +0800189 if (ndata->old_rate <= ndata->new_rate)
190 return NOTIFY_DONE;
191
Shawn Lin60cf09e2018-03-09 09:51:03 +0800192 if (event == PRE_RATE_CHANGE)
193 mmc_clock->cached_phase =
194 rockchip_mmc_get_phase(&mmc_clock->hw);
Shawn Lin570fda92018-03-21 10:39:20 +0800195 else if (mmc_clock->cached_phase != -EINVAL &&
196 event == POST_RATE_CHANGE)
Shawn Lin60cf09e2018-03-09 09:51:03 +0800197 rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);
198
199 return NOTIFY_DONE;
200}
201
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800202struct clk *rockchip_clk_register_mmc(const char *name,
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +0200203 const char *const *parent_names, u8 num_parents,
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800204 void __iomem *reg, int shift)
205{
206 struct clk_init_data init;
207 struct rockchip_mmc_clock *mmc_clock;
208 struct clk *clk;
Shawn Lin60cf09e2018-03-09 09:51:03 +0800209 int ret;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800210
211 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
212 if (!mmc_clock)
Shawn Lin022dce02016-02-15 11:33:41 +0800213 return ERR_PTR(-ENOMEM);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800214
Heiko Stuebner7c494ad2015-07-05 11:00:15 +0200215 init.name = name;
Heiko Stuebner595144c2016-05-17 20:57:50 +0200216 init.flags = 0;
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800217 init.num_parents = num_parents;
218 init.parent_names = parent_names;
219 init.ops = &rockchip_mmc_clk_ops;
220
221 mmc_clock->hw.init = &init;
222 mmc_clock->reg = reg;
223 mmc_clock->shift = shift;
224
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800225 clk = clk_register(NULL, &mmc_clock->hw);
Shawn Lin0d92d182018-03-21 10:39:20 +0800226 if (IS_ERR(clk)) {
227 ret = PTR_ERR(clk);
Shawn Lin60cf09e2018-03-09 09:51:03 +0800228 goto err_register;
Shawn Lin0d92d182018-03-21 10:39:20 +0800229 }
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800230
Shawn Lin60cf09e2018-03-09 09:51:03 +0800231 mmc_clock->clk_rate_change_nb.notifier_call =
232 &rockchip_mmc_clk_rate_notify;
233 ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);
234 if (ret)
235 goto err_notifier;
236
237 return clk;
238err_notifier:
239 clk_unregister(clk);
240err_register:
241 kfree(mmc_clock);
Shawn Lin0d92d182018-03-21 10:39:20 +0800242 return ERR_PTR(ret);
Alexandru M Stan89bf26c2014-11-26 17:30:27 -0800243}