blob: 3d6000cd5048f8db24570685dcfa41ff1c9bf90a [file] [log] [blame]
Rob Clark16ea9752013-01-08 15:04:28 -06001/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
Rob Clarka464d612013-08-07 13:41:20 -040018#include "drm_flip_work.h"
Daniel Vetter3cb9ae42014-10-29 10:03:57 +010019#include <drm/drm_plane_helper.h>
Jyri Sarha305198d2016-04-07 15:05:16 +030020#include <drm/drm_atomic_helper.h>
Rob Clark16ea9752013-01-08 15:04:28 -060021
22#include "tilcdc_drv.h"
23#include "tilcdc_regs.h"
24
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +020025#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
26
Rob Clark16ea9752013-01-08 15:04:28 -060027struct tilcdc_crtc {
28 struct drm_crtc base;
29
Jyri Sarha47f571c2016-04-07 15:04:18 +030030 struct drm_plane primary;
Rob Clark16ea9752013-01-08 15:04:28 -060031 const struct tilcdc_panel_info *info;
Rob Clark16ea9752013-01-08 15:04:28 -060032 struct drm_pending_vblank_event *event;
33 int dpms;
34 wait_queue_head_t frame_done_wq;
35 bool frame_done;
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +020036 spinlock_t irq_lock;
37
38 ktime_t last_vblank;
Rob Clark16ea9752013-01-08 15:04:28 -060039
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030040 struct drm_framebuffer *curr_fb;
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +020041 struct drm_framebuffer *next_fb;
Rob Clark16ea9752013-01-08 15:04:28 -060042
43 /* for deferred fb unref's: */
Rob Clarka464d612013-08-07 13:41:20 -040044 struct drm_flip_work unref_work;
Jyri Sarha103cd8b2015-02-10 14:13:23 +020045
46 /* Only set if an external encoder is connected */
47 bool simulate_vesa_sync;
Jyri Sarha5895d082016-01-08 14:33:09 +020048
49 int sync_lost_count;
50 bool frame_intact;
Rob Clark16ea9752013-01-08 15:04:28 -060051};
52#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
53
Rob Clarka464d612013-08-07 13:41:20 -040054static void unref_worker(struct drm_flip_work *work, void *val)
Rob Clark16ea9752013-01-08 15:04:28 -060055{
Darren Etheridgef7b45752013-06-21 13:52:26 -050056 struct tilcdc_crtc *tilcdc_crtc =
Rob Clarka464d612013-08-07 13:41:20 -040057 container_of(work, struct tilcdc_crtc, unref_work);
Rob Clark16ea9752013-01-08 15:04:28 -060058 struct drm_device *dev = tilcdc_crtc->base.dev;
Rob Clark16ea9752013-01-08 15:04:28 -060059
60 mutex_lock(&dev->mode_config.mutex);
Rob Clarka464d612013-08-07 13:41:20 -040061 drm_framebuffer_unreference(val);
Rob Clark16ea9752013-01-08 15:04:28 -060062 mutex_unlock(&dev->mode_config.mutex);
63}
64
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030065static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
Rob Clark16ea9752013-01-08 15:04:28 -060066{
67 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
68 struct drm_device *dev = crtc->dev;
Rob Clark16ea9752013-01-08 15:04:28 -060069 struct drm_gem_cma_object *gem;
70 unsigned int depth, bpp;
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030071 dma_addr_t start, end;
Rob Clark16ea9752013-01-08 15:04:28 -060072
73 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
74 gem = drm_fb_cma_get_gem_obj(fb, 0);
75
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030076 start = gem->paddr + fb->offsets[0] +
77 crtc->y * fb->pitches[0] +
78 crtc->x * bpp / 8;
Rob Clark16ea9752013-01-08 15:04:28 -060079
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030080 end = start + (crtc->mode.vdisplay * fb->pitches[0]);
Rob Clark16ea9752013-01-08 15:04:28 -060081
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +030082 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
83 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
84
85 if (tilcdc_crtc->curr_fb)
86 drm_flip_work_queue(&tilcdc_crtc->unref_work,
87 tilcdc_crtc->curr_fb);
88
89 tilcdc_crtc->curr_fb = fb;
Rob Clark16ea9752013-01-08 15:04:28 -060090}
91
Tomi Valkeinen2efec4f2015-10-20 09:37:27 +030092static void reset(struct drm_crtc *crtc)
Rob Clark16ea9752013-01-08 15:04:28 -060093{
94 struct drm_device *dev = crtc->dev;
95 struct tilcdc_drm_private *priv = dev->dev_private;
96
Tomi Valkeinen2efec4f2015-10-20 09:37:27 +030097 if (priv->rev != 2)
98 return;
99
100 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
101 usleep_range(250, 1000);
102 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
103}
104
105static void start(struct drm_crtc *crtc)
106{
107 struct drm_device *dev = crtc->dev;
108
109 reset(crtc);
Rob Clark16ea9752013-01-08 15:04:28 -0600110
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300111 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
Rob Clark16ea9752013-01-08 15:04:28 -0600112 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
113 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
Jyri Sarhad85f850e2016-06-15 11:16:23 +0300114
115 drm_crtc_vblank_on(crtc);
Rob Clark16ea9752013-01-08 15:04:28 -0600116}
117
118static void stop(struct drm_crtc *crtc)
119{
Jyri Sarha2d5be882016-04-07 20:20:23 +0300120 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
Rob Clark16ea9752013-01-08 15:04:28 -0600121 struct drm_device *dev = crtc->dev;
Jyri Sarha2d5be882016-04-07 20:20:23 +0300122 struct tilcdc_drm_private *priv = dev->dev_private;
Rob Clark16ea9752013-01-08 15:04:28 -0600123
Jyri Sarha2d5be882016-04-07 20:20:23 +0300124 tilcdc_crtc->frame_done = false;
Rob Clark16ea9752013-01-08 15:04:28 -0600125 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
Jyri Sarha2d5be882016-04-07 20:20:23 +0300126
127 /*
128 * if necessary wait for framedone irq which will still come
129 * before putting things to sleep..
130 */
131 if (priv->rev == 2) {
132 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
133 tilcdc_crtc->frame_done,
Jyri Sarha437c7d92016-06-16 16:19:17 +0300134 msecs_to_jiffies(500));
Jyri Sarha2d5be882016-04-07 20:20:23 +0300135 if (ret == 0)
136 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
137 __func__);
138 }
Jyri Sarhad85f850e2016-06-15 11:16:23 +0300139
140 drm_crtc_vblank_off(crtc);
Rob Clark16ea9752013-01-08 15:04:28 -0600141}
142
143static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
144{
145 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
146
Jyri Sarhade9cb5f2015-02-26 10:12:41 +0200147 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
Rob Clark16ea9752013-01-08 15:04:28 -0600148
Jyri Sarhad66284fb2015-05-27 11:58:37 +0300149 of_node_put(crtc->port);
Rob Clark16ea9752013-01-08 15:04:28 -0600150 drm_crtc_cleanup(crtc);
Rob Clarka464d612013-08-07 13:41:20 -0400151 drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
Rob Clark16ea9752013-01-08 15:04:28 -0600152}
153
Jyri Sarha8c65abb2016-04-07 14:56:32 +0300154int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
Rob Clark16ea9752013-01-08 15:04:28 -0600155 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700156 struct drm_pending_vblank_event *event,
157 uint32_t page_flip_flags)
Rob Clark16ea9752013-01-08 15:04:28 -0600158{
159 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
160 struct drm_device *dev = crtc->dev;
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300161 unsigned long flags;
Tomi Valkeinen6f206e92014-02-07 17:37:07 +0000162
Rob Clark16ea9752013-01-08 15:04:28 -0600163 if (tilcdc_crtc->event) {
164 dev_err(dev->dev, "already pending page flip!\n");
165 return -EBUSY;
166 }
167
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300168 drm_framebuffer_reference(fb);
169
Matt Roperf4510a22014-04-01 15:22:40 -0700170 crtc->primary->fb = fb;
Tomi Valkeinen65734a22015-10-19 12:30:03 +0300171
172 pm_runtime_get_sync(dev->dev);
173
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200174 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300175
Jyri Sarha0a1fe1b2016-06-13 09:53:36 +0300176 if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
177 ktime_t next_vblank;
178 s64 tdiff;
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300179
Jyri Sarha0a1fe1b2016-06-13 09:53:36 +0300180 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
181 1000000 / crtc->hwmode.vrefresh);
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200182
Jyri Sarha0a1fe1b2016-06-13 09:53:36 +0300183 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
184
185 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
186 tilcdc_crtc->next_fb = fb;
187 }
188
189 if (tilcdc_crtc->next_fb != fb)
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200190 set_scanout(crtc, fb);
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200191
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300192 tilcdc_crtc->event = event;
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200193
194 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
Rob Clark16ea9752013-01-08 15:04:28 -0600195
Tomi Valkeinen65734a22015-10-19 12:30:03 +0300196 pm_runtime_put_sync(dev->dev);
197
Rob Clark16ea9752013-01-08 15:04:28 -0600198 return 0;
199}
200
Darren Etheridge614b3cfe2014-09-25 00:59:32 +0000201void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
Rob Clark16ea9752013-01-08 15:04:28 -0600202{
203 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
204 struct drm_device *dev = crtc->dev;
205 struct tilcdc_drm_private *priv = dev->dev_private;
206
207 /* we really only care about on or off: */
208 if (mode != DRM_MODE_DPMS_ON)
209 mode = DRM_MODE_DPMS_OFF;
210
211 if (tilcdc_crtc->dpms == mode)
212 return;
213
214 tilcdc_crtc->dpms = mode;
215
Rob Clark16ea9752013-01-08 15:04:28 -0600216 if (mode == DRM_MODE_DPMS_ON) {
Tomi Valkeinen65734a22015-10-19 12:30:03 +0300217 pm_runtime_get_sync(dev->dev);
Rob Clark16ea9752013-01-08 15:04:28 -0600218 start(crtc);
219 } else {
Rob Clark16ea9752013-01-08 15:04:28 -0600220 stop(crtc);
Tomi Valkeinen65734a22015-10-19 12:30:03 +0300221 pm_runtime_put_sync(dev->dev);
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300222
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200223 if (tilcdc_crtc->next_fb) {
224 drm_flip_work_queue(&tilcdc_crtc->unref_work,
225 tilcdc_crtc->next_fb);
226 tilcdc_crtc->next_fb = NULL;
227 }
228
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300229 if (tilcdc_crtc->curr_fb) {
230 drm_flip_work_queue(&tilcdc_crtc->unref_work,
231 tilcdc_crtc->curr_fb);
232 tilcdc_crtc->curr_fb = NULL;
233 }
234
235 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
Jyri Sarha0a1fe1b2016-06-13 09:53:36 +0300236 tilcdc_crtc->last_vblank = ktime_set(0, 0);
Tomi Valkeinen65734a22015-10-19 12:30:03 +0300237 }
Rob Clark16ea9752013-01-08 15:04:28 -0600238}
239
Jyri Sarha8fe56162016-06-14 11:43:30 +0300240int tilcdc_crtc_current_dpms_state(struct drm_crtc *crtc)
241{
242 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
243
244 return tilcdc_crtc->dpms;
245}
246
Rob Clark16ea9752013-01-08 15:04:28 -0600247static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
248 const struct drm_display_mode *mode,
249 struct drm_display_mode *adjusted_mode)
250{
Jyri Sarha103cd8b2015-02-10 14:13:23 +0200251 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
252
253 if (!tilcdc_crtc->simulate_vesa_sync)
254 return true;
255
256 /*
257 * tilcdc does not generate VESA-compliant sync but aligns
258 * VS on the second edge of HS instead of first edge.
259 * We use adjusted_mode, to fixup sync by aligning both rising
260 * edges and add HSKEW offset to fix the sync.
261 */
262 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
263 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
264
265 if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
266 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
267 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
268 } else {
269 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
270 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
271 }
272
Rob Clark16ea9752013-01-08 15:04:28 -0600273 return true;
274}
275
Jyri Sarha305198d2016-04-07 15:05:16 +0300276static void tilcdc_crtc_disable(struct drm_crtc *crtc)
Rob Clark16ea9752013-01-08 15:04:28 -0600277{
278 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
279}
280
Jyri Sarha305198d2016-04-07 15:05:16 +0300281static void tilcdc_crtc_enable(struct drm_crtc *crtc)
Rob Clark16ea9752013-01-08 15:04:28 -0600282{
283 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
284}
285
Jyri Sarhaf6382f12016-04-07 15:09:50 +0300286static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
287{
288 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
289 struct drm_device *dev = crtc->dev;
290 struct tilcdc_drm_private *priv = dev->dev_private;
291 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
292 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
293 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
294 struct drm_framebuffer *fb = crtc->primary->state->fb;
295
296 if (WARN_ON(!info))
297 return;
298
299 if (WARN_ON(!fb))
300 return;
301
302 pm_runtime_get_sync(dev->dev);
303
304 /* Configure the Burst Size and fifo threshold of DMA: */
305 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
306 switch (info->dma_burst_sz) {
307 case 1:
308 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
309 break;
310 case 2:
311 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
312 break;
313 case 4:
314 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
315 break;
316 case 8:
317 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
318 break;
319 case 16:
320 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
321 break;
322 default:
323 dev_err(dev->dev, "invalid burst size\n");
324 return;
325 }
326 reg |= (info->fifo_th << 8);
327 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
328
329 /* Configure timings: */
330 hbp = mode->htotal - mode->hsync_end;
331 hfp = mode->hsync_start - mode->hdisplay;
332 hsw = mode->hsync_end - mode->hsync_start;
333 vbp = mode->vtotal - mode->vsync_end;
334 vfp = mode->vsync_start - mode->vdisplay;
335 vsw = mode->vsync_end - mode->vsync_start;
336
337 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
338 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
339
340 /* Set AC Bias Period and Number of Transitions per Interrupt: */
341 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
342 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
343 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
344
345 /*
346 * subtract one from hfp, hbp, hsw because the hardware uses
347 * a value of 0 as 1
348 */
349 if (priv->rev == 2) {
350 /* clear bits we're going to set */
351 reg &= ~0x78000033;
352 reg |= ((hfp-1) & 0x300) >> 8;
353 reg |= ((hbp-1) & 0x300) >> 4;
354 reg |= ((hsw-1) & 0x3c0) << 21;
355 }
356 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
357
358 reg = (((mode->hdisplay >> 4) - 1) << 4) |
359 (((hbp-1) & 0xff) << 24) |
360 (((hfp-1) & 0xff) << 16) |
361 (((hsw-1) & 0x3f) << 10);
362 if (priv->rev == 2)
363 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
364 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
365
366 reg = ((mode->vdisplay - 1) & 0x3ff) |
367 ((vbp & 0xff) << 24) |
368 ((vfp & 0xff) << 16) |
369 (((vsw-1) & 0x3f) << 10);
370 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
371
372 /*
373 * be sure to set Bit 10 for the V2 LCDC controller,
374 * otherwise limited to 1024 pixels width, stopping
375 * 1920x1080 being supported.
376 */
377 if (priv->rev == 2) {
378 if ((mode->vdisplay - 1) & 0x400) {
379 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
380 LCDC_LPP_B10);
381 } else {
382 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
383 LCDC_LPP_B10);
384 }
385 }
386
387 /* Configure display type: */
388 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
389 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
390 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
391 0x000ff000 /* Palette Loading Delay bits */);
392 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
393 if (info->tft_alt_mode)
394 reg |= LCDC_TFT_ALT_ENABLE;
395 if (priv->rev == 2) {
396 unsigned int depth, bpp;
397
398 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
399 switch (bpp) {
400 case 16:
401 break;
402 case 32:
403 reg |= LCDC_V2_TFT_24BPP_UNPACK;
404 /* fallthrough */
405 case 24:
406 reg |= LCDC_V2_TFT_24BPP_MODE;
407 break;
408 default:
409 dev_err(dev->dev, "invalid pixel format\n");
410 return;
411 }
412 }
413 reg |= info->fdd < 12;
414 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
415
416 if (info->invert_pxl_clk)
417 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
418 else
419 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
420
421 if (info->sync_ctrl)
422 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
423 else
424 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
425
426 if (info->sync_edge)
427 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
428 else
429 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
430
431 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
432 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
433 else
434 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
435
436 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
437 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
438 else
439 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
440
441 if (info->raster_order)
442 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
443 else
444 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
445
446 drm_framebuffer_reference(fb);
447
448 set_scanout(crtc, fb);
449
450 tilcdc_crtc_update_clk(crtc);
451
452 pm_runtime_put_sync(dev->dev);
453
454 crtc->hwmode = crtc->state->adjusted_mode;
455}
456
Jyri Sarhadb380c52016-04-07 15:10:23 +0300457static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
458 struct drm_crtc_state *state)
459{
460 struct drm_display_mode *mode = &state->mode;
461 int ret;
462
463 /* If we are not active we don't care */
464 if (!state->active)
465 return 0;
466
467 if (state->state->planes[0].ptr != crtc->primary ||
468 state->state->planes[0].state == NULL ||
469 state->state->planes[0].state->crtc != crtc) {
470 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
471 return -EINVAL;
472 }
473
474 ret = tilcdc_crtc_mode_valid(crtc, mode);
475 if (ret) {
476 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
477 return -EINVAL;
478 }
479
480 return 0;
481}
482
Rob Clark16ea9752013-01-08 15:04:28 -0600483static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
Jyri Sarha305198d2016-04-07 15:05:16 +0300484 .destroy = tilcdc_crtc_destroy,
485 .set_config = drm_atomic_helper_set_config,
486 .page_flip = drm_atomic_helper_page_flip,
487 .reset = drm_atomic_helper_crtc_reset,
488 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
489 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
Rob Clark16ea9752013-01-08 15:04:28 -0600490};
491
492static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
Rob Clark16ea9752013-01-08 15:04:28 -0600493 .mode_fixup = tilcdc_crtc_mode_fixup,
Jyri Sarha305198d2016-04-07 15:05:16 +0300494 .enable = tilcdc_crtc_enable,
495 .disable = tilcdc_crtc_disable,
Jyri Sarhadb380c52016-04-07 15:10:23 +0300496 .atomic_check = tilcdc_crtc_atomic_check,
Jyri Sarhaf6382f12016-04-07 15:09:50 +0300497 .mode_set_nofb = tilcdc_crtc_mode_set_nofb,
Rob Clark16ea9752013-01-08 15:04:28 -0600498};
499
500int tilcdc_crtc_max_width(struct drm_crtc *crtc)
501{
502 struct drm_device *dev = crtc->dev;
503 struct tilcdc_drm_private *priv = dev->dev_private;
504 int max_width = 0;
505
506 if (priv->rev == 1)
507 max_width = 1024;
508 else if (priv->rev == 2)
509 max_width = 2048;
510
511 return max_width;
512}
513
514int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
515{
516 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
517 unsigned int bandwidth;
Darren Etheridgee1c5d0a2013-06-21 13:52:25 -0500518 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
Rob Clark16ea9752013-01-08 15:04:28 -0600519
Darren Etheridgee1c5d0a2013-06-21 13:52:25 -0500520 /*
521 * check to see if the width is within the range that
522 * the LCD Controller physically supports
523 */
Rob Clark16ea9752013-01-08 15:04:28 -0600524 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
525 return MODE_VIRTUAL_X;
526
527 /* width must be multiple of 16 */
528 if (mode->hdisplay & 0xf)
529 return MODE_VIRTUAL_X;
530
531 if (mode->vdisplay > 2048)
532 return MODE_VIRTUAL_Y;
533
Darren Etheridgee1c5d0a2013-06-21 13:52:25 -0500534 DBG("Processing mode %dx%d@%d with pixel clock %d",
535 mode->hdisplay, mode->vdisplay,
536 drm_mode_vrefresh(mode), mode->clock);
537
538 hbp = mode->htotal - mode->hsync_end;
539 hfp = mode->hsync_start - mode->hdisplay;
540 hsw = mode->hsync_end - mode->hsync_start;
541 vbp = mode->vtotal - mode->vsync_end;
542 vfp = mode->vsync_start - mode->vdisplay;
543 vsw = mode->vsync_end - mode->vsync_start;
544
545 if ((hbp-1) & ~0x3ff) {
546 DBG("Pruning mode: Horizontal Back Porch out of range");
547 return MODE_HBLANK_WIDE;
548 }
549
550 if ((hfp-1) & ~0x3ff) {
551 DBG("Pruning mode: Horizontal Front Porch out of range");
552 return MODE_HBLANK_WIDE;
553 }
554
555 if ((hsw-1) & ~0x3ff) {
556 DBG("Pruning mode: Horizontal Sync Width out of range");
557 return MODE_HSYNC_WIDE;
558 }
559
560 if (vbp & ~0xff) {
561 DBG("Pruning mode: Vertical Back Porch out of range");
562 return MODE_VBLANK_WIDE;
563 }
564
565 if (vfp & ~0xff) {
566 DBG("Pruning mode: Vertical Front Porch out of range");
567 return MODE_VBLANK_WIDE;
568 }
569
570 if ((vsw-1) & ~0x3f) {
571 DBG("Pruning mode: Vertical Sync Width out of range");
572 return MODE_VSYNC_WIDE;
573 }
574
Darren Etheridge4e564342013-06-21 13:52:23 -0500575 /*
576 * some devices have a maximum allowed pixel clock
577 * configured from the DT
578 */
579 if (mode->clock > priv->max_pixelclock) {
Darren Etheridgef7b45752013-06-21 13:52:26 -0500580 DBG("Pruning mode: pixel clock too high");
Darren Etheridge4e564342013-06-21 13:52:23 -0500581 return MODE_CLOCK_HIGH;
582 }
583
584 /*
585 * some devices further limit the max horizontal resolution
586 * configured from the DT
587 */
588 if (mode->hdisplay > priv->max_width)
589 return MODE_BAD_WIDTH;
590
Rob Clark16ea9752013-01-08 15:04:28 -0600591 /* filter out modes that would require too much memory bandwidth: */
Darren Etheridge4e564342013-06-21 13:52:23 -0500592 bandwidth = mode->hdisplay * mode->vdisplay *
593 drm_mode_vrefresh(mode);
594 if (bandwidth > priv->max_bandwidth) {
Darren Etheridgef7b45752013-06-21 13:52:26 -0500595 DBG("Pruning mode: exceeds defined bandwidth limit");
Rob Clark16ea9752013-01-08 15:04:28 -0600596 return MODE_BAD;
Darren Etheridge4e564342013-06-21 13:52:23 -0500597 }
Rob Clark16ea9752013-01-08 15:04:28 -0600598
599 return MODE_OK;
600}
601
602void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
603 const struct tilcdc_panel_info *info)
604{
605 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
606 tilcdc_crtc->info = info;
607}
608
Jyri Sarha103cd8b2015-02-10 14:13:23 +0200609void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
610 bool simulate_vesa_sync)
611{
612 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
613
614 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
615}
616
Rob Clark16ea9752013-01-08 15:04:28 -0600617void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
618{
619 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
620 struct drm_device *dev = crtc->dev;
621 struct tilcdc_drm_private *priv = dev->dev_private;
622 int dpms = tilcdc_crtc->dpms;
Darren Etheridge3d193062014-01-15 15:52:36 -0600623 unsigned long lcd_clk;
624 const unsigned clkdiv = 2; /* using a fixed divider of 2 */
Rob Clark16ea9752013-01-08 15:04:28 -0600625 int ret;
626
627 pm_runtime_get_sync(dev->dev);
628
629 if (dpms == DRM_MODE_DPMS_ON)
630 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
631
Darren Etheridge3d193062014-01-15 15:52:36 -0600632 /* mode.clock is in KHz, set_rate wants parameter in Hz */
633 ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
634 if (ret < 0) {
Rob Clark16ea9752013-01-08 15:04:28 -0600635 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
636 crtc->mode.clock);
637 goto out;
638 }
639
640 lcd_clk = clk_get_rate(priv->clk);
Rob Clark16ea9752013-01-08 15:04:28 -0600641
Darren Etheridge3d193062014-01-15 15:52:36 -0600642 DBG("lcd_clk=%lu, mode clock=%d, div=%u",
643 lcd_clk, crtc->mode.clock, clkdiv);
Rob Clark16ea9752013-01-08 15:04:28 -0600644
645 /* Configure the LCD clock divisor. */
Darren Etheridge3d193062014-01-15 15:52:36 -0600646 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
Rob Clark16ea9752013-01-08 15:04:28 -0600647 LCDC_RASTER_MODE);
648
649 if (priv->rev == 2)
650 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
651 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
652 LCDC_V2_CORE_CLK_EN);
653
654 if (dpms == DRM_MODE_DPMS_ON)
655 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
656
657out:
658 pm_runtime_put_sync(dev->dev);
659}
660
Jyri Sarha5895d082016-01-08 14:33:09 +0200661#define SYNC_LOST_COUNT_LIMIT 50
662
Rob Clark16ea9752013-01-08 15:04:28 -0600663irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
664{
665 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
666 struct drm_device *dev = crtc->dev;
667 struct tilcdc_drm_private *priv = dev->dev_private;
Tomi Valkeinen317aae72015-10-20 12:08:03 +0300668 uint32_t stat;
Rob Clark16ea9752013-01-08 15:04:28 -0600669
Tomi Valkeinen317aae72015-10-20 12:08:03 +0300670 stat = tilcdc_read_irqstatus(dev);
671 tilcdc_clear_irqstatus(dev, stat);
672
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300673 if (stat & LCDC_END_OF_FRAME0) {
Rob Clark16ea9752013-01-08 15:04:28 -0600674 unsigned long flags;
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200675 bool skip_event = false;
676 ktime_t now;
677
678 now = ktime_get();
Rob Clark16ea9752013-01-08 15:04:28 -0600679
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300680 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
Rob Clark16ea9752013-01-08 15:04:28 -0600681
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200682 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
Rob Clark16ea9752013-01-08 15:04:28 -0600683
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200684 tilcdc_crtc->last_vblank = now;
Rob Clark16ea9752013-01-08 15:04:28 -0600685
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200686 if (tilcdc_crtc->next_fb) {
687 set_scanout(crtc, tilcdc_crtc->next_fb);
688 tilcdc_crtc->next_fb = NULL;
689 skip_event = true;
Tomi Valkeinen2b2080d72015-10-20 09:37:27 +0300690 }
691
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200692 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
693
Gustavo Padovan099ede82016-07-04 21:04:52 -0300694 drm_crtc_handle_vblank(crtc);
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200695
696 if (!skip_event) {
697 struct drm_pending_vblank_event *event;
698
699 spin_lock_irqsave(&dev->event_lock, flags);
700
701 event = tilcdc_crtc->event;
702 tilcdc_crtc->event = NULL;
703 if (event)
Gustavo Padovandfebc152016-04-14 10:48:22 -0700704 drm_crtc_send_vblank_event(crtc, event);
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200705
706 spin_unlock_irqrestore(&dev->event_lock, flags);
707 }
Jyri Sarha5895d082016-01-08 14:33:09 +0200708
709 if (tilcdc_crtc->frame_intact)
710 tilcdc_crtc->sync_lost_count = 0;
711 else
712 tilcdc_crtc->frame_intact = true;
Rob Clark16ea9752013-01-08 15:04:28 -0600713 }
714
Jyri Sarha14944112016-04-07 20:36:48 +0300715 if (stat & LCDC_FIFO_UNDERFLOW)
716 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
717 __func__, stat);
718
719 /* For revision 2 only */
Rob Clark16ea9752013-01-08 15:04:28 -0600720 if (priv->rev == 2) {
721 if (stat & LCDC_FRAME_DONE) {
722 tilcdc_crtc->frame_done = true;
723 wake_up(&tilcdc_crtc->frame_done_wq);
724 }
Rob Clark16ea9752013-01-08 15:04:28 -0600725
Jyri Sarha1abcdac2016-06-17 11:54:06 +0300726 if (stat & LCDC_SYNC_LOST) {
727 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
728 __func__, stat);
729 tilcdc_crtc->frame_intact = false;
730 if (tilcdc_crtc->sync_lost_count++ >
731 SYNC_LOST_COUNT_LIMIT) {
732 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
733 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
734 LCDC_SYNC_LOST);
735 }
Jyri Sarha5895d082016-01-08 14:33:09 +0200736 }
Jyri Sarhac0c2baa2015-12-18 13:07:52 +0200737
Jyri Sarha14944112016-04-07 20:36:48 +0300738 /* Indicate to LCDC that the interrupt service routine has
739 * completed, see 13.3.6.1.6 in AM335x TRM.
740 */
741 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
742 }
Jyri Sarhac0c2baa2015-12-18 13:07:52 +0200743
Rob Clark16ea9752013-01-08 15:04:28 -0600744 return IRQ_HANDLED;
745}
746
Rob Clark16ea9752013-01-08 15:04:28 -0600747struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
748{
Jyri Sarhad66284fb2015-05-27 11:58:37 +0300749 struct tilcdc_drm_private *priv = dev->dev_private;
Rob Clark16ea9752013-01-08 15:04:28 -0600750 struct tilcdc_crtc *tilcdc_crtc;
751 struct drm_crtc *crtc;
752 int ret;
753
Jyri Sarhad0ec32c2016-02-23 12:44:27 +0200754 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
Rob Clark16ea9752013-01-08 15:04:28 -0600755 if (!tilcdc_crtc) {
756 dev_err(dev->dev, "allocation failed\n");
757 return NULL;
758 }
759
760 crtc = &tilcdc_crtc->base;
761
Jyri Sarha47f571c2016-04-07 15:04:18 +0300762 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
763 if (ret < 0)
764 goto fail;
765
Rob Clark16ea9752013-01-08 15:04:28 -0600766 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
767 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
768
Boris BREZILLONd7f8db52014-11-14 19:30:30 +0100769 drm_flip_work_init(&tilcdc_crtc->unref_work,
Rob Clarka464d612013-08-07 13:41:20 -0400770 "unref", unref_worker);
Rob Clark16ea9752013-01-08 15:04:28 -0600771
Tomi Valkeinen2b3a8cd2015-11-03 12:00:51 +0200772 spin_lock_init(&tilcdc_crtc->irq_lock);
773
Jyri Sarha47f571c2016-04-07 15:04:18 +0300774 ret = drm_crtc_init_with_planes(dev, crtc,
775 &tilcdc_crtc->primary,
776 NULL,
777 &tilcdc_crtc_funcs,
778 "tilcdc crtc");
Rob Clark16ea9752013-01-08 15:04:28 -0600779 if (ret < 0)
780 goto fail;
781
782 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
783
Jyri Sarhad66284fb2015-05-27 11:58:37 +0300784 if (priv->is_componentized) {
785 struct device_node *ports =
786 of_get_child_by_name(dev->dev->of_node, "ports");
787
788 if (ports) {
789 crtc->port = of_get_child_by_name(ports, "port");
790 of_node_put(ports);
791 } else {
792 crtc->port =
793 of_get_child_by_name(dev->dev->of_node, "port");
794 }
795 if (!crtc->port) { /* This should never happen */
796 dev_err(dev->dev, "Port node not found in %s\n",
797 dev->dev->of_node->full_name);
798 goto fail;
799 }
800 }
801
Rob Clark16ea9752013-01-08 15:04:28 -0600802 return crtc;
803
804fail:
805 tilcdc_crtc_destroy(crtc);
806 return NULL;
807}