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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07002#ifndef LINUX_MSI_H
3#define LINUX_MSI_H
4
Neil Hormanb50cac52011-10-06 14:08:18 -04005#include <linux/kobject.h>
Michael Ellerman4aa9bc92007-04-05 17:19:10 +10006#include <linux/list.h>
7
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07008struct msi_msg {
9 u32 address_lo; /* low 32 bits of msi message address */
10 u32 address_hi; /* high 32 bits of msi message address */
11 u32 data; /* 16 bits of msi message data */
12};
13
Yijing Wang38737d82014-10-27 10:44:36 +080014extern int pci_msi_ignore_mask;
Satoru Takeuchic54c1872007-01-18 13:50:05 +090015/* Helper functions */
Thomas Gleixner1c9db522010-09-28 16:46:51 +020016struct irq_data;
Thomas Gleixner39431ac2010-09-28 19:09:51 +020017struct msi_desc;
Jiang Liu25a98bd2015-07-09 16:00:45 +080018struct pci_dev;
Marc Zyngierc09fcc4b2015-07-28 14:46:16 +010019struct platform_msi_priv_data;
Bjorn Helgaas2366d062013-04-18 10:55:46 -060020void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
Arnd Bergmann2f44e292017-02-14 22:53:12 +010021#ifdef CONFIG_GENERIC_MSI_IRQ
Bjorn Helgaas2366d062013-04-18 10:55:46 -060022void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
Arnd Bergmann2f44e292017-02-14 22:53:12 +010023#else
24static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
25{
26}
27#endif
Jiang Liu891d4a42014-11-09 23:10:33 +080028
Marc Zyngierc09fcc4b2015-07-28 14:46:16 +010029typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
30 struct msi_msg *msg);
31
32/**
33 * platform_msi_desc - Platform device specific msi descriptor data
34 * @msi_priv_data: Pointer to platform private data
35 * @msi_index: The index of the MSI descriptor for multi MSI
36 */
37struct platform_msi_desc {
38 struct platform_msi_priv_data *msi_priv_data;
39 u16 msi_index;
40};
41
Jiang Liufc884192015-07-09 16:00:46 +080042/**
J. German Rivera550308e2016-01-06 16:03:20 -060043 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
44 * @msi_index: The index of the MSI descriptor
45 */
46struct fsl_mc_msi_desc {
47 u16 msi_index;
48};
49
50/**
Lokesh Vutla49b32312019-04-30 15:42:28 +053051 * ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
52 * @dev_index: TISCI device index
53 */
54struct ti_sci_inta_msi_desc {
55 u16 dev_index;
56};
57
58/**
Jiang Liufc884192015-07-09 16:00:46 +080059 * struct msi_desc - Descriptor structure for MSI based interrupts
60 * @list: List head for management
61 * @irq: The base interrupt number
62 * @nvec_used: The number of vectors used
63 * @dev: Pointer to the device which uses this descriptor
64 * @msg: The last set MSI message cached for reuse
Thomas Gleixner0972fa52016-07-04 17:39:26 +090065 * @affinity: Optional pointer to a cpu affinity mask for this descriptor
Jiang Liufc884192015-07-09 16:00:46 +080066 *
67 * @masked: [PCI MSI/X] Mask bits
68 * @is_msix: [PCI MSI/X] True if MSI-X
69 * @multiple: [PCI MSI/X] log2 num of messages allocated
70 * @multi_cap: [PCI MSI/X] log2 num of messages supported
71 * @maskbit: [PCI MSI/X] Mask-Pending bit supported?
72 * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
73 * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
74 * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
75 * @mask_pos: [PCI MSI] Mask register position
76 * @mask_base: [PCI MSI-X] Mask register base address
Marc Zyngierc09fcc4b2015-07-28 14:46:16 +010077 * @platform: [platform] Platform device specific msi descriptor data
Laurentiu Tudor87840fb2017-07-19 14:42:25 +030078 * @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
Lokesh Vutla49b32312019-04-30 15:42:28 +053079 * @inta: [INTA] TISCI based INTA specific msi descriptor data
Jiang Liufc884192015-07-09 16:00:46 +080080 */
Eric W. Biederman3b7d1922006-10-04 02:16:59 -070081struct msi_desc {
Jiang Liufc884192015-07-09 16:00:46 +080082 /* Shared device/bus type independent data */
83 struct list_head list;
84 unsigned int irq;
85 unsigned int nvec_used;
86 struct device *dev;
87 struct msi_msg msg;
Dou Liyangbec04032018-12-04 23:51:20 +080088 struct irq_affinity_desc *affinity;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -070089
Matthew Wilcox264d9ca2009-03-17 08:54:08 -040090 union {
Jiang Liufc884192015-07-09 16:00:46 +080091 /* PCI MSI/X specific data */
92 struct {
93 u32 masked;
94 struct {
Logan Gunthorpeddd065e2019-02-08 09:54:38 -070095 u8 is_msix : 1;
96 u8 multiple : 3;
97 u8 multi_cap : 3;
98 u8 maskbit : 1;
99 u8 is_64 : 1;
100 u16 entry_nr;
Jiang Liufc884192015-07-09 16:00:46 +0800101 unsigned default_irq;
102 } msi_attrib;
103 union {
104 u8 mask_pos;
105 void __iomem *mask_base;
106 };
107 };
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700108
Jiang Liufc884192015-07-09 16:00:46 +0800109 /*
110 * Non PCI variants add their data structure here. New
111 * entries need to use a named structure. We want
112 * proper name spaces for this. The PCI part is
113 * anonymous for now as it would require an immediate
114 * tree wide cleanup.
115 */
Marc Zyngierc09fcc4b2015-07-28 14:46:16 +0100116 struct platform_msi_desc platform;
J. German Rivera550308e2016-01-06 16:03:20 -0600117 struct fsl_mc_msi_desc fsl_mc;
Lokesh Vutla49b32312019-04-30 15:42:28 +0530118 struct ti_sci_inta_msi_desc inta;
Jiang Liufc884192015-07-09 16:00:46 +0800119 };
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700120};
121
Jiang Liud31eb342014-11-15 22:24:03 +0800122/* Helpers to hide struct msi_desc implementation details */
Jiang Liu25a98bd2015-07-09 16:00:45 +0800123#define msi_desc_to_dev(desc) ((desc)->dev)
Jiang Liu4a7cc832015-07-09 16:00:44 +0800124#define dev_to_msi_list(dev) (&(dev)->msi_list)
Jiang Liud31eb342014-11-15 22:24:03 +0800125#define first_msi_entry(dev) \
126 list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
127#define for_each_msi_entry(desc, dev) \
128 list_for_each_entry((desc), dev_to_msi_list((dev)), list)
Miquel Raynal81b1e6e2018-10-11 11:12:34 +0200129#define for_each_msi_entry_safe(desc, tmp, dev) \
130 list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)
Jiang Liud31eb342014-11-15 22:24:03 +0800131
132#ifdef CONFIG_PCI_MSI
133#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
134#define for_each_pci_msi_entry(desc, pdev) \
135 for_each_msi_entry((desc), &(pdev)->dev)
136
Jiang Liu25a98bd2015-07-09 16:00:45 +0800137struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc);
Jiang Liuc179c9b2015-07-09 16:00:36 +0800138void *msi_desc_to_pci_sysdata(struct msi_desc *desc);
Arnd Bergmann2f44e292017-02-14 22:53:12 +0100139void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
Jiang Liuc179c9b2015-07-09 16:00:36 +0800140#else /* CONFIG_PCI_MSI */
141static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
142{
143 return NULL;
144}
Arnd Bergmann2f44e292017-02-14 22:53:12 +0100145static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
146{
147}
Jiang Liud31eb342014-11-15 22:24:03 +0800148#endif /* CONFIG_PCI_MSI */
149
Thomas Gleixner28f4b042016-09-14 16:18:47 +0200150struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
Dou Liyangbec04032018-12-04 23:51:20 +0800151 const struct irq_affinity_desc *affinity);
Jiang Liuaa48b6f2015-07-09 16:00:47 +0800152void free_msi_entry(struct msi_desc *entry);
Jiang Liu891d4a42014-11-09 23:10:33 +0800153void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
Jiang Liu83a18912014-11-09 23:10:34 +0800154void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
Jiang Liu83a18912014-11-09 23:10:34 +0800155
Thomas Gleixner23ed8d52014-11-23 11:55:58 +0100156u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
157u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
158void pci_msi_mask_irq(struct irq_data *data);
159void pci_msi_unmask_irq(struct irq_data *data);
160
Jiang Liu83a18912014-11-09 23:10:34 +0800161/* Conversion helpers. Should be removed after merging */
162static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
163{
164 __pci_write_msi_msg(entry, msg);
165}
166static inline void write_msi_msg(int irq, struct msi_msg *msg)
167{
168 pci_write_msi_msg(irq, msg);
169}
Thomas Gleixner23ed8d52014-11-23 11:55:58 +0100170static inline void mask_msi_irq(struct irq_data *data)
171{
172 pci_msi_mask_irq(data);
173}
174static inline void unmask_msi_irq(struct irq_data *data)
175{
176 pci_msi_unmask_irq(data);
177}
Jiang Liu891d4a42014-11-09 23:10:33 +0800178
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700179/*
Thomas Petazzoni4287d822013-08-09 22:27:06 +0200180 * The arch hooks to setup up msi irqs. Those functions are
181 * implemented as weak symbols so that they /can/ be overriden by
182 * architecture specific code if needed.
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700183 */
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -0700184int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700185void arch_teardown_msi_irq(unsigned int irq);
Bjorn Helgaas2366d062013-04-18 10:55:46 -0600186int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
187void arch_teardown_msi_irqs(struct pci_dev *dev);
DuanZhenzhongac8344c2013-12-04 13:09:16 +0800188void arch_restore_msi_irqs(struct pci_dev *dev);
Thomas Petazzoni4287d822013-08-09 22:27:06 +0200189
190void default_teardown_msi_irqs(struct pci_dev *dev);
DuanZhenzhongac8344c2013-12-04 13:09:16 +0800191void default_restore_msi_irqs(struct pci_dev *dev);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700192
Yijing Wangc2791b82014-11-11 17:45:45 -0700193struct msi_controller {
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200194 struct module *owner;
195 struct device *dev;
Thomas Petazzoni0d5a6db2013-08-09 22:27:09 +0200196 struct device_node *of_node;
197 struct list_head list;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200198
Yijing Wangc2791b82014-11-11 17:45:45 -0700199 int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev,
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200200 struct msi_desc *desc);
Lucas Stach339e5b42015-09-18 13:58:34 -0500201 int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev,
202 int nvec, int type);
Yijing Wangc2791b82014-11-11 17:45:45 -0700203 void (*teardown_irq)(struct msi_controller *chip, unsigned int irq);
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200204};
205
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100206#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
Jiang Liud9109692014-11-15 22:24:04 +0800207
Jiang Liuaeeb5962014-11-15 22:24:05 +0800208#include <linux/irqhandler.h>
Jiang Liud9109692014-11-15 22:24:04 +0800209#include <asm/msi.h>
210
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100211struct irq_domain;
Marc Zyngier552c4942015-11-23 08:26:07 +0000212struct irq_domain_ops;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100213struct irq_chip;
214struct device_node;
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100215struct fwnode_handle;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100216struct msi_domain_info;
217
218/**
219 * struct msi_domain_ops - MSI interrupt domain callbacks
220 * @get_hwirq: Retrieve the resulting hw irq number
221 * @msi_init: Domain specific init function for MSI interrupts
222 * @msi_free: Domain specific function to free a MSI interrupts
Jiang Liud9109692014-11-15 22:24:04 +0800223 * @msi_check: Callback for verification of the domain/info/dev data
224 * @msi_prepare: Prepare the allocation of the interrupts in the domain
Thomas Petazzoni1d1e8cd2015-12-21 14:13:08 +0100225 * @msi_finish: Optional callback to finalize the allocation
Jiang Liud9109692014-11-15 22:24:04 +0800226 * @set_desc: Set the msi descriptor for an interrupt
227 * @handle_error: Optional error handler if the allocation fails
228 *
229 * @get_hwirq, @msi_init and @msi_free are callbacks used by
230 * msi_create_irq_domain() and related interfaces
231 *
232 * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
Thomas Petazzoni1d1e8cd2015-12-21 14:13:08 +0100233 * are callbacks used by msi_domain_alloc_irqs() and related
Jiang Liud9109692014-11-15 22:24:04 +0800234 * interfaces which are based on msi_desc.
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100235 */
236struct msi_domain_ops {
Jiang Liuaeeb5962014-11-15 22:24:05 +0800237 irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info,
238 msi_alloc_info_t *arg);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100239 int (*msi_init)(struct irq_domain *domain,
240 struct msi_domain_info *info,
241 unsigned int virq, irq_hw_number_t hwirq,
Jiang Liuaeeb5962014-11-15 22:24:05 +0800242 msi_alloc_info_t *arg);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100243 void (*msi_free)(struct irq_domain *domain,
244 struct msi_domain_info *info,
245 unsigned int virq);
Jiang Liud9109692014-11-15 22:24:04 +0800246 int (*msi_check)(struct irq_domain *domain,
247 struct msi_domain_info *info,
248 struct device *dev);
249 int (*msi_prepare)(struct irq_domain *domain,
250 struct device *dev, int nvec,
251 msi_alloc_info_t *arg);
252 void (*msi_finish)(msi_alloc_info_t *arg, int retval);
253 void (*set_desc)(msi_alloc_info_t *arg,
254 struct msi_desc *desc);
255 int (*handle_error)(struct irq_domain *domain,
256 struct msi_desc *desc, int error);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100257};
258
259/**
260 * struct msi_domain_info - MSI interrupt domain data
Jiang Liuaeeb5962014-11-15 22:24:05 +0800261 * @flags: Flags to decribe features and capabilities
262 * @ops: The callback data structure
263 * @chip: Optional: associated interrupt chip
264 * @chip_data: Optional: associated interrupt chip data
265 * @handler: Optional: associated interrupt flow handler
266 * @handler_data: Optional: associated interrupt flow handler data
267 * @handler_name: Optional: associated interrupt flow handler name
268 * @data: Optional: domain specific data
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100269 */
270struct msi_domain_info {
Jiang Liuaeeb5962014-11-15 22:24:05 +0800271 u32 flags;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100272 struct msi_domain_ops *ops;
273 struct irq_chip *chip;
Jiang Liuaeeb5962014-11-15 22:24:05 +0800274 void *chip_data;
275 irq_flow_handler_t handler;
276 void *handler_data;
277 const char *handler_name;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100278 void *data;
279};
280
Jiang Liuaeeb5962014-11-15 22:24:05 +0800281/* Flags for msi_domain_info */
282enum {
283 /*
284 * Init non implemented ops callbacks with default MSI domain
285 * callbacks.
286 */
287 MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0),
288 /*
289 * Init non implemented chip callbacks with default MSI chip
290 * callbacks.
291 */
292 MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1),
Jiang Liuaeeb5962014-11-15 22:24:05 +0800293 /* Support multiple PCI MSI interrupts */
Thomas Gleixnerb6140912016-07-04 17:39:22 +0900294 MSI_FLAG_MULTI_PCI_MSI = (1 << 2),
Jiang Liuaeeb5962014-11-15 22:24:05 +0800295 /* Support PCI MSIX interrupts */
Thomas Gleixnerb6140912016-07-04 17:39:22 +0900296 MSI_FLAG_PCI_MSIX = (1 << 3),
Marc Zyngierf3b09462016-07-13 17:18:33 +0100297 /* Needs early activate, required for PCI */
298 MSI_FLAG_ACTIVATE_EARLY = (1 << 4),
Thomas Gleixner22d0b122017-09-13 23:29:13 +0200299 /*
300 * Must reactivate when irq is started even when
301 * MSI_FLAG_ACTIVATE_EARLY has been set.
302 */
303 MSI_FLAG_MUST_REACTIVATE = (1 << 5),
Marc Zyngier0be81532018-05-08 13:14:30 +0100304 /* Is level-triggered capable, using two messages */
305 MSI_FLAG_LEVEL_CAPABLE = (1 << 6),
Jiang Liuaeeb5962014-11-15 22:24:05 +0800306};
307
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100308int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
309 bool force);
310
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100311struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100312 struct msi_domain_info *info,
313 struct irq_domain *parent);
Jiang Liud9109692014-11-15 22:24:04 +0800314int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
315 int nvec);
316void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100317struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain);
318
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100319struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
Marc Zyngierc09fcc4b2015-07-28 14:46:16 +0100320 struct msi_domain_info *info,
321 struct irq_domain *parent);
322int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
323 irq_write_msi_msg_t write_msi_msg);
324void platform_msi_domain_free_irqs(struct device *dev);
Marc Zyngierb2eba392015-11-23 08:26:05 +0000325
326/* When an MSI domain is used as an intermediate domain */
327int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
328 int nvec, msi_alloc_info_t *args);
Marc Zyngier2145ac92015-11-23 08:26:06 +0000329int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
330 int virq, int nvec, msi_alloc_info_t *args);
Marc Zyngier552c4942015-11-23 08:26:07 +0000331struct irq_domain *
Marc Zyngier1f835152018-10-01 16:13:45 +0200332__platform_msi_create_device_domain(struct device *dev,
333 unsigned int nvec,
334 bool is_tree,
335 irq_write_msi_msg_t write_msi_msg,
336 const struct irq_domain_ops *ops,
337 void *host_data);
338
339#define platform_msi_create_device_domain(dev, nvec, write, ops, data) \
340 __platform_msi_create_device_domain(dev, nvec, false, write, ops, data)
341#define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \
342 __platform_msi_create_device_domain(dev, nvec, true, write, ops, data)
343
Marc Zyngier552c4942015-11-23 08:26:07 +0000344int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
345 unsigned int nr_irqs);
346void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
347 unsigned int nvec);
348void *platform_msi_get_host_data(struct irq_domain *domain);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100349#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
350
Jiang Liu3878eae2014-11-11 21:02:18 +0800351#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
352void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg);
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100353struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
Jiang Liu3878eae2014-11-11 21:02:18 +0800354 struct msi_domain_info *info,
355 struct irq_domain *parent);
Jiang Liu3878eae2014-11-11 21:02:18 +0800356irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
357 struct msi_desc *desc);
358int pci_msi_domain_check_cap(struct irq_domain *domain,
359 struct msi_domain_info *info, struct device *dev);
David Daneyb6eec9b2015-10-08 15:10:49 -0700360u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
Marc Zyngier54fa97e2015-10-02 14:43:06 +0100361struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
362#else
363static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
364{
365 return NULL;
366}
Jiang Liu3878eae2014-11-11 21:02:18 +0800367#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
368
Eric W. Biederman3b7d1922006-10-04 02:16:59 -0700369#endif /* LINUX_MSI_H */