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Mika Westerbergd16a5aa2014-03-20 22:04:23 +08001/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
Alan Cox093e00bb2014-04-18 19:17:40 +08009 * Author: Alan Cox <alan@linux.intel.com>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Mika Westerberg37670672015-11-18 13:25:18 +020016#include <linux/delay.h>
Thierry Redinge0c86a32014-08-23 00:22:45 +020017#include <linux/io.h>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080018#include <linux/kernel.h>
19#include <linux/module.h>
Qipeng Zhaf080be22015-10-26 12:58:27 +020020#include <linux/pm_runtime.h>
qipeng.zha883e4d02015-11-17 17:20:15 +080021#include <linux/time.h>
Alan Cox093e00bb2014-04-18 19:17:40 +080022
Andy Shevchenkoc558e392014-08-19 19:17:35 +030023#include "pwm-lpss.h"
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080024
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080029#define PWM_ON_TIME_DIV_MASK 0x000000ff
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080030
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030031/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080034struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
qipeng.zha883e4d02015-11-17 17:20:15 +080037 const struct pwm_lpss_boardinfo *info;
Alan Cox093e00bb2014-04-18 19:17:40 +080038};
39
Alan Cox093e00bb2014-04-18 19:17:40 +080040/* BayTrail */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030041const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030042 .clk_rate = 25000000,
43 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080044 .base_unit_bits = 16,
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080045};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030046EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080047
Alan Cox373c5782014-08-19 17:18:29 +030048/* Braswell */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030049const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030050 .clk_rate = 19200000,
51 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080052 .base_unit_bits = 16,
Alan Cox373c5782014-08-19 17:18:29 +030053};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030054EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
Alan Cox373c5782014-08-19 17:18:29 +030055
Mika Westerberg87219cb2015-10-20 16:53:06 +030056/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
qipeng.zha883e4d02015-11-17 17:20:15 +080060 .base_unit_bits = 22,
Mika Westerberg87219cb2015-10-20 16:53:06 +030061};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080064static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030069static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
Mika Westerberg37670672015-11-18 13:25:18 +020083static void pwm_lpss_update(struct pwm_device *pwm)
84{
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +020085 /*
86 * Set a limit for busyloop since not all implementations correctly
87 * clear PWM_SW_UPDATE bit (at least it's not visible on OS side).
88 */
89 unsigned int count = 10;
90
Mika Westerberg37670672015-11-18 13:25:18 +020091 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +020092 while (pwm_lpss_read(pwm) & PWM_SW_UPDATE && --count)
93 usleep_range(10, 20);
Mika Westerberg37670672015-11-18 13:25:18 +020094}
95
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +020096static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
97 int duty_ns, int period_ns)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080098{
Mika Westerbergab248b62016-06-10 15:43:21 +030099 unsigned long long on_time_div;
Andy Shevchenkod9cd4a72016-07-04 18:36:27 +0300100 unsigned long c = lpwm->info->clk_rate, base_unit_range;
qipeng.zha883e4d02015-11-17 17:20:15 +0800101 unsigned long long base_unit, freq = NSEC_PER_SEC;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800102 u32 ctrl;
103
104 do_div(freq, period_ns);
105
qipeng.zha883e4d02015-11-17 17:20:15 +0800106 /*
107 * The equation is:
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100108 * base_unit = round(base_unit_range * freq / c)
qipeng.zha883e4d02015-11-17 17:20:15 +0800109 */
Andy Shevchenko684309e2017-01-28 17:10:39 +0200110 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100111 freq *= base_unit_range;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800112
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100113 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800114
Mika Westerbergab248b62016-06-10 15:43:21 +0300115 on_time_div = 255ULL * duty_ns;
116 do_div(on_time_div, period_ns);
117 on_time_div = 255ULL - on_time_div;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800118
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300119 ctrl = pwm_lpss_read(pwm);
qipeng.zha883e4d02015-11-17 17:20:15 +0800120 ctrl &= ~PWM_ON_TIME_DIV_MASK;
Andy Shevchenko684309e2017-01-28 17:10:39 +0200121 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
122 base_unit &= base_unit_range;
qipeng.zha883e4d02015-11-17 17:20:15 +0800123 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800124 ctrl |= on_time_div;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300125 pwm_lpss_write(pwm, ctrl);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800126}
127
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +0200128static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
129 struct pwm_state *state)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800130{
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +0200131 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
Mika Westerberg37670672015-11-18 13:25:18 +0200132
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +0200133 if (state->enabled) {
134 if (!pwm_is_enabled(pwm)) {
135 pm_runtime_get_sync(chip->dev);
136 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
137 pwm_lpss_update(pwm);
138 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
139 } else {
140 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
141 pwm_lpss_update(pwm);
142 }
143 } else if (pwm_is_enabled(pwm)) {
144 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
145 pm_runtime_put(chip->dev);
146 }
147
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800148 return 0;
149}
150
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800151static const struct pwm_ops pwm_lpss_ops = {
Andy Shevchenkob14e8ce2017-01-28 17:10:41 +0200152 .apply = pwm_lpss_apply,
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800153 .owner = THIS_MODULE,
154};
155
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300156struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
157 const struct pwm_lpss_boardinfo *info)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800158{
159 struct pwm_lpss_chip *lpwm;
Andy Shevchenkod9cd4a72016-07-04 18:36:27 +0300160 unsigned long c;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800161 int ret;
162
Alan Cox093e00bb2014-04-18 19:17:40 +0800163 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800164 if (!lpwm)
Alan Cox093e00bb2014-04-18 19:17:40 +0800165 return ERR_PTR(-ENOMEM);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800166
Alan Cox093e00bb2014-04-18 19:17:40 +0800167 lpwm->regs = devm_ioremap_resource(dev, r);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800168 if (IS_ERR(lpwm->regs))
Thierry Reding89c03392014-05-07 10:27:57 +0200169 return ERR_CAST(lpwm->regs);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800170
qipeng.zha883e4d02015-11-17 17:20:15 +0800171 lpwm->info = info;
Andy Shevchenkod9cd4a72016-07-04 18:36:27 +0300172
173 c = lpwm->info->clk_rate;
174 if (!c)
175 return ERR_PTR(-EINVAL);
176
Alan Cox093e00bb2014-04-18 19:17:40 +0800177 lpwm->chip.dev = dev;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800178 lpwm->chip.ops = &pwm_lpss_ops;
179 lpwm->chip.base = -1;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300180 lpwm->chip.npwm = info->npwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800181
182 ret = pwmchip_add(&lpwm->chip);
183 if (ret) {
Alan Cox093e00bb2014-04-18 19:17:40 +0800184 dev_err(dev, "failed to add PWM chip: %d\n", ret);
185 return ERR_PTR(ret);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800186 }
187
Alan Cox093e00bb2014-04-18 19:17:40 +0800188 return lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800189}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300190EXPORT_SYMBOL_GPL(pwm_lpss_probe);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800191
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300192int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800193{
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800194 return pwmchip_remove(&lpwm->chip);
195}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300196EXPORT_SYMBOL_GPL(pwm_lpss_remove);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800197
198MODULE_DESCRIPTION("PWM driver for Intel LPSS");
199MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
200MODULE_LICENSE("GPL v2");