[clang-format] Parse Verilog if statements
This patch mainly handles treating `begin` as block openers.
While and for statements will be handled in another patch.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D123450
NOKEYCHECK=True
GitOrigin-RevId: 9ed2e68c9ae5cf346f938cc095e5448c1ff60f51
diff --git a/ClangFormat.cpp b/ClangFormat.cpp
index b85cb12..07110a0 100644
--- a/ClangFormat.cpp
+++ b/ClangFormat.cpp
@@ -79,7 +79,18 @@
"assume-filename",
cl::desc("Override filename used to determine the language.\n"
"When reading from stdin, clang-format assumes this\n"
- "filename to determine the language."),
+ "filename to determine the language.\n"
+ "Unrecognized filenames are treated as C++.\n"
+ "supported:\n"
+ " CSharp: .cs\n"
+ " Java: .java\n"
+ " JavaScript: .mjs .js .ts\n"
+ " Json: .json\n"
+ " Objective-C: .m .mm\n"
+ " Proto: .proto .protodevel\n"
+ " TableGen: .td\n"
+ " TextProto: .textpb .pb.txt .textproto .asciipb\n"
+ " Verilog: .sv .svh .v .vh"),
cl::init("<stdin>"), cl::cat(ClangFormatCategory));
static cl::opt<bool> Inplace("i",